chapter3 VHDL Syntax Fundamentals

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Library Declaration （库声明）:
LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL;
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Entity（实体） just like a device symbol
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Architecture（结构体）


Be used to describe the internal structure of design entity and the logic relationship between entity ports, that equivalents the internal structure of the circuit. Be composed of signal declaration and function description. Signal declaration：Declare signal name and type that will be used in the architecture;
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3.1.2 Program Structure
库声明 LIBRARY … 包声明 USE … ENTITY 实体名 IS PORT（端口名1：端口模式 数据类型； 实体 … ）； END 实体名； ARCHITECTURE 结构体名 OF 实体名 IS 结构体 结构体说明 BEGIN 并行语句； END 结构体名； 配置 14 configuration；
Chapter 3 VHDL Syntax Fundamentals
Introduction 3.1 Program Structure (基本结构) 3.2 Language Element （语言要素） 3.3 Concurrent Statement (并行语句) 3.4 Sequential Statement (顺序语句)
文件名、 实体名 一致
每行；结尾 关键字 end后跟 实体名
构造体
architecture dataflow of eqcomp4 is begin equal <= ‗1‘ when a=b else ‗0‘; End dataflow;
关键字 end后跟 构造体名
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Library、Package(库、程序包)
“Black-Box”
ENTITY entity_name is [ GENERIC( generic_declarations类属参数 说明) ; ] [ PORT( port_declarations端口说明) ; ] END entity_name ;
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A[3..0]
equal B[3..0]
VHDL 大小写不敏感 库 包 实体
eqcomp4.vhd
--eqcomp4 is a four bit equality comparator Library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; USE IEEE. std_logic_UNSIGNED.ALL; entity eqcomp4 is port(a, b:in std_logic_vector(3 downto 0); equal :out std_logic); end eqcomp4;
GENERIC( constant_name : type [ := value ] );
e.g. GENERIC(m：TIME：=1 ns); q<=tmp AFTER m; GENERIC 利用类属参数为tmp建立1ns延迟值
★灵活地改变参数以满足实际设计中的要求， 是GENERIC语句的关键用途
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Port Format
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注意：

双向（Inout）可代替所有其他模式，但降低了 程序的可读性，一般用于与CPU的数据总线接口。 如计算机PCI总线的地址/数据复用总线，DMA 控制器数据总线等纯双向的信号。
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Differences between OUT and BUFFER

Entity test1 is port(a: in std_logic; b,c: out std_logic ); end test1; architecture a of test1 is begin b <= not(a); c <= b； --Error end a;
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Introduction HDL Description
VHDL
Verilog
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Introduction
3
Introduction
4
Introduction
5
Introduction
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VHDL History
1980
- The USA Department of Defense (DoD)
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Entity －－ Port Format
PORT------the input/output of a block Name Mode Type PORT （端口名 ：端口模式 数据类型； 端口名 ：端口模式 数据类型； … …）；
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Port Format
Port MODE indicates the direction that data is transferred
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VHDL History
1987
- The DoD mandated that all digital circuits were described by VHDL. - IEEE-1076
- The F22 advanced tactical fighter aircraft. 1993
Function description：Describe logic behavior of entity.
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ARCHITECTURE architecture_name OF entity_name is {architecture_declarative_item } BEGIN { concurrent_statement并行处理语句} END [ architecture_name ] ;


Describe the Input/Output ports of a block （Port） In structural design, PORT is interface between modules ; In chip-level design, PORT represents specific pin of chips.
- IEEE 1076-1993
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VHDL History
1996
- Both commercial synthesis and simulation tools were available adhering to the IEEE 1076-1993 standard.
- A VHDL package for use with synthesis tools ( IEEE 1076.3) - IEEE 1076.4(VITAL): ASIC and FPGA library.
IN: Data goes into the entity only OUT: Data goes out of the entity only (and is not used internally) INOUT: Data is bi-directional (goes into and out of the entity) BUFFER: Data that goes out of the entity (and is also fedback internally)
Efficiency in design cycle time
Flexibility to adapting to design changes
Reuse of designs and package
Easy of various architectures and implementations Design verification and auto-regression tests

Entity test2 is port(a: in std_logic; b : buffer std_logic; c: out std_logic ); end test2; architecture a of test2 is begin b <= not(a); c <= b; end a;
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3.1 Program Structure (语法结构) 3.1.1 Syntax Rule 语法规则 3.1.2 Program Structure
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3.1.1 Syntax Rule 语法规则
Identifiers & comment & spaces
Not case-sensitive 不区分大小写 The semicolon（；） is used to indicate termination of a statement. ；作为结束符 Two dashes („--‟) are used to indicate the start of a comment. --表示注释 Identifiers must begin with a letter, subsequent characters can be alphanumeric, number or ‗_‘ (underscore). 标识符中第一个字符必须是字母，之后 可以由字母、数字、单个下划线组成 ‘_‘ (underscore) can‟t follow ‗_‘ (underscore) . 下划线不可以连续 Space can be used everywhere and can‟t affect the circuit function.