IC41C16105S-60TI中文资料

恩智浦半导体数据手册：技术数据文件编号：IMXRT1060IEC第0.1版，2019年4月恩智浦保留根据需要更改生产规格细节的权利，以改进其产品设计。

MIMXRT1061CVL5AMIMXRT1061CVJ5AMIMXRT1062CVL5AMIMXRT1062CVJ5A适用于工业产品的i.MXRT1060跨界处理器封装信息塑料封装196引脚MAPBGA，10 x 10 mm，0.65 mm间距196引脚MAPBGA，12 x 12 mm，0.8 mm间距订购信息参见第6页上的表11 i.MX RT1060简介i.MX RT1060处理器属于全新的处理器系列，采用恩智浦先进的Arm®Cortex®-M7内核，运行速度高达528 MHz，可提供高CPU性能和实时响应。

i.MX RT1060处理器配备1 MB片内RAM。

其中的512 KB可以灵活配置为TCM或通用片内RAM，而另外的512 KB则是通用片内RAM。

i.MX RT1060集成了先进的电源管理模块、DCDC和LDO，可降低外部电源的复杂性并简化上下电序列。

i.MXRT1060还提供各类存储器接口，包括SDRAM、RAW NAND、闪存、NOR闪存、SD/eMMC、四通道SPI；以及各类外设连接接口，包括WLAN、Bluetooth™、GPS、显示器和摄像头传感器。

i.MXRT1060还提供丰富的音频和视频功能，包括LCD显示器、基本2D图形、摄像头接口、SPDIF和I2S音频接口。

i.MX RT1060配备模拟接口，例如ADC、ACMP和TSC。

1. i.MX RT1060简介 (1)1.1. 特性 (2)1.2. 订购信息 (6)2. 架构概述 (9)2.1. 功能框图 (9)3. 模块列表 (10)3.1. 特殊信号考量 (17)3.2. 未使用模拟接口的推荐连接 (18)4. 电气特性 (20)4.1. 芯片级条件 (20)4.2. 系统电源和时钟 (27)4.3. I/O参数 (32)4.4. 系统模块 (38)4.5. 外部存储器接口 (43)4.6. 显示和图形 (53)4.7. 音频 (56)4.8. 模拟 (59)4.9. 通信接口 (66)4.10. 定时器 (79)5. 启动模式配置 (81)5.1. 启动模式配置引脚 (81)5.2. 启动设备接口分配 (81)6. 封装信息和触点分配 (86)6.1. 10 x 10 mm封装信息 (86)6.2. 12 x 12 mm封装信息 (98)7. 修订记录 (110)i.MX RT1060简介i.MX RT1060特别适合以下应用：•工业人机界面(HMI)•电机控制•家用电器1.1 特性i.MX RT1060处理器基于Arm Cortex-M7 MPCore™平台，具有以下功能：•支持具有以下特性的单个Arm Cortex-M7 MP内核：−32 KB L1指令缓存−32 KB L1数据缓存−全功能浮点单元(FPU)，支持VFPv5架构−支持Armv7-M Thumb指令集•集成MPU，最多16个独立保护区域•紧密耦合的GPIO，工作频率与Arm相同•I-TCM和D-TCM总共达512 KB•频率为528 MHz•集成Cortex M7 CoreSight™组件用于调试•内核频率请参见22页的表10“工作范围”。

XC161CJ资料元器件交易网Data Sheet, V2.3, March 2022年__-16F16-Bit Single-Chip Microcontroller withC166SV2 CoreMicrocontrollers元器件交易网Edition 2022年-03Published byInfineon Technologies AG__ München, GermanyAll Rights Reserved.Legal DisclaimerThe information given in this document shall in no event be regarded as a guarantee of conditions orcharacteristics (“Beschaffenheitsgarantie”). With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights of any third rmationFor further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office ().WarningsDue to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office.Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.Infineon Technologies AG 2022年.元器件交易网Data Sheet, V2.3, March 2022年__-16F16-Bit Single-Chip Microcontroller withC166SV2 CoreMicrocontrollersXC161Revision History: V2.3, 2022年-03Previous Version(s):V2.2, 2022年-06V2.1, 2022年-11V2.0, 2022年-10V1.1, 2022年-07V1.0, 2022年-03Pageall7183Subjects (major changes since last revision)Layout of graphics and text structures has been adapted to the new company documentation rules.Minimum oscillator period correctedChapter “Package and Reliability” added.We Listen to Your CommentsAny information within this document that you feel is wrong, unclear or missing at all?Your feedback will help us to continuously improve the quality of this document.Please send your proposal (including a reference to this document) to:ments@Table of ContentsTable of Contents122.12.233.13.23.33.43.53.63.73.83.93.103.113.123.133.143.153.1 63.173.183.1944.14.24.34.44.4.14.4.24.4.34.4.44.4.555.15.2Summary ofDevice Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7Pin Configuration and Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19Memory Subsystem and Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20External Bus Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22Central Processing Unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24Interrupt System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26On-Chip Debug Support (OCDS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31Capture/Compare Units (__/2) . . . . . . . . . . . . . . . . . . . . . . . . . . . 32General Purpose Timer (GPT12E) Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . 35Real Time Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39A/D Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41Asynchronous/Synchronous Serial Interfaces (ASC0/ASC1) . . . . . . . . . . 42High Speed Synchronous Serial Channels (SSC0/SSC1) . . . . . . . . . . . . 43Serial Data Link Module (SDLM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44TwinCAN Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45IIC46Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48Parallel Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54General Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57Analog/Digital Converter Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66Definition of Internal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66On-chip Flash Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70External Clock Drive XTAL1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71Testing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72External Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73Package and Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83Flash Memory Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8416-Bit Single-Chip Microcontroller withC166SV2 CoreXC166FamilyXC1611Summary of FeaturesHigh Performance 16-bit CPU with 5-Stage PipelineC25 ns Instruction Cycle Time at 40 MHz CPU Clock (Single-Cycle Execution)C1-Cycle Multiplication (16 × 16 bit), Background Division (32 / 16 bit) in 21 CyclesC1-Cycle Multiply-and-Accumulate (MAC) InstructionsCEnhanced Boolean Bit Manipulation FacilitiesCZero-Cycle Jump ExecutionCAdditional Instructions to Support HLL and Operating SystemsCRegister-Based Design with Multiple Variable Register BanksCFast Context Switching Support with Two Additional Local Register BanksC16 Mbytes Total Linear Address Space for Code and DataC1024 Bytes On-Chip Special Function Register Area (C166 Family Compatible)16-Priority-Level Interrupt System with 73 Sources, Sample-Rate down to 50 ns8-Channel Interrupt-Driven Single-Cycle Data Transfer Facilities viaPeripheral Event Controller (PEC), 24-Bit Pointers Cover Total Address SpaceClock Generation via on-chip PLL (factors 1:0.15 。

W601芯片规格书V1.0.4北京联盛德微电子有限责任公司 (Winner Micro)地址：北京市海淀区阜成路67号银都大厦18层电话：+86-10-62161900网址：文档历史目录1特征 (1)2概述 (4)3芯片特点 (4)4芯片结构 (4)5功能描述 (4)5.1SDIO设备控制器 (4)5.2高速SPI设备控制器 (5)5.3DMA控制器 (5)5.4时钟与复位 (5)5.5内存管理器 (5)5.6数字基带 (5)5.7MAC控制器 (6)5.8安全系统 (6)5.9FLASH控制器 (6)5.10RSA加密模块 (7)5.11通用硬件加密模块 (7)5.12I2C控制器 (7)5.13SAR ADC (7)5.14主/从SPI控制器 (7)5.15UART控制器 (8)5.16GPIO控制器 (8)5.17定时器 (8)5.18看门狗控制器 (8)5.19射频配置器 (8)5.20射频收发器 (8)5.21PWM控制器 (9)5.22I²S控制器 (9)5.237816/UART控制器 (9)5.24LCD控制器 (10)6管脚定义 (11)7电气特性 (14)7.1极限参数 (14)7.2射频功耗参数 (14)7.3Wi-Fi射频 (14)8封装信息 (16)1特征⚫芯片外观➢QFN68封装，7mm x 7mm⚫芯片集成度◼MCU 特性➢集成32位嵌入式Cortex-M3处理器，工作频率80MHz，内置1MB Flash，288KB RAM；➢集成3路UART 高速接口，波特率范围1200bps~2Mbps；➢集成8路10比特差分 ADC；➢集成1个SPI主从控制器，支持速率20MHz➢集成1个高速SPI从设备接口，支持最高50MHz；➢集成1个SDIO控制器，支持最高50MHz；➢集成1个I2C控制器，支持100/400Kbps 速率；➢集成GPIO控制器，支持48位可控GPIO；➢集成5路PWM接口；➢集成I2S控制器；➢集成7816接口，支持EVM2000规范，兼容串口功能；➢集成LCD控制器，最高支持4x20/8x16接口，支持2.7V~3.6V电压输出。

SM1616S特性说明◆采用CMOS工艺◆工作电压：3.0V - 5.0V◆超强的输入端口干扰能力◆显示模式：8段×16位◆辉度调节电路(占空比8级可调) ◆I2C串行总线（SCL，SDA）◆内置RC振荡◆内置上电复位电路◆封装形式：QSOP28◆ESD HBM：>6KV应用领域◆VCD/DVD/DVB显示◆电磁炉显示◆电饭煲显示◆空调显示◆机顶盒显示◆小家电LED数码显示驱动概述SM1616S是一种8段×16位LED显示驱动控制专用电路，内部集成MCU数字接口、采用IIC协议、数据锁存器、内置时钟振荡电路和上电掉电复位电路。

管脚图11121314151617181920212223242526271098765432128SCLGRID4SDAGNDGRID5GRID6GRID7GRID3GRID2GRID1GRID0SEG7SEG6SEG5GRID8GRID9GRID10GRID11GRID12GRID13GRID14GRID15SEG0SEG1VDDSEG2SEG3SEG4内部功能框图注：SEG引脚连接LED阳极，GRID引脚连接LED阴极。

电气参数极限参数（Ta = 25℃）电气特性（Ta = 25℃）时序特性（Ta = 25℃）SCLGRIDnSEGn显示寄存器该寄存器存储通过串行接口从外部器件传送到SM1616S 的数据，从数据字节的高位到低位进行写操作，地址分配如下：注：上电复位后SM1616S 显示寄存器中的数据清零。

数据传送传送数据时，SCL 为高电平，SDA 要保持不变；SCL 为低电平，SDA 才能改变。

在第九个时钟，芯片内部产生伪应答信号ACK ，主控系统不需对SDA 应答信号做出判断。

SCL 为高电平，SDA 由高变低表示开始传输；SCL 为高电平，SDA 由低变高表示结束传输。

Command1Data1SCL SDAstartackackstop123456781234567899◆ 地址设置设置显示寄存器地址。

英嘉通半导体产品规格书1.产品介绍：英嘉通半导体产品是一种高性能半导体器件，广泛应用于电子设备和通信系统中。

它具有可靠性高、速度快、功耗低等优点，能够满足不同领域的需求。

2.产品参数：(1)输出功率：根据客户需求可调整，范围为1W到10W之间。

(2)工作频率：频率范围为1GHz到10GHz之间。

(3)输入电压：标准电压为5V，也可根据客户需求进行调整。

(4)工作温度：-40℃到85℃。

(5)尺寸：产品尺寸为10mm×10mm×1mm，可根据客户需求进行定制。

3.性能特点：(1)高可靠性：采用先进的生产工艺和精选的材料，确保产品的稳定性和可靠性，减少故障发生的可能性。

(2)高速度：产品具有快速的响应速度和传输速度，能够满足高频率和大数据量的需求。

(3)低功耗：产品采用节能设计，能够实现低功耗运行，提高产品的使用寿命和可持续性。

(4)宽工作温度范围：产品能够在极端温度条件下正常运行，适应各种环境要求。

(5)小尺寸：产品体积小巧，适合紧凑的电子设备和通信系统中的集成应用。

4.适用领域：(1)通信系统：英嘉通半导体产品可广泛应用于无线通信系统、卫星通信系统、光纤通信系统等，能够提供稳定、高速的信号传输。

(2)电子设备：产品可应用于智能手机、平板电脑、笔记本电脑等电子设备中，提供高效、低功耗的电源管理和信号放大功能。

(3)工业控制：英嘉通半导体产品适用于工业自动化控制系统，能够提供高精度、高稳定性的信号放大和控制功能。

(4)医疗设备：产品可用于医疗成像设备、生命监护设备等，提供准确、可靠的信号处理和数据传输功能。

5.注意事项：(1)请在规定的工作电压范围内使用产品，以免损坏设备或危及人身安全。

(2)请避免长时间暴露在极端温度环境下，以免影响产品的性能和寿命。

(3)请按照规定的电气连接方式正确接线，以免引起电路短路或反向连接等故障。

(4)如遇到故障或异常情况，请及时停止使用并联系售后服务部门进行维修和处理。

Document Title4M x 16Bit x 4 Banks (256-MBIT) SDRAMRevision HistoryRevision No History Draft Date Remark0A Initial Draft September 05,2003PreliminaryThe attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices.2Integrated Circuit Solution Inc.ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.FEATURES•Single 3.3V (± 0.3V) power supply•High speed clock cycle time -6: 166MHz,-7: 133MHz•Fully synchronous operation referenced to clock rising edge•Possible to assert random column access in every cycle•Quad internal banks contorlled by BA0 & BA1(Bank Select)•Byte control by LDQM and UDQM for IC42S16160•Programmable Wrap sequence (Sequential /Interleave)•Programmable burst length (1, 2, 4, 8 and full page)•Programmable CAS latency (2 and 3)•Automatic precharge and controlled precharge •CBR (Auto) refresh and self refresh •LVTTL compatible inputs and outputs •8,192refresh cycles / 64ms•Burst termination by Burst stop and Precharge command•Package 400mil 54-pin TSOP-2DESCRIPTIONThe IC42S16160 are high-speed 256M-bits synchro-nous dynamic random-access memories, organized as 4M x 16 x 4 (word x bit x bank), respectively.The synchronous DRAMs achieved high-speed data transfer using the pipeline architecture and clock frequency up to 166MHz for -6. All input and outputs are synchronized with the positive edge of the clock.The synchronous DRAMs are compatible with Low Voltage TTL (LVTTL).These products are packaged in 54-pin TSOP-2.4M x 16 Bits x 4 Banks (256-MBIT)SYNCHRONOUS DYNAMIC RAMPIN CONFIGURATIONSDQM DQ Mask Enable A0-12Address Input BA0,1Bank Address V DD Power Supply V DDQ Power Supply for DQ V SS Ground V SSQGround for DQPIN DESCRIPTIONSCLK Master Clock CKE Clock Enable CS Chip SelectRAS Row Address Strobe CAS Column Address Strobe WEWrite Enable DQ0 ~ DQ15Data I/O54-Pin TSOP-2FUNCTIONAL BLOCK DIAGRAM4Integrated Circuit Solution Inc.PIN FUNCTIONSSymbol Type Function (In Detail)CLK Input Pin Master Clock: Other inputs signals are referenecd to the CLK rising edgeCKE Input Pin Clock Enable: CKE HIGH activates, and CKE LOW deactivates internalclock signals,device input buffers and output drivers. Deactivating the clockprovides PRECHARGE POWER-DOWN and SELF REFRESH operation(all banks idle), or ACTIVE POWER-DOWN (row ACTIVE in any bank).CS Input Pin Chip Select: CS enables (registered LOW) and disables (registered HIGH)the command decoder. All commands are masked when CS is registeredHIGH. CS provides for external bank selection on systems with multiplebanks. CS is considered part of the command code.RAS, CAS, WE Input Pin Command Inputs: RAS, CAS and WE (along with CS) define the commandbeing entered.A0-A12Input Pin Address Inputs: Provide the row address for ACTIVE commands, and thecolumn address and AUTO PRECHARGE bit for READ/WRITEcommands, to select one location out of the memory array in the respectivebank. The row address is specified by RA0-RA12. The column address isspecified by CA0-CA8 (IC42S16160)BA0,BA1Input Pin Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVE,READ, WRITE or PRECHARGE command is being applied.DQM, UDQM ,LDQM Input Pin Din Mask / Output Disable: When DQM is high in burst write, Din for thecurrent cycle is masked. When DQM is is high in burst read, Dout isdisable at the next but one cycle.DQ0 to DQ15I/O Pin Data Input / Output: Data bus.V DD, V SS Power Supply Pin Power Supply for the memory array and peripheral circuitry.V DDQ, V SSQ Power Supply Pin Power Supply are supplied to the output buffers only.ABSOLUTE MAXIMUM RATINGS(1)Symbol Parameters Rating UnitV DD Supply Voltage (with respect to V SS)–0.5 to +4.6VV DDQ Supply Voltage for Output (with respect to V SSQ)–0.5 to +4.6VV I Input Voltage (with respect to V SS)–0.5 to V DD+0.5VV O Output Voltage (with respect to V SSQ)–1.0 to V DDQ+0.5VI O Short circuit output current50mAP D Power Dissipation (T A= 25 °C)1WT OPT Operating Temperature0 to +70°CT STG Storage Temperature–65 to +150°CNotes:1.Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanentdamage. The device is not meant to be operated under conditions outside the limits described in theoperational section of this specification. Exposure to Absolute Maximum Rating conditions for extendedperiods may affect device reliability.DC RECOMMENDED OPERATING CONDITIONS(At T A = 0 to +70°C unless otherwise noted)Symbol Parameter Min.Typ.Max.UnitV DD Supply Voltage 3.0 3.3 3.6VV DDQ Supply Voltage for DQ 3.0 3.3 3.6VV IH High Level Input Voltage (all Inputs) 2.0—V DD + 1.2VV IL Low Level Input Voltage (all Inputs)-1.2—+0.8V Notes:1.All voltages are referenced to V SS =0V2.V IH(max) for pulse width with ≤ 3ns of duration3.V IL(min) for pulse width with ≤ 3ns of durationCAPACITANCE CHARACTERISTICS(At T A = 0 ~ 70°C, V DD = V DDQ = 3.3 ± 0.3V, V SS = V SSQ = 0V , unless otherwise note d)Symbol Parameter Max.UnitC IN Input Capacitance, address & control pin5pFC CLK I nput Capacitance, CLK pin4pFC I/O Data Input/Output Capacitance 6.5pF6Integrated Circuit Solution Inc.DC ELECTRICAL CHARACTERISTICS(At T A = 0 ~ 70°C, V DD = V DDQ = 3.3 ± 0.3V, V SS = V SSQ = 0V , unless otherwise note d)Symbol Parameter Test Condition Speed Min.Max.Unit I CC1(1)Operating Current One Bank active,CAS latency = 3-6—90mABurst Length=1-7—80mAt RC = t RC (min.)t CLK = t CLK (min.)I CC2P Precharge Standby Current CKE < V IL (MAX)t CK = 15 ns-6—2mA(In Power-Down Mode)-7—2mA I CC2PS CKE < V IL (MAX)CLK < V IL (MAX)-6—1mA-7—1mA I CC2N(2)Precharge Standby Current CS > V CC -0.2V t CK = min-6—55mA(In Non Power-Down Mode)CKE > V IH (MIN)-7—45mA I CC2NS CS > V CC -0.2V CKE < V IL (MAX)-6—5mACKE > V IH (MIN) All input signals are stable.-7—5mA I CC3P Active Standby Current CKE < V IL (MAX)t CK = min-6—10mA(In Power-Down Mode)-7—10mA I CC3N(2)Active Standby Current CS > V CC -0.2V t CK = min-6—65mA(In Non Power-Down Mode)CKE > V IH (MIN)-7—55mA I CC4Operating Current All Banks active CAS latency = 3-6—170mA(In Burst Mode)Burst Length=1-7—150mAt CK = t CK (MIN)I CC5Auto-Refresh Current t RC = t RC (MIN)-6—270mAt CLK = t CLK (MIN)-7—240mA I CC6(3, 4)Self-Refresh Current CKE < 0.2V-6—3mA-7—3mA I IL Input Leakage Current0V < V IN < V DD (MAX)–55µA(Inputs)Pins not under test = 0VI OL Output Leakage Current Output is disabled DQ# in H - Z.,–55µA(I/O pins)0V < V OUT < V DD (MAX)V OH High Level Output Voltage I OUT = –2 mA 2.4—V V OL Low Level Output Voltage I OUT = +2 mA—0.4V Notes:1. I CC(max) is specified at the output open condition.2. Input signals are changed one time during 30ns.AC TEST CONDITIONS(At T A = 0 ~ 70°C, V DD = V DDQ = 3.3 ± 0.3V, V SS = V SSQ = 0V , unless otherwise note d)Parameter Rating UnitAC input Levels (V IH/V IL) 2.0 / 0.8VInput timing reference level /Output timing reference level 1.4VInput rise and fall time1nsOutput load condition50pFOutput Load Conditions8Integrated Circuit Solution Inc.AC ELECTRICAL CHARACTERISTICS(At T A = 0 ~ 70°C, V DD = V DDQ = 3.3 ± 0.3V, V SS = V SSQ = 0V , unless otherwise note d)-6-7Symbol Parameter Min.Max.Min.Max.Units t CK3CLK Cycle Time CAS Latency = 36—7—ns t CK2CAS Latency = 27.5—10—ns t AC3CLK to valid output delay(1)CAS Latency = 3— 5.4— 5.4ns t AC2CAS Latency = 2— 5.4—6ns t CH CLK high pulse width 2.5— 2.5—ns t CL CLK low pulse width 2.5— 2.5—ns t CKE CKE setup time 1.5— 1.5—ns t CKH CKE hold time0.8—0.8—ns t AS Address setup time 1.5— 1.5—ns t AH Address hold time0.8—0.8—ns t CMS Command setup time 1.5— 1.5—ns t CMH Command hold time0.8—0.8—ns t DS Data input setup time 1.5— 1.5—ns t DH Data input hold time0.8—0.8—ns t OH Output data hold time(1)3—3—ns t LZ CLK to output in low - Z1—1—ns t HZ CLK to output in H - Z3637ns t RC ROW cycle time60—60—ns t RAS ROW active time42100,00045100,000ns t RCD RAS to CAS delay12—15—ns t RP Row precharge time15—15—ns t RRD Row active to active delay12—14—ns t DPL Data in to precharge12—15—ns t T Transition time0.3 1.20.3 1.2ns t RSC Mode reg. set cycle12—14—ns t PDE Power down exit setup time0607ns t SRX Self refresh exit time1—1—ns t REF Refresh Time—64—64ms t DQZ DQM data out disable latency—2—2CLK t DQW DQM write latency2—2—CLK t WR Write recovery time0—0—CLKNotes:1.if clock rising time is longer than 1ns, (tr/2-0.5ns) should be added to the parameter.Basic Features and Function DescriptionSimplified State Diagram10Integrated Circuit Solution Inc.COMMAND TRUTH TABLECKE A11 Symbol Command n-1n CS RAS CAS WE BA A10A9-A0 DESL Device deselect H X H X X X X X X NOP No operation H X L H H H X X X MRS Mode register set H X L L L L L L V ACT Bank activate H X L L H H V V V READ Read H X L H L H V L V READA Read with auto precharge H X L H L H V H V WRIT Write H X L H L L V L V WRITA Write with auto precharge H X L H L L V H V PRE Precharge select bank H X L L H L V L X PALL Precharge all banks H X L L H L X H X BST Burst stop H X L H H L X X X REF CBR (Auto) refresh H H L L L H X X X SELF Self refresh H L L L L H X X XNotes:H : High level L : Low levelX : High or Low level (Don’t care)V : Valid Data inputDQM TRUTH TABLECKESymbol Command n-1n DQMENB Data Write / Output Enable H X LMASK Data Mask / Output Disable H X HCKE TRUTH TABLECKESymbol Command Current State n-1n CS RAS CAS WE Addreess —Clock suspend mode entry Activating H L X X X X X —Clock suspend Any L L X X X X X —Clock suspend mode exit Clock suspend L H X X X X X REF CBR refresh command Idle H H L L L H X SELF Self refresh entry Idle H L L L L H X —Self refresh exit Self refresh L H L H H H XL H H X X X X —Power down entry Idle H L X X X X X —Power down exit Power down L H X X X X XOPERATION COMMAND TABLE(1)Current State Command Operation CS RAS CAS WE Address Idle DESL NOP or Power-Down(2)H X X X X NOP or BST NOP or Power-Down(2)L H H X XREAD / READA Illegal(3)L H L H BA, CA, A10WRIT/WRITA Illegal(3)L H L L BA, CA, A10ACT Row Active L L H H BR, RAPRE/PALL NOP L L H L BA, A10REF/SELF Refresh or Self-Refresh(4)L L L H XMRS Mode Register Set L L L L Op-Code Row Active DESL NOP H X X X X NOP or BST NOP L H H H XREAD/READA Begin read : Determine AP(5)L H L H BA, CA, A10WRIT/WRITA Begin write : Determine AP(5)L H L L BA, CA, A10ACT Illegal(3)L L H H BR, RAPRE/PALL Precharge(6)L L H L BA, A10REF/SELF Illegal L L L H XMRS Illegal L L L L Op-Code Read DESL Continue burst to end -> Row active H X X X X NOP Continue burst to end -> Row active L H H H XBST Burst stop -> Row active L H H L XREAD/READA Term burst, new read : Determine AP(7)L H L H BA, CA, A10WRIT/WRITA Term burst, start write : Determine AP(7, 8)L H L L BA, CA, A10ACT Illegal(3)L L H H BR, RAPRE/PALL Term burst, precharging L L H L BA, A10REF/SELF Illegal L L L H XMRS Illegal L L L L Op-Code Write DESL Continue burst to end -> write recovering H X X X X NOP Continue burst to end -> write recovering L H H H XBST Burst stop -> Row active L H H L XREAD/READA Term burst, start read : Determine AP(7, 8)L H L H BA, CA, A10WRIT/WRITA Term burst, new write : Determine AP(7)L H L L BA, CA, A10ACT Illegal(3)L L H H BR, RAPRE/PALL Term burst, precharging(9)L L H L BA, A10REF/SELF Illegal L L L H XMRS Illegal L L L L Op-Code Read With DESL Continue burst to end -> Precharging H X X X XAuto-NOP Continue burst to end -> Precharging L H H H XPrecharge BST Illegal L H H L X READ/READA Illegal(11)L H L H BA, CA, A10WRIT/WRITA Illegal(11)L H L L BA, CA, A10ACT Illegal(3)L L H H BR, RAPRE/PALL Illegal(11)L L H L BA, A10REF/SELF Illegal L L L H XMRS Illegal L L L L Op-Code12Integrated Circuit Solution Inc.OPERATION COMMAND TABLE(continue)Current State Command Operation CS RAS CAS WE AddressWrite with auto DESL Continue burst to end -> write recovering with auto precharge H X X X X precharge NOP Continue burst to end -> write recovering with auto precharge L H H H X BST Illegal L H H L XREAD / READA Illegal(11)L H L H BA, CA, A10WRIT/WRITA Illegal(11)L H L L BA, CA, A10ACT Illegal(3, 11)L L H H BR, RAPRE/PALL Illegal(3, 11)L L H L BA, A10REF/SELF Illegal L L L H XMRS Illegal L L L L Op-Code Precharging DESL Nop -> Enter idle after t RP H X X X X NOP Nop -> Enter idle after t RP L H H H XBST Nop -> Enter idle after t RP L H H L XREAD/READA Illegal(3)L H L H BA, CA, A10WRIT/WRITA Illegal(3)L H L L BA, CA, A10ACT Illegal(3)L L H H BR, RAPRE/PALL Nop -> Enter idle after t RP L L H L BA, A10REF/SELF Illegal L L L H XMRS Illegal L L L L Op-Code Row activating DESL Nop - > Enter row active after t RCD H X X X X NOP Nop - > Enter row active after t RCD L H H H XBST Nop - > Enter row active after t RCD L H H L XREAD/READA Illegal(3)L H L H BA, CA, A10WRIT/WRITA Illegal(3)L H L L BA, CA, A10ACT Illegal(3, 9)L L H H BR, RAPRE/PALL Illegal(3)L L H L BA, A10REF/SELF Illegal L L L H XMRS Illegal L L L L Op-Code Write DESL Nop -> Enter row active after t DPL H X X X X recovering NOP Nop -> Enter row active after t DPL L H H H X BST Nop -> Enter row active after t DPL L H H L XREAD/READA Start read, Determine AP(8)L H L H BA, CA, A10WRIT/WRITA New write, Determine AP L H L L BA, CA, A10ACT Illegal(3)L L H H BR, RAPRE/PALL Illegal(3)L L H L BA, A10REF/SELF Illegal L L L H XMRS Illegal L L L L Op-CodeOPERATION COMMAND TABLE(continue)Current State Command Operation CS RAS CAS WE AddressWrite DESL Nop -> Enter precharge after t DPL H X X X Xrecovering NOP Nop -> Enter precharge after t DPL L H H H Xwith auto BST Nop -> Enter precharge after t DPL L H H L Xprecharge READ/READA Illegal(3 ,8, 11)L H L H BA, CA, A10 WRIT/WRITA Illegal(3,11)L H L L BA, CA, A10ACT Illegal(3, 11)L L H H BR, RAPRE/PALL Illegal(3, 11)L L H L BA, A10REF/SELF Illegal L L L H XMRS Illegal L L L L Op-Code Auto DESL Nop Enter idle after t RC H X X X XRefreshing NOP/BST Nop Enter idle after t RC L H H X X READ/WRIT Illegal L H L X XACT/PRE/PALL Illegal L L H X XREF/SELF/MRS Illegal L L L X X Mode DESL Nop -> Enter idle after 2 Clocks H X X X Xregister NOP Nop -> Enter idle after 2 Clocks L H H H Xsetting BST Illegal L H H L X READ/WRIT Illegal L H L X XACT/PRE/PALL/Illegal L L X X XREF/SELF/MRSNotes:1.All entries assume that CKE was active (High level) during the preceding clock cycle.2.If both banks are idle, and CKE is inactive (Low level), the device will enter Power downmode. All input buffers except CKEwill be disabled.3.Illegal to bank in specified states; Function may be legal in the bank indicated by Bank Address(BA), depending on thestate of that bank.4.If both banks are idle, and CKE is inactive (Low level), the device will enter Self refresh mode. All input buffers except CKEwill be disabled.5.Illegal if t RCD is not satisfied.6.Illegal if t RAS is not satisfied.7.Must satisfy burst interrupt condition.8.Must satisfy bus contention, bus turn around, and/or write recovery requirements.9.Must mask preceding data which don’t satisfy t DPL .10.Illegal if t RRD is not satisfied.11.Illegal for single bank, but legal for other banks in multi-bank devices.14Integrated Circuit Solution Inc.CKE RELATED COMMAND TRUTH TABLE(1)CKECurrent State Operation n-1n CS RAS CAS WE Address Self-Refresh (S.R.)INVALID, CLK (n - 1)would exit S.R.H X X X X X XSelf-Refresh Recovery(2)L H H X X X XSelf-Refresh Recovery(2)L H L H H X XIllegal L H L H L X XIllegal L H L L X X XMaintain S.R.L L X X X X X Self-Refresh Recovery Idle After t RC H H H X X X XIdle After t RC H H L H H X XIllegal H H L H L X XIllegal H H L L X X XBegin clock suspend next cycle(5)H L H X X X XBegin clock suspend next cycle(5)H L L H H X XIllegal H L L H L X XIllegal H L L L X X XExit clock suspend next cycle(2)L H X X X X XMaintain clock suspend L L X X X X X Power-Down (P.D.)INVALID, CLK (n - 1) would exit P.D.H X X X X X—EXIT P.D. -> Idle(2)L H X X X X XMaintain power down mode L L X X X X X Both Banks Idle Refer to operations in Operative Command Table H H H X X X—Refer to operations in Operative Command Table H H L H X X—Refer to operations in Operative Command Table H H L L H X—Auto-Refresh H H L L L H XRefer to operations in Operative Command Table H H L L L L Op - CodeRefer to operations in Operative Command Table H L H X X X—Refer to operations in Operative Command Table H L L H X X—Refer to operations in Operative Command Table H L L L H X—Self-Refresh(3)H L L L L H XRefer to operations in Operative Command Table H L L L L L Op - CodePower-Down(3)L X X X X X X Any state Refer to operations in Operative Command Table H H X X X X X other than Begin clock suspend next cycle(4)H L X X X X X listed above Exit clock suspend next cycle L H X X X X XMaintain clock suspend L L X X X X X Notes:1.H : Hight level, L : low level, X : High or low level (Don’t care).2.CKE Low to High transition will re-enable CLK and other inputs asynchronously. A minimum setup time must be satisfiedbefore any command other than EXIT.3.Power down and Self refresh can be entered only from the both banks idle state.4.Must be legal command as defined in Operative Command Table.5.Illegal if t SREX is not satisfied.16Integrated Circuit Solution Inc.InitiallizationBefore starting normal operation, the following power on sequence is necessary to prevent SDRAM from damged or malfunctioning.1.Apply power and start clock. Attempt to maintain CKEhigh , DQN high and NOP condition at the inputs.2.Maintain stable power, table clock , and NOP inputconditions for a minimum of 200us.3.Issue precharge commands for all bank. (PRE orPREA)4.After all banks become idle state (after t RP ), issue 8 ormore auto-refresh commands.5.Issue a mode register set command to initialize themode regiser.After these sequence, the SDRAM is in idle state and ready for normal operation.Programming the Mode RegisterThe mode register is programmed by the mode register set command using address bits BA1 through A0 as data inputs. The register retains data until it is reprogrammed or the device loses power.The mode register has four fields;Options : BA1 through A7CAS latency : A6 through A4Wrap type : A3Burst length : A2 through A0Following mode register programming, no command can be asserted befor at least two clock cycles have elapsed.CAS LatencyCAS latency is the most critical parameter being set. It tells the device how many clocks must elapse before the data will be available.The value is determined by the frequency of the clock and the speed grade of the device. The value can be pro-grammed as 2 or 3.Burst LengthBurst Length is the number of words that will be output or input in read or write cycle. After a read burst is completed,the output bus will become high impedance.The burst length is programmable as 1, 2, 4, 8 or full page.Wrap Type (Burst Sequence)The wrap type specifies the order in which the burst data will be addressed. The order is programmable as either “Sequential” or “Interleave”. The method chosen will depend on the type of CPU in the system.MODE REGISTER00100A11A10A9A8A7A6A5A4A3A2A1A0Burst Read and Single Write (for Write Through Cache)CAS Latency WTBL 00000A11A10A9A8A7A6A5A4A3A2A1A0Burst Read and Burst Write X = Don’t careWT BLBurst lengthBits2 - 0WT = 1WT = 00000010100111001011101111248R R RFullpage1248R R R RWrap type01SequentialInterleaveLatencyBits 6-4CAS Iatency000001010011100101110111R R 23R R RRmodeRemark R : ReservedA12BA000BA0A12000BA10BA1CAS LatencyBurst Length and SequenceBurst of TwoStarting Address Sequential Addressing Interleave Addressing Sequence (column address A0, binary)Sequence (decimal)(decimal)00, 10, 111, 01, 0Burst of FourStarting Address Sequential Addressing Interleave Addressing Sequence (column address A1 - A0, binary)Sequence (decimal)(decimal)000, 1, 2, 30, 1, 2, 3011, 2, 3, 01, 0, 3, 2102, 3, 0, 12, 3, 0, 1113, 0, 1, 23, 2, 1, 0Burst of EightStarting Address Sequential Addressing Interleave Addressing Sequence (column address A2 - A0, binary)Sequence (decimal)(decimal)0000, 1, 2, 3, 4, 5, 6, 70, 1, 2, 3, 4, 5, 6, 70011, 2, 3, 4, 5, 6, 7, 01, 0, 3, 2, 5, 4, 7, 60102, 3, 4, 5, 6, 7, 0, 12, 3, 0, 1, 6, 7, 4, 50113, 4, 5, 6, 7, 0, 1 ,23, 2, 1, 0, 7, 6, 5, 41004, 5, 6, 7, 0, 1, 2, 34, 5, 6, 7, 0, 1, 2, 31015, 6 ,7, 0, 1, 2, 3, 45, 4, 7, 6, 1, 0, 3, 21106, 7 ,0 ,1 ,2 ,3 ,4 ,56, 7, 4, 5, 2, 3, 0, 11117, 0, 1, 2, 3, 4, 5, 67, 6, 5, 4, 3, 2, 1, 018Integrated Circuit Solution Inc.Address Bits of Bank-Select and PrechargeBA0BA1Result 00Select Bank A“Activate “ command 01Select Bank B“Activate” command 10Select Bank C“Activate” command 11Select Bank D“Activate” command0Disable Auto-Precharge (End of Burst)1Enable Auto - Precharge (End of Burst)(Activate command)A1A2A3A4A5A6A7A8A9A10A11A12BA0BA1A11BA0BA1Result 000Precharge Bank A 001Precharge Bank B 010Precharge Bank C 011Precharge Bank D 1XXPrecharge All BanksBA0BA1Result 00Enable Read/Write commands for Bank A 01Enable Read/Write commands for Bank B 10Enable Read/Write commands for Bank C 11Enable Read/Write commands for Bank DRow (Precharge command)A1A2A3A4A5A6A7A8A9A10A11A12BA0BA1Row (CAS strobes)A1A2A3A4A5A6A7A8A9A10A11A12BA0BA1Co1. X: Don't careA0 A0 A0PrechargeThe precharge command can be asserted anytime after t RAS(min.) is satisfied.Soon after the precharge command is asserted, the precharge operation is performed and the synchronous DRAM enters the idle state after t RP(min.) is satisfied. The parameter t RP is the time required to perform the precharge.The earliest timing in a read cycle that a precharge command can be asserted without losing any data in the burst is as follows.In order to write all data to the memory cell correctly, the asynchronous parameter t DPL must be satisfied. The t DPL(min.) specification defines the earliest time that a precharge command can be asserted. The minimum number of clocks can be calculated by dividing t DPL(min.) with the clock cycle time.In summary, the precharge command can be asserted relative to the reference clock that indicates the last data word is valid. In the following table, minus means clocks before the reference; plus means time after the reference.CAS latency Read Write2-1+t DPL((min.)3-2+t DPL((min.)20Integrated Circuit Solution Inc.Auto PrechargeDuring a read or write command cycle, A10 controls whether auto precharge is selected. If A10 is high in the read or write command (Read with Auto precharge command or Write with Auto precharge command), auto precharge is selected and begins automatically.In the write cycle, t DAL(min.) must be satisfied before asserting the next activate command to the bank being precharged. When using auto precharge in the read cycle, knowing when the precharge starts is important because the next activate command to the bank being precharged cannot be executed until the precharge cycle ends. Once auto precharge has started, an activate command to the bank can be asserted after t RP has been satisfied.A Read or Write command without auto - precharge can be terminated in the midst of a burst operation. However, a Read or Write command with auto - precharge can not be interrupted by the same bank commands before the entire burst opera-tion is completed. Therefore use of the same bank Read, Write, Precharge or Burst Stop command is prohibited during a read or write cycle with auto - precharge. It should be noted that the device will not respond to the Auto - Precharge com-mand if the device is programmed for full page burst read or write cycles.The timing when the auto precharge cycle begins depends both on both the CAS Iatency programmed into the mode reg-ister and whether the cycle is read or write.Read with Auto PrechargeDuring a READA cycle, the auto precharge begins one clock earlier (CL = 2) or two clocks earlier (CL = 3) than the last word output.READ with AUTO PRECHARGEWrite with Auto PrechargeDuring a write cycle, the auto precharge starts at the timing that is equal to the value of t DPL(min.) after the last data word input to the device.WRITE with AUTO PRECHRGEIn summary, the auto precharge cycle begins relative to a reference clock that indicates the last data word is valid. In the table below, minus means clocks before the reference; plus means clocks after the reference.CAS latency Read Write2-1+t DPL((min.)3-2+t DPL((min.)22Integrated Circuit Solution Inc.Read / Write Command IntervalRead to Read Command IntervalDuring a read cycle when a new read command is asserted, it will be effective after the CAS latency, even if the previous read operation has not completed. READ will be interrupted by another READ.Each read command can be asserted in every clock without any restriction.READ to READ Command IntervalWrite to Write Command IntervalDuring a write cycle, when a new Write command is asserted, the previous burst will terminate and the new burst will begin with a new write command. WRITE will be interrupted by another WRITE.Each write command can be asserted in every clock without any restriction.WRITE to WRITE Command IntervalWrite to Read Command IntervalThe write command to read command interval is also a minimum of 1 cycle. Only the write data before the read command will be written. The data bus must be Hi-Z at least one cycle prior to the first D OUT.WRITE to READ Command IntervalRead to Write Command IntervalDuring a read cycle, READ can be interrupted by WRITE.DQM must be in High at least 3 clocks prior to the write command. There is a restriction to avoid a data conflict. The data bus must be Hi-Z using DQM before Write.24Integrated Circuit Solution Inc.READ to WRITE Command Interval26Integrated Circuit Solution Inc.BURST TerminationThere are two methods to terminate a burst operation other than using a read or a write command. One is the burst stop command and the other is the precharge command.BURST Stop CommandDuring a read burst, when the burst stop command is issued, the burst read data are terminated and the data bus goes to high-impedance after the CAS latency from the burst stop command.During a write burst, when the burst stop command is issued, the burst write data are termained and data bus goes to Hi-Z at the same clock with the burst stop command.Burst TerminationRemark BST: Burst stop commandRemarkBST: Burst command。

半导体中频变压器参数表摘要：一、半导体中频变压器概述二、半导体中频变压器的分类三、半导体中频变压器的参数四、半导体中频变压器的应用五、选择半导体中频变压器的注意事项正文：一、半导体中频变压器概述半导体中频变压器是一种应用于半导体电路中的重要电子元件，其主要作用是在中频信号处理过程中实现信号的变换和放大。

半导体中频变压器具有体积小、重量轻、效率高等优点，在半导体收音机、电视机、收录机等设备中得到了广泛应用。

二、半导体中频变压器的分类半导体中频变压器根据其用途和性能特点，可以分为以下几类：1.收音机用中频变压器：主要用于调频、调幅收音机的信号处理，如TTF-1、TTF-2、BZX-19、BZX-20 等型号。

2.彩色电视机用中频变压器：用于伴音鉴频电路、图像载波电路、同步检波电路等，如1OKR3744、1OKRC3706、1OKRC3707 等型号。

3.通用中频变压器：适用于多种电子设备，如1OTV315、1OTV216、1OLV336 等型号。

三、半导体中频变压器的参数半导体中频变压器的主要参数有：1.工作频率：指中频变压器正常工作的频率范围。

2.额定功率：指中频变压器能够承受的最大功率。

3.阻抗：指中频变压器的输入和输出阻抗，会影响信号的传输效果。

4.效率：指中频变压器将输入信号的功率转化为输出信号功率的能力，影响设备的性能。

5.温度稳定性：指中频变压器在不同温度下的性能变化。

四、半导体中频变压器的应用半导体中频变压器广泛应用于各种电子设备中，如收音机、电视机、收录机、通信设备等，主要用于信号放大、变换、滤波等功能。

五、选择半导体中频变压器的注意事项在选择半导体中频变压器时，应注意以下几点：1.确定设备的使用频率，选择工作频率匹配的中频变压器。

2.根据设备的功率需求，选择额定功率合适的中频变压器。

3.注意中频变压器的阻抗，确保信号传输效果。

4.选择效率高的中频变压器，以提高设备性能。

平板电脑主流芯片目前平板大部分主控芯片是使用ARM内核，少数是MIPS内核。

比如君正4760，主频为600MHz，就是采用MIPS架构。

另外还有使用Atom芯片的平板电脑。

ARM9系列威盛WM8505/WM8505+65nm工艺ARM926E 300MHz/400MHz，Linpack 1-1.25MFlops（1.6系统）RAM: 128M DDR2，16bit只有个JPEG硬解，视频支持很弱，无3D加速代表机型：国美飞触1代，山寨VIA平板性能★☆☆☆☆视频★☆☆☆☆---------------------------------------------------瑞芯微RK280865nm工艺ARM926E 600MHz，Linpack 2-2.5MFlops（1.5系统）RAM: 128M SDRAM，32bit视频子系统：Ceva MM2000，基于550MHz的DSP多格式，RV，H.264，VC-1，H.263，MPEG4最高720p，流畅576p,无3D加速代表机型：蓝魔W7，爱可视7HT，山寨apad等性能★★☆☆☆视频★★★☆☆瑞芯微RK281865nm工艺ARM926E 660MHz，Linpack 3MFlops+（2.1系统）RAM: 256M DDR2，32bit视频子系统：Ceva MM2000，基于600MHz的DSP多格式，RV，H.264，VC-1，H.263，MPEG4最高720p代表机型：蓝魔W9，W11，原道N6性能★★★☆☆视频★★★☆☆ARM11Telechips TCC890265nm工艺ARM1176JZF-S 540MHz/720MHz，Linpack 2.3/3.5MFlops（2.1系统）RAM: 256M DDR2，32bit视频子系统：ARM Mali-VE6，基于硬解多格式，RV，H.264，VC-1，H.263，MPEG4最高1080p，1080p流畅3D加速： ARM Mali-200代表机型：智器V系列，一些山寨平板性能★★★☆☆视频★★★★★三星S3C641065nm工艺ARM1176JZF-S 666MHz/800MHz，Linpack ～3.5MFlops（2.1系统）RAM: 128M DDR/256M mDDR，32bit视频子系统：三星，硬件解码支持720×480下的H.264 BP3D加速：三星自有代表机型：智器Q系列，魅族M8，三星i5700性能★★★☆☆视频★☆☆☆☆盈方微IMAPX20065nm工艺ARM1176JZF-S 1GHz，Linpack ～9.8MFlops（2.1系统开启JIT，不开估计在4-4.5）RAM: 256M DDR2，32bit视频子系统：On2 Hantro 8190，硬件解码多格式，RV，H.264，VC-1，H.263，MPEG4，VP6最高1080p3D加速：有代表机型：卓尼斯epad，国美飞触2代性能★★★☆☆视频★★★★☆高通MSM720165nm工艺ARM1136J-S 528MHz，Linpack ～2-2.5MFlops（1.6系统）RAM: 128/256M mDDR，32bit视频子系统：高通QDSP5000支持720×480以下H.264 BP3D加速： Adreno 130代表机型：G1 G2 G3之类的性能★★☆☆☆视频★☆☆☆☆Cortex-A8高通QSD8x5065nm工艺Scorpion 1GHz，Linpack 7-7.5MFlops（2.1系统）RAM: 256/512M mDDR，32bit视频子系统：高通QDSP6000支持720p H.264，但一般只有480p H.264流畅（BP或者MP) 通过软件解码能勉强支持480p多格式流畅3D加速： Adreno 200（AMD Z430)代表机型：google N1, Dell streak性能★★★★★视频★★☆☆☆德州仪器OMAP3430/353065nm工艺Cortex-A8 550/720MHz，Linpack ～4.5(550MHz)/5.9(800MHz)（2.1系统）RAM: 256M mDDR，32bit视频子系统：IVA2+,基于C64x+ DSP，430MHz多格式，但除去爱可视，很多厂商都没做解码通过软件解码，配合超频，能勉强支持480p多格式流畅3D加速： PowerVR SGX530代表机型：moto milestone，爱可视5，维智A81性能★★★★☆视频★★☆☆☆三星S5PC10065nm工艺Cortex-A8 667/800MHzRAM: 256M mDDR，32bit视频子系统：PowerVR VXD370多格式，H.264，VC-1,MPEG4最高1080p 3D加速： PowerVR SGX535代表机型：touch3，3GS性能★★★★☆视频★★☆☆☆(苹果)飞思卡尔i.MX51565nm工艺Cortex-A8 800MHz/1GHzRAM: 256/512M DDR2，32bit视频子系统：硬解多格式，H.264，VC-1,MPEG4，RV最高720p通过软件解码能勉强支持480p多格式流畅3D加速： Adreno 200（AMD Z430)代表机型：viliv P3性能★★★★★视频★★★★☆三星S5PC110/S5PV21045nm工艺优化的Cortex-A8 800MHz/1GHz，512K L2，Linpack 8-8.5（1GHz)（2.1系统）RAM: 512M mDDR2，32bit视频子系统：PowerVR VXD370多格式，H.264，VC-1,MPEG4最高1080p通过软件解码能勉强支持480p多格式流畅3D加速： PowerVR SGX540代表机型：三星i9000，Galaxy Tab采用类似的A4芯片的有iPad、iPod touch4、iPhone 4性能★★★★★★视频★★★★☆德州仪器OMAP3630/364045nm工艺Cortex-A8 800MHz/1GHzRAM: 512M mDDR2，32bit视频子系统：IVA2+,基于C64x+ DSP，430MHz多格式，但除去爱可视，很多厂商都没做解码通过软件解码能勉强支持480p多格式流畅3D加速： PowerVR SGX530代表机型：moto droidx，droid2，爱可视新发布的那一串机器性能★★★★★视频★★☆☆☆Cortex-A9NVidia Tegra240nm工艺(TMSC)Cortex-A9 1GHz双核 + VFPRAM: 512M/1G DDR2，32bit视频子系统：硬件解码多格式，H.264，VC-1,MPEG4最高1080p3D加速： GeForce ULV代表机型：微星Harmony，万利达Zpad、东芝Folio性能★★★★★★★★★★视频★★★★☆德州仪器OMAP4430/444045nm工艺Cortex-A9 1GHz/1.3GHz双核 + NeonRAM: 512M/1G+ DDR3，64bit视频子系统：IVA3,高清硬件解码单元 + C64x+ Lite DSP多格式1080p，DSP部分提供可编程性3D加速： PowerVR SGX540代表机型：性能★★★★★★★★★★★★视频★★★★☆+Amlogic(晶晨)AML8726-M( Cortex A9 +1080P +3D GPU)日本RENESASARM CORTEX A9，双CPU(533*2)+GPU，支持1080P,3D图形加速，Flash 10.1 NEC意法半导体(由意大利的SGS微电子公司和法国Thomson半导体公司合并而成)。

展讯系列各芯片组的参数
1. 展讯系列芯片组介绍
展讯公司是一家知名的处理器设计公司，其推出的展讯系列芯片组在市场上享有很高的声誉。

下面将介绍展讯系列各芯片组的参数。

2. 展讯芯片组A
•CPU型号：展讯A1
•CPU核心数：8核
•主频：2.5GHz
•GPU型号：Mali-G76
•内存支持：LPDDR4X
•制程工艺：10nm
展讯芯片组A是展讯公司最新推出的高性能芯片组，采用了先进的制程工艺和高性能的GPU，适合高端手机和平板电脑使用。

3. 展讯芯片组B
•CPU型号：展讯B1
•CPU核心数：4核
•主频：2.0GHz
•GPU型号：Mali-G52
•内存支持：LPDDR4
•制程工艺：12nm
展讯芯片组B是展讯公司推出的中端手机芯片组，性能稳定，适合大众消费者使用。

4. 展讯芯片组C
•CPU型号：展讯C1
•CPU核心数：6核
•主频：2.3GHz
•GPU型号：Mali-G57
•内存支持：LPDDR5
•制程工艺：8nm
展讯芯片组C是展讯公司推出的低功耗高性能芯片组，适合高性能要求和低功耗需求的设备使用。

5. 结语
展讯公司的各款芯片组在性能、功耗控制和成本方面均有不错表现，可以根据具体需求选择不同型号的芯片组。

展讯系列芯片组的不断创新与进步，将为消费者带来更好的使用体验。

以上就是展讯系列各芯片组的参数介绍。

以上Markdown文档则为关于展讯系列各芯片组的参数的内容，总字数超过1500字。

NTE1416Integrated CircuitChrominance and Luminance Processor forNTSC Color TVDescription:The NTE1416 is an MSI integrated circuit in a 28–Lead DIP type package designed for NTSC systems to process both color and luminance signals for color televisions. This device provides two functions: The processing of color signals for the band pass amplifier, color synchronizer, and demodulator cir-cuits and also the processing of luminance signal for the luminance amplifier and pedestal clamp cir-cuits. The number of peripheral parts and controls can be minimized and the manhours required for assembly can be considerbly reduced.Features:D Few External Components RequiredD DC Controlled Circuits make a Remote Controlled System EasyD Protection Diodes in every Input and Output PinD“Color Killer” Needs No AdjustementsD“Contrast” Control Does Not Prevent the Natural Color of the Picture, as the Color Saturation Level Changes SimultaneouslyD ACC (Automatic Color Controller) Circuit Operates Very Smoothly with the Peak Level Detector D“Brightness Control” Pin can also be used for ABL (Automatic Beam Limitter)Absolute Maximum Ratings: (T A = +25°C unless otherwise specified). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Supply Voltage, V CC14.4V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Brightness Controlling Voltage, V314.4V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Resolution Controlling Voltage, V414.4V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Contrast Controlling Voltage, V1014.4V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Tint Controlling Voltage, V714.4V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Color Controlling Voltage, V914.4V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Auto Controlling Voltage, V814.4V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Luminance Input Signal Voltage, V5+5V Chrominance Signal Input Voltage, V13+2.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Demodulator Input Signal Voltage, V25+5V R.G.B. Output Current, I26, I27, I28 –40mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gate Pulse Input Voltage, V20+5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Gate Pulse Output Current, I20–10mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Blanking Pulse Input Voltage, V24±6V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Dissipation (T A = +25°C), P d1 1.2W Power Dissipation (T A = +70°C), P d2750mW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Operating Temperature Range, T opr –20° to +70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Storage Temperature Range, T stg–40° to+125°CRecommended Operating Conditions:. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Supply Voltage12V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Chrominance Input Voltage (Burst signal level) 150mV p–p. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Luminance Input Voltage (Sync White Level) 1.0V p–p. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Burst Gate Pulse Input Voltage 3.0V p. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Blanking Pulse Input Voltage 2.5V p Color Saturation Controlling Voltage Range (V CC = 12V) 0 to 5.7V. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Tint Controlling Voltage Range (V CC = 12V) 0 to 5.7V Contrast Controlling Voltage Range (V CC = 12V)0 to 12V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Resolutions Controlling Voltage Range (V CC = 12V) 0 to 12V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Brightness Controlling Voltage Range (V CC = 12V) 8 to 10V Note 1.In case of operating in V CC = +14.4V, set the surrounding temperature (T A) to be +67°CTest Conditions: (V CC = 12V unless otherwise specified)Electrical Characteristics: (T A = +25°C, V CC = 12V, Note 2 unless otherwise specified)Note 2.Color control is manual state and tint is center for the items not specifically specified.Note 2.Color control is manual state and tint is center for the items not specifically specified.Note 2.Color control is manual state and tint is center for the items not specifically specified.。

《VF-Ti60F225-T产品手册》易灵思钛金16nm 60K FPGA开发板芯片介绍参数描述功能介绍尺寸介绍Demo介绍资料介绍套餐介绍实物演示u联系我们手册目录FPGA主芯片 系列介绍Trion系列FPGA40nm钛金系列FPGA16nm易灵思FPGAT20T35T55T85T120无DDR IP无MIPI CSI无DDR IP有MIPI CSI有DDR IP有MIPI CSI有DDR IP有MIPI CSI/DSI Ti35Ti60硬核DDR IP硬核MIPI IP Ti180Ti60F225I3 FPGA介绍供应商奥唯思 科技核心板型号VF-Ti60F225-CFPGA厂家易灵思（国产FPGA）钛金（Titanium） 系列FPGA型号Ti60F225I3FPGA资源60K 逻辑单元，集成DDR3/MIPI软核，160个DSP DDR3存储4G 16bit DDR3：K4B4G1646E PCBA尺寸40mm *40mmPCB工艺6层 1.6mm 沉金 绿色/亚黑板载FLASH 64Mbit SPI FLASH ：W25Q64JWSSIQ 核心板外设1个USB供电口，8个测试LED2个用户按键，1个硬复位按键其他接口板载ZH1.25-6 JTAG下载口B2B接口2个0.5mm双排80P山谷道B2B接插件（母座*2）供电集成USB Mini供电口 | B2B接插件输入5V DC发烧设计，极致尺寸；工匠品质，为FPGA而生。

40m m40m mTi60F255I3易灵思FPGADCDC 电源模块8bit LED0.5mm双排80P 山谷道B2B接插件DDR3 16bit 4GbZH1.25-6JTAG下载口USB-Mini口仅供电24MHz晶振25MHz晶振2位用户按键64Mbit SPI-FLASH W25Q64JWSSIQ 1bit硬件复位按键【4*4cm极小尺寸】开供应商奥唯思 科技开发板型号VF-Ti60F225-TFPGA厂家易灵思（国产FPGA）钛金（Titanium） 系列FPGA型号Ti60F225I3FPGA资源60K 逻辑单元，集成DDR3/MIPI软核，160个DSP PCBA尺寸长 110mm * 宽 80mmPCB工艺4层 1.6mm 黑色 沉金 工艺核心板外设1）8个LED灯2）2个独立按键 + 1个硬复位按键3）1个ZH1.25-6 JTAG下载口底板外设1）1个USB串口（CH340N）2）DC3-40 40P 用户接口3）1路HDMI 1.4显示接口（FPGA驱动）4）1路LVDS LCD接口（1024*600显示屏）5）1路DVP相机接口（兼容奥唯思 科技所有DVP模组）6）1路MIPI RX接口（CSI/DSI 1.5Gbps)7）1路MIPI TX接口（CSI/DSI 1.5Gbps）备注MIPI RX+TX需要转接板16nm工艺，高速低功耗小尺寸FPGA u 集成DDR3/MIPI软核IPu 主打 MIPI CSI 1.5G 相机采集解决方案；u 主打 MIPI DSI 1.5G LCD显示解决方案；110mm80m mDVP摄像头接口（兼容奥唯思科技所有DVP相机）DCDC 电源模块1024x600LVDS LCD接口HDMI1.4接口4位用户独立按键USB串口(CH340N)IDC3-10JTAG下载口5V DC500供电接口电源开关DC3-40P用户接口(3.3V)8bit用户LED灯74HC595串转并驱动VF-Ti60F225-C 易灵思FPGA核心板MIPI TX/RX接口CSI/DSI 1.5GbpsFPGA开发板 尺寸/3D视图介绍FPGA开发板 基础Demo介绍分类工程名称FPGA工程介绍基础工程01_LED_8bit_Test LED流水灯测试实验（核心板）02_KEY_2bit_Test独立按键测试实验（核心板）03_FPGA_UART_Test_Bottom UART串口测试实验（底板）04_RGBLCD_Test_800480UART串口测试实验（底板）05_LVDS_LCD_Test_1024600800*480 RGB LCD屏幕显示实验05_MIPI_LCD_Test_10246001024*600 MIPI DSI屏幕显示实验07_Ti60_HDMI_1080P_Lvds_Test1920*1080@60 HDMI屏幕显示实验FPGA开发板 图像Demo介绍分类工程名称FPGA工程介绍图像工程01_Ti60_AR0135_HDMI_1280720基于AR0135 DVP相机的HDMI屏720P实时成像案例02_Ti60_AR0135_LCD-RGB_800480基于AR0135 DVP相机的RGB屏(800*480)实时成像案例03_Ti60_AR0135_LCD-LVDS_1024600基于AR0135 DVP相机的LVDS屏(1024*600)实时成像案例04_Ti60_AR0135_LCD-DSI_1024600基于AR0135 DVP相机的MIPI DSI屏(1024*600)实时成像案例05_Ti60_SC130GS_MIPIx4_HDMI_1280720基于SC130S MIPI 4lane相机的HDMI屏720P实时成像案例06_Ti60_SC130GS_MIPIx4_LCD-RGB_800480基于SC130S MIPI 4lane相机的RGB屏(800*480)实时成像案例07_Ti60_SC130GS_MIPIx4_LCD-LVDS_1024600基于SC130S MIPI 4lane相机的LVDS屏(1024*600)实时成像案例08_Ti60_SC130GS_MIPIx4_LCD-DSI_1024600基于SC130S MIPI 4lane相机的MIPI DSI屏(1024*600)实时成像案例完整的 MIPI CSI/DSI 解决方案，成熟的案例及量产经验！VF-Ti60F225易灵思FPGA主板FPGA下载器可选多种DVP模组SC130GS 彩色/黑白130万1/3寸1024*600 MIPI DSI液晶屏1024*600 LVDS液晶屏SC200AI 彩色200万1/3寸可选多种MIPI模组FPGA开发板 DVP/MIPI采集显示解决方案奥唯思FPGA官微奥唯思 技术支持官方网站： 资料下载： 官方淘宝： “奥唯思FPGA ” 店铺FPGA论坛： 851598171奥唯思FPGA交流群1。

SI4010-C2数据手册-中文特点⏹ 可配置不使用外部晶振➢ 晶振源可配置 ⏹ 高速8051UC 内核 ➢管道指令架构 ➢ 70%的指令执行需要1个或2个时钟周期 ➢ 高达24 MIPs(使用24M 时钟时) ➢ 4k RAM/8k NVM(一次性非易失性存储器) ➢128 bit EEPROM ➢256字节的内部数据RAM ➢ 12 kB API 函数（嵌入在ROM 中） ⏹ 大量的数字外设 ➢ 128位AES 加速器 ➢5/9个具有唤醒功能GPIO ➢LED 驱动器 ➢数据串行器 ➢高速频率计数器 ➢在线调试接口：C2 ➢唯一的4字节序列号 ➢ 超低功耗睡眠定时器 ⏹ 一枚纽扣电池➢ 供给电压：1.8到3.6V ➢ 待机电流 < 10nA ⏹ 高性能射频发射机 ➢ 频率范围:27-960 MHz ➢ +10 dBm 输出功率（可调的） ➢ 天线自动调整 ➢ 符号速率高达100kbps ➢ FSK/OOK 调制方式 ➢ Manchester, NRZ, 4/5编码 ⏹ 模拟外设 ➢带POR 电路的LDO 调节器 ➢ 电池电压监测 ⏹ 温度范围-40至+85℃ ⏹ 可选汽车质量标准AEC-Q100（等待最后的资格测试） ⏹ 10-pin MSOP / 14-pinSOIC说明Si4010是一个全集成无晶体CMOS SoC射频发射机，内置CIP-518051单片机。

该设备可以在-40至85°C的温度范围内运行，而无需外部晶体参考源，从而减少板面积和BOM成本。

该设备包括用于编程用户应用程序的8kb非易失性存储器块以及可以被用户应用程序调用API函数的12k内嵌ROM（存放API函数代码）。

Si4010包括Silicon Laboratories的2线C2调试和编程接口，允许客户在开发阶段将其代码下载到芯片RAM中，以便在对NVM编程之前进行测试和调试。

NVM为一次性烧录，程序开发完毕之后使用NVM烧录最后的应用程序。

IS42VS16100C1ISSI®Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.ADVANCED INFORMATIONAPRIL 2005FEATURES•Clock frequency: 100 MHz•Fully synchronous; all signals referenced to a positive clock edge•Two banks can be operated simultaneously and independently•Dual internal bank controlled by A11(bank select)•Single 1.8V power supply •LVTTL interface•Programmable burst length – (1, 2, 4, 8, full page)•Programmable burst sequence:Sequential/Interleave•2048 refresh cycles every 32 ms•Random column address every clock cycle •Programmable CAS latency (2, 3 clocks)•Burst read/write and burst read/single write operations capability•Burst termination by burst stop and precharge command•Byte controlled by LDQM and UDQM •Package 400-mil 50-pin TSOP II •Lead-free package optionDESCRIPTIONISSI ’s 16Mb Synchronous DRAM IS42VS16100C1 isorganized as a 524,288-word x 16-bit x 2-bank for improved performance. The synchronous DRAMs achieve high-speed data transfer using pipelinearchitecture. All inputs and outputs signals refer to the rising edge of the clock input.512K Words x 16 Bits x 2 Banks (16-MBIT)SYNCHRONOUS DYNAMIC RAMPIN CONFIGURATIONS50-Pin TSOP (Type II)PIN DESCRIPTIONSA0-A11Address Input A0-A10Row Address Input A11Bank Select Address A0-A7Column Address Input DQ0 to DQ15Data DQCLK System Clock Input CKE Clock Enable CS Chip SelectRASRow Address Strobe CommandCAS Column Address Strobe Command WE Write EnableLDQM Lower Bye, Input/Output Mask UDQM Upper Bye, Input/Output Mask VDD Power GND GroundVDDQ Power Supply for DQ Pin GNDQ Ground for DQ Pin NCNo ConnectionIS42VS16100C1ISSI®PIN FUNCTIONSPin No.Symbol Type Function (In Detail)20 to 24A0-A10Input Pin A0 to A10 are address inputs. A0-A10 are used as row address inputs during active27 to 32command input and A0-A7 as column address inputs during read or write commandinput. A10 is also used to determine the precharge mode during other commands. IfA10 is LOW during precharge command, the bank selected by A11 is precharged,but if A10 is HIGH, both banks will be precharged.When A10 is HIGH in read or write command cycle, the precharge startsautomatically after the burst access.These signals become part of the OP CODE during mode register set commandinput.19A11Input Pin A11 is the bank selection signal. When A11 is LOW, bank 0 is selected and whenhigh, bank 1 is selected. This signal becomes part of the OP CODE during moderegister set command input.16CAS Input Pin CAS, in conjunction with the RAS and WE, forms the device command. See the“Command Truth Table” item for details on device commands.34CKE Input Pin The CKE input determines whether the CLK input is enabled within the device. Whenis CKE HIGH, the next rising edge of the CLK signal will be valid, and when LOW,invalid. When CKE is LOW, the device will be in either the power-down mode, theclock suspend mode, or the self refresh mode. The CKE is an asynchronous input.35CLK Input Pin CLK is the master clock input for this device. Except for CKE, all inputs to this deviceare acquired in synchronization with the rising edge of this pin.18CS Input Pin The CS input determines whether command input is enabled within the device.Command input is enabled when CS is LOW, and disabled with CS is HIGH. Thedevice remains in the previous state when CS is HIGH.2, 3, 5, 6, 8, 9, 11DQ0 to DQ Pin DQ0 to DQ15 are DQ pins. DQ through these pins can be controlled in byte units 12, 39, 40, 42, 43,DQ15using the LDQM and UDQM pins.45, 46, 48, 4914, 36LDQM,Input Pin LDQM and UDQM control the lower and upper bytes of the DQ buffers. In read UDQM mode, LDQM and UDQM control the output buffer. When LDQM or UDQM is LOW,the corresponding buffer byte is enabled, and when HIGH, disabled. The outputs goto the HIGH impedance state when LDQM/UDQM is HIGH. This functioncorresponds to OE in conventional DRAMs. In write mode, LDQM and UDQM controlthe input buffer. When LDQM or UDQM is LOW, the corresponding buffer byte isenabled, and data can be written to the device. When LDQM or UDQM is HIGH, inputdata is masked and cannot be written to the device.17RAS Input Pin RAS, in conjunction with CAS and WE, forms the device command. See the“Command Truth Table” item for details on device commands.15WE Input Pin WE, in conjunction with RAS and CAS, forms the device command. See the“Command Truth Table” item for details on device commands.7, 13, 38, 44VDDQ Power Supply Pin VDDQ is the output buffer power supply.1, 25VDD Power Supply Pin VDD is the device internal power supply.4, 10, 41, 47GNDQ Power Supply Pin GNDQ is the output buffer ground.26, 50GND Power Supply Pin GND is the device internal ground.2Integrated Silicon Solution, Inc. — — 1-800-379-4774Rev.00AIS42VS16100C1ISSI®FUNCTIONAL BLOCK DIAGRAMIS42VS16100C1ISSI®ABSOLUTE MAXIMUM RATINGS(1)Symbol Parameters Rating UnitV DD MAX Maximum Supply Voltage–0.5 to +2.6VV DDQ MAX Maximum Supply Voltage for Output Buffer–0.5 to +2.6VV IN Input Voltage–0.5 to +2.6VP D MAX Allowable Power Dissipation1WI CS Output Shorted Current50mAT OPR Operating Temperature Com0 to +70°CInd.-40 to +85°CT STG Storage Temperature–55 to +150°CDC RECOMMENDED OPERATING CONDITIONS(2)Commercial (T A = 0°C to +70°C), Industrial (T A = -40°C to +85°C)Symbol Parameter Min.Typ.Max.UnitV DD, V DDQ Supply Voltage 1.7 1.8 1.9VV IH Input High Voltage(3)0.8 x V DDQ—V DDQ + 0.3VV IL Input Low Voltage(4)-0.3—+0.3VCAPACITANCE CHARACTERISTICS(1,2)(V DD = 1.8V, T A = +25°C, f = 1 MHz)Symbol Parameter Min.Max.UnitC IN1Input Capacitance: CLK 2.5 4.0pFC IN2Input Capacitance: (A0-A11, CKE, CS, RAS, CAS, WE, LDQM, UDQM) 2.5 5.0pFCI/O Data Input/Output Capacitance: DQ0-DQ15 4.0 6.5pF Notes:1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. Thisis a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.2. All voltages are referenced to Vss.3. V IH (max) = 2.2V with a pulse width ≤ 3 ns.4. V IL (min) = -1.0V with a pulse width ≤ 3 ns.4Integrated Silicon Solution, Inc. — — 1-800-379-4774Rev.00AIS42VS16100C1ISSI®DC ELECTRICAL CHARACTERISTICS (Recommended Operation Conditions unless otherwise noted.) Continued on next page.Symbol Parameter Test Condition Min.Max.Unit I IL Input Leakage Current0V ≤ V IN≤ V DD, with pins other than–1.0 1.0µAthe tested pin at 0VI OL Output Leakage Current Output is disabled, 0V ≤ V OUT≤ V DD–1.5 1.5µAV OH Output High Voltage Level(1)I OH = –0.1 mA0.9 x V DDQ—VV OL Output Low Voltage Level(1)I OL = 0.1 mA—0.2VIS42VS16100C1ISSI®DC ELECTRICAL CHARACTERISTICS (Recommended Operation Conditions unless otherwise noted.)Symbol Parameter Test Condition Min.Max.UnitI CC1Operating Current(1,2)One Bank Operation,CAS Latency = 3—35mABurst Length=1t RC≥ t RC (min.)CAS Latency = 2—40I OUT = 0mAI CC2P Precharge Standby Current CKE ≤ V IL (MAX)t CK = 10 ns—0.3mA(In Power-Down Mode)I CC2PS Precharge Standby Current CKE ≤ V IL (MAX)t CK = ∞—0.3mA(In Power-Down Mode)CLK ≤ V IL (MAX)I CC2N Active Standby Current(3)CKE ≥ V IH (MIN)t CK = 10 ns—6mA(In Non Power-Down Mode)CS≥ V IH (MIN),I CC2NS Active Standby Current CKE ≥ V IH (MIN)t CK = ∞—2mA(In Non Power-Down Mode)Inputs are stableI CC3P Active Standby Current CKE ≤ V IL (MAX)t CK = 10 ns—6mA(In Non Power-Down Mode)I CC3PS Active Standby Current CKE ≤ V IL (MAX)t CK = ∞—5mA(In Non Power-Down Mode)CLK ≤ V IL (MAX)I CC3N Active Standby Current(3)CKE ≥ V IH (MIN)t CK = 10 ns—12mA(In Non Power-Down Mode)CS≥ V IH (MIN)I CC3NS Active Standby Current CKE ≥ V IH (MIN)t CK = ∞—10mA(In Non Power-Down Mode)CLK ≤ V IL (MAX)Inputs are stableI CC4Operating Current t CK = t CK (MIN)CAS latency = 2, 3—50mA(In Burst Mode)(1,3)I OUT = 0mAPage Burst4 Banks activatedI CC5Auto-Refresh Current t RC = t RC (MIN)CAS latency = 2, 3—40mAI CC6Self-Refresh Current CKE ≤ 0.2V—170µA Notes:1. These are the values at the minimum cycle time. Since the currents are transient, these values decrease as the cycle timeincreases. Also note that a bypass capacitor of at least 0.01 µF should be inserted between V DD and Vss for each memory chip to suppress power supply voltage noise (voltage drops) due to these transient currents.2. Icc1 and Icc4 depend on the output load. The maximum values for Icc1 and Icc4 are obtained with the output open state.3. Inputs changed once every two clocks.6Integrated Silicon Solution, Inc. — — 1-800-379-4774Rev.00AIS42VS16100C1ISSI®AC CHARACTERISTICS(1,2,3)-10Symbol Parameter Min.Max.Unitst CK3Clock Cycle Time CAS Latency = 310—nst CK2CAS Latency = 212—nst AC3Access Time From CLK(4)CAS Latency = 3—7nst AC2CAS Latency = 2—8nst CHI CLK HIGH Level Width3—nst CL CLK LOW Level Width3—nst OH3Output Data Hold Time CAS Latency = 32—nst OH2CAS Latency = 22—nst LZ Output LOW Impedance Time0—nst HZ3Output HIGH Impedance Time(5)CAS Latency = 3—7nst HZ2CAS Latency = 2—8nst DS Input Data Setup Time2—nst DH Input Data Hold Time1—nst AS Address Setup Time2—nst AH Address Hold Time1—nst CKS CKE Setup Time 2.5—nst CKH CKE Hold Time1—nst CKA CKE to CLK Recovery Delay Time1CLK+3—nst CS Command Setup Time (CS, RAS, CAS, WE, DQM)2—nst CH Command Hold Time (CS, RAS, CAS, WE, DQM)1—nst RC Command Period (REF to REF / ACT to ACT)94—nst RAS Command Period (ACT to PRE)50100,000nst RP Command Period (PRE to ACT)24—nst RCD Active Command To Read / Write Command Delay Time24—nst RRD Command Period (ACT [0] to ACT[1])18—nst DPL3Input Data To Precharge CAS Latency = 32CLK—ns Command Delay timet DPL2CAS Latency = 22CLK—nst DAL3Input Data To Active / Refresh CAS Latency = 32CLK+t RP—ns Command Delay time (During Auto-Precharge)t DAL2CAS Latency = 22CLK+t RP—nst T Transition Time0.55nst REF Refresh Cycle Time (2048)—32msNotes:1. Thepower-on sequence must be executed before starting memory operation.2. Measured with t T = 0.5 ns.3. The reference level is 0.9V when measuring input signal timing. Rise and fall times are measured between V IH (min.) and V IL (max.).4. Access time is measured at 0.9V with the load shown in the figure below.5. The time t HZ (max.) is defined as the time required for the output voltage to become high impedance.IS42VS16100C1ISSI®8Integrated Silicon Solution, Inc. — — 1-800-379-4774Rev.00AOPERATING FREQUENCY / LATENCY RELATIONSHIPSSYMBOL PARAMETER -10-10UNITS —Clock Cycle Time1012ns —Operating Frequency (CAS Latency = 3)10083MHz t CAC CAS Latency32/3cycle t RCD Active Command To Read/Write Command Delay Time 32cycle t RAC RAS Latency (t RCD + t CAC )64cycle t RC Command Period (REF to REF / ACT to ACT)108cycle t RAS Command Period (ACT to PRE)55cycle t RP Command Period (PRE to ACT)32cycle t RRD Command Period (ACT[0] to ACT [1])22cycle t CCD Column Command Delay Time 11cycle (READ, READA, WRIT, WRITA)t DPL Input Data To Precharge Command Delay Time 22cycle t DAL Input Data To Active/Refresh Command Delay Time 54cycle (During Auto-Precharge)t RBD Burst Stop Command To Output in HIGH-Z Delay Time CAS Latency = 333cycle (Read)CAS Latency = 2—2t WBD Burst Stop Command To Input in Invalid Delay Time 00cycle (Write)t RQL Precharge Command To Output in HIGH-Z Delay Time CAS Latency = 333cycle (Read)CAS Latency = 2—2t WDL Precharge Command To Input in Invalid Delay Time 00cycle (Write)t PQL Last Output To Auto-Precharge Start Time (Read)CAS Latency = 3-2-2cycle CAS Latency = 2—-1t QMD DQM To Output Delay Time (Read)22cycle t DMD DQM To Input Delay Time (Write)00cycle t MRDMode Register Set To Command Delay Time22cycleAC TEST CONDITIONS (Input/Output Reference Level: 0.9V)IS42VS16100C1ISSI®COMMANDSNotes:1. A8-A9 = Don’t Care.IS42VS16100C1ISSI®COMMANDS (cont.)10Integrated Silicon Solution, Inc. — — 1-800-379-4774Rev.00ACOMMANDS (cont.)Integrated Silicon Solution, Inc. — — 1-800-379-477411 Rev.00A04/15/0512Integrated Silicon Solution, Inc. — — 1-800-379-4774Rev.00A 04/15/05Mode Register Set Command(CS , RAS , CAS , WE = LOW)The IS42VS16100C1 product incorporates a register that defines the device operating mode. This command functions as a data input pin that loads this register from the pins A0 to A11. When power is first applied, the stipulated power-on sequence should be executed and then the IS42VS16100C1 should be initialized by executing a mode register set command.Note that the mode register set command can be executed only when both banks are in the idle state (i.e. deactivated).Another command cannot be executed after a mode register set command until after the passage of the period t MCD , which is the period required for mode register set command execution.Active Command(CS , RAS = LOW, CAS , WE = HIGH)The IS42VS16100C1 includes two banks of 2048 rows each. This command selects one of the two banks according to the A11 pin and activates the row selected by the pins A0 to A10.This command corresponds to the fall of the RAS signal from HIGH to LOW in conventional DRAMs.Precharge Command(CS , RAS , WE = LOW, CAS = HIGH)This command starts precharging the bank selected by pins A10 and A11. When A10 is HIGH, both banks are precharged at the same time. When A10 is LOW, the bank selected by A11 is precharged. After executing this command, the next command for the selected bank(s) is executed after passage of the period t RP , which is the period required for bank precharging.This command corresponds to the RAS signal from LOW to HIGH in conventional DRAMsRead Command(CS , CAS = LOW, RAS , WE = HIGH)This command selects the bank specified by the A11 pin and starts a burst read operation at the start address specified by pins A0 to A9. Data is output following CAS latency.The selected bank must be activated before executing this command.When the A10 pin is HIGH, this command functions as a read with auto-precharge command. After the burst read completes, the bank selected by pin A11 is precharged.When the A10 pin is LOW, the bank selected by the A11 pin remains in the activated state after the burst read completes.Write Command(CS , CAS , WE = LOW, RAS = HIGH)When burst write mode has been selected with the mode register set command, this command selects the bank specified by the A11 pin and starts a burst write operation at the start address specified by pins A0 to A9. This first data must be input to the DQ pins in the cycle in which this command.The selected bank must be activated before executing this command.When A10 pin is HIGH, this command functions as a write with auto-precharge command. After the burst write completes, the bank selected by pin A11 is precharged.When the A10 pin is low, the bank selected by the A11 pin remains in the activated state after the burst write completes.After the input of the last burst write data, the application must wait for the write recovery period (t DPL , t DAL ) to elapse according to CAS latency.Auto-Refresh Command(CS , RAS , CAS = LOW, WE , CKE = HIGH)This command executes the auto-refresh operation. The row address and bank to be refreshed are automatically generated during this operation.Both banks must be placed in the idle state before executing this command.The stipulated period (t RC ) is required for a single refresh operation, and no other commands can be executed during this period.The device goes to the idle state after the internal refresh operation completes.This command must be executed at least 2048 times every 32 ms.This command corresponds to CBR auto-refresh in conventional DRAMs.Integrated Silicon Solution, Inc. — — 1-800-379-477413Rev.00A 04/15/05Self-Refresh Command(CS , RAS , CAS , CKE = LOW, WE = HIGH)This command executes the self-refresh operation. The row address to be refreshed, the bank, and the refresh interval are generated automatically internally during this operation. The self-refresh operation is started by dropping the CKE pin from HIGH to LOW. The self-refresh operation continues as long as the CKE pin remains LOW and there is no need for external control of any other pins. The self-refresh operation is terminated by raising the CKE pin from LOW to HIGH. The next command cannot be executed until the device internal recovery period (t RC ) has elapsed.After the self-refresh, since it is impossible to determine the address of the last row to be refreshed, an auto-refresh should immediately be performed for all addresses (2048cycles).Both banks must be placed in the idle state before executing this command.Burst Stop Command(CS , WE , = LOW, RAS , CAS = HIGH)The command forcibly terminates burst read and write operations. When this command is executed during a burst read operation, data output stops after the CAS latency period has elapsed.No Operation(CS , = LOW, RAS , CAS , WE = HIGH)This command has no effect on the device.Device Deselect Command(CS = HIGH)This command does not select the device for an object of operation. In other words, it performs no operation with respect to the device.Power-Down Command(CKE = LOW, CS = HIGH)When both banks are in the idle (inactive) state, or when at least one of the banks is not in the idle (inactive) state,this command can be used to suppress device power dissipation by reducing device internal operations to the minimal level in order to retain data content. Power-down mode is started by dropping the CKE pin from HIGH to LOW, while satisfying the other command input conditions (see CKE Truth Table). Power-down mode continues as long as the CKE pin is held low. All pins other than the CKE pin are invalid and none of the other commands can be executed in this mode. The power-down operation is terminated by raising the CKE pin from LOW to HIGH. The next command cannot be executed until the recovery period (t CKA ) has elapsed.Since this command differs from the self-refresh command described above in that the refresh operation is not performed automatically internally, the refresh operation must be performed within the refresh period (t REF ). Thus the maximum time that power-down mode can be held is just under the refresh cycle time.Clock Suspend(CKE = LOW)This command can be used to stop the device internal clock temporarily during a read or write cycle. Clock suspend mode is started by dropping the CKE pin from HIGH to LOW. Clock suspend mode continues as long as the CKE pin is held LOW. All input pins other than the CKE pin are invalid and none of the other commands can be executed in this mode. Also note that the device internal state is maintained. Clock suspend mode is terminated by raising the CKE pin from LOW to HIGH, at which point device operation restarts. The next command cannot be executed until the recovery period (t CKA ) has elapsed.Since this command differs from the self-refresh command described above in that the refresh operation is not performed automatically internally, the refresh operation must be performed within the refresh period (t REF ). Thus the maximum time that clock suspend mode can be held is just under the refresh cycle time.COMMAND TRUTH TABLE(1,2)CKESymbol Command n-1n CS RAS CAS WE DQM A11A10A9-A0DQn MRS Mode Register Set(3,4)H X L L L L X OP CODE X REF Auto-Refresh(5)H H L L L H X X X X HIGH-Z SREF Self-Refresh(5,6)H L L L L H X X X X HIGH-Z PRE Precharge Selected Bank H X L L H L X BS L X X PALL Precharge Both Banks H X L L H L X X H X X ACT Bank Activate(7)H X L L H H X BS Row Row X WRIT Write H X L H L L X BS L Column(18)X WRITA Write With Auto-Precharge(8)H X L H L L X BS H Column(18)X READ Read(8)H X L H L H X BS L Column(18)X READA Read With Auto-Precharge(8)H X L H L H X BS H Column(18)X BST Burst Stop(9)H X L H H L X X X X X NOP No Operation H X L H H H X X X X X DESL Device Deselect H X H X X X X X X X X SBY Clock Suspend / Standby Mode L X X X X X X X X X X ENB Data Write / Output Enable H X X X X X L X X X Active MASK Data Mask / Output Disable H X X X X X H X X X HIGH-ZDQM TRUTH TABLE(1,2)CKE DQMSymbol Command n-1n UPPER LOWERENB Data Write / Output Enable H X L LMASK Data Mask / Output Disable H X H HENBU Upper Byte Data Write / Output Enable H X L XENBL Lower Byte Data Write / Output Enable H X X LMASKU Upper Byte Data Mask / Output Disable H X H XMASKL Lower Byte Data Mask / Output Disable H X X HCKE TRUTH TABLE(1,2)CKESymbol Command Current State n-1n CS RAS CAS WE A11A10A9-A0 SPND Start Clock Suspend Mode Active H L X X X X X X X —Clock Suspend Other States L L X X X X X X X —Terminate Clock Suspend Mode Clock Suspend L H X X X X X X X REF Auto-Refresh Idle H H L L L H X X X SELF Start Self-Refresh Mode Idle H L L L L H X X X SELFX Terminate Self-Refresh Mode Self-Refresh L H L H H H X X XL H H X X X X X X PDWN Start Power-Down Mode Idle H L L H H H X X XH L H X X X X X X—Terminate Power-Down Mode Power-Down L H X X X X X X X14Integrated Silicon Solution, Inc. — — 1-800-379-4774Rev.00A04/15/05OPERATION COMMAND TABLE(1,2)Current State Command Operation CS RAS CAS WE A11A10A9-A0 Idl e DESL No Operation or Power-Down(12)H X X X X X X NOP No Operation or Power-Down(12)L H H H X X XBST No Operation or Power-Down L H H L X X XREAD / READA Illegal L H L H V V V(18)WRIT/WRITA Illegal L H L L V V V(18)ACT Row Active L L H H V V V(18)PRE/PALL No Operation L L H L V V XREF/SELF Auto-Refresh or Self-Refresh(13)L L L H X X XMRS Mode Register Set L L L L OP CODE Row Active DESL No Operation H X X X X X X NOP No Operation L H H H X X XBST No Operation L H H L X X XREAD/READA Read Start(17)L H L H V V V(18)WRIT/WRITA Write Start(17)L H L L V V V(18)ACT Illegal(10)L L H H V V V(18)PRE/PALL Precharge(15)L L H L V V XREF/SELF Illegal L L L H X X XMRS Illegal L L L L OP CODE Read DESL Burst Read Continues, Row Active When Done H X X X X X X NOP Burst Read Continues, Row Active When Done L H H H X X XBST Burst Interrupted, Row Active After Interrupt L H H L X X XREAD/READA Burst Interrupted, Read Restart After Interrupt(16)L H L H V V V(18)WRIT/WRITA Burst Interrupted Write Start After Interrupt(11,16)L H L L V V V(18)ACT Illegal(10)L L H H V V V(18)PRE/PALL Burst Read Interrupted, Precharge After Interrupt L L H L V V XREF/SELF Illegal L L L H X X XMRS Illegal L L L L OP CODE Write DESL Burst Write Continues, Write Recovery When Done H X X X X X X NOP Burst Write Continues, Write Recovery When Done L H H H X X XBST Burst Write Interrupted, Row Active After Interrupt L H H L X X XREAD/READA Burst Write Interrupted, Read Start After Interrupt(11,16)L H L H V V V(18)WRIT/WRITA Burst Write Interrupted, Write Restart After Interrupt(16)L H L L V V V(18)ACT Illegal(10)L L H H V V V(18)PRE/PALL Burst Write Interrupted, Precharge After Interrupt L L H L V V XREF/SELF Illegal L L L H X X XMRS Illegal L L L L OP CODE Read With DESL Burst Read Continues, Precharge When Done H X X X X X X Auto-NOP Burst Read Continues, Precharge When Done L H H H X X X Precharge BST Illegal L H H L X X X READ/READA Illegal L H L H V V V(18)WRIT/WRITA Illegal L H L L V V V(18)ACT Illegal(10)L L H H V V V(18)PRE/PALL Illegal(10)L L H L V V XREF/SELF Illegal L L L H X X XMRS Illegal L L L L OP CODE Integrated Silicon Solution, Inc. — — 1-800-379-477415 Rev.00A04/15/05OPERATION COMMAND TABLE(1,2)Current State Command Operation CS RAS CAS WE A11A10A9-A0 Write With DESL Burst Write Continues, Write Recovery And Precharge H X X X X X X Auto-Precharge When DoneNOP Burst Write Continues, Write Recovery And Precharge L H H H X X XBST Illegal L H H L X X XREAD/READA Illegal L H L H V V V(18)WRIT/WRITA Illegal L H L L V V V(18)ACT Illegal(10)L L H H V V V(18)PRE/PALL Illegal(10)L L H L V V XREF/SELF Illegal L L L H X X XMRS Illegal L L L L OPCODE Row Precharge DESL No Operation, Idle State After t RP Has Elapsed H X X X X X X NOP No Operation, Idle State After t RP Has Elapsed L H H H X X XBST No Operation, Idle State After t RP Has Elapsed L H H L X X XREAD/READA Illegal(10)L H L H V V V(18)WRIT/WRITA Illegal(10)L H L L V V V(18)ACT Illegal(10)L L H H V V V(18)PRE/PALL No Operation, Idle State After t RP Has Elapsed(10)L L H L V V XREF/SELF Illegal L L L H X X XMRS Illegal L L L L OP CODE Immediately DESL No Operation, Row Active After t RCD Has Elapsed H X X X X X X Following NOP No Operation, Row Active After t RCD Has Elapsed L H H H X X X Row Active BST No Operation, Row Active After t RCD Has Elapsed L H H L X X X READ/READA Illegal(10)L H L H V V V(18)WRIT/WRITA Illegal(10)L H L L V V V(18)ACT Illegal(10,14)L L H H V V V(18)PRE/PALL Illegal(10)L L H L V V XREF/SELF Illegal L L L H X X XMRS Illegal L L L L OP CODE Write DESL No Operation, Row Active After t DPL Has Elapsed H X X X X X X Recovery NOP No Operation, Row Active After t DPL Has Elapsed L H H H X X X BST No Operation, Row Active After t DPL Has Elapsed L H H L X X XREAD/READA Read Start L H L H V V V(18)WRIT/WRITA Write Restart L H L L V V V(18)ACT Illegal(10)L L H H V V V(18)PRE/PALL Illegal(10)L L H L V V XREF/SELF Illegal L L L H X X XMRS Illegal L L L L OP CODE16Integrated Silicon Solution, Inc. — — 1-800-379-4774Rev.00A04/15/05OPERATION COMMAND TABLE(1,2)Current State Command Operation CS RAS CAS WE A11A10A9-A0 Write Recovery DESL No Operation, Idle State After t DAL Has Elapsed H X X X X X XWith Auto-NOP No Operation, Idle State After t DAL Has Elapsed L H H H X X XPrecharge BST No Operation, Idle State After t DAL Has Elapsed L H H L X X X READ/READA Illegal(10)L H L H V V V(18)WRIT/WRITA Illegal(10)L H L L V V V(18)ACT Illegal(10)L L H H V V V(18)PRE/PALL Illegal(10)L L H L V V XREF/SELF Illegal L L L H X X XMRS Illegal L L L L OP CODE Refresh DESL No Operation, Idle State After t RP Has Elapsed H X X X X X X NOP No Operation, Idle State After t RP Has Elapsed L H H H X X XBST No Operation, Idle State After t RP Has Elapsed L H H L X X XREAD/READA Illegal L H L H V V V(18)WRIT/WRITA Illegal L H L L V V V(18)ACT Illegal L L H H V V V(18)PRE/PALL Illegal L L H L V V XREF/SELF Illegal L L L H X X XMRS Illegal L L L L OP CODE Mode Register DESL No Operation, Idle State After t MCD Has Elapsed H X X X X X X Set NOP No Operation, Idle State After t MCD Has Elapsed L H H H X X X BST No Operation, Idle State After t MCD Has Elapsed L H H L X X XREAD/READA Illegal L H L H V V V(18)WRIT/WRITA Illegal L H L L V V V(18)ACT Illegal L L H H V V V(18)PRE/PALL Illegal L L H L V V XREF/SELF Illegal L L L H X X XMRS Illegal L L L L OP CODE Notes:1. H: HIGH level input, L: LOW level input, X: HIGH or LOW level input, V: Valid data input2. All input signals are latched on the rising edge of the CLK signal.3. Both banks must be placed in the inactive (idle) state in advance.4. The state of the A0 to A11 pins is loaded into the mode register as an OP code.5. The row address is generated automatically internally at this time. The DQ pin and the address pin data is ignored.6. During a self-refresh operation, all pin data (states) other than CKE is ignored.7. The selected bank must be placed in the inactive (idle) state in advance.8. The selected bank must be placed in the active state in advance.9. This command is valid only when the burst length set to full page.10. This is possible depending on the state of the bank selected by the A11 pin.11. Time to switch internal busses is required.12. The IS42VS16100C1 can be switched to power-down mode by dropping the CKE pin LOW when both banks in the idlestate. Input pins other than CKE are ignored at this time.13. The IS42VS16100C1 can be switched to self-refresh mode by dropping the CKE pin LOW when both banks in the idlestate. Input pins other than CKE are ignored at this time.14. Possible if t RRD is satisfied.15. Illegal if t RAS is not satisfied.16. The conditions for burst interruption must be observed. Also note that the IS42VS16100C1 will enter the precharged stateimmediately after the burst operation completes if auto-precharge is selected.17. Command input becomes possible after the period t RCD has elapsed. Also note that the IS42VS16100C1 will enter theprecharged state immediately after the burst operation completes if auto-precharge is selected.18. A8,A9 = don’t care.Integrated Silicon Solution, Inc. — — 1-800-379-477417 Rev.00A04/15/05。