Ultra-Low Cost and Power Communication and Computation Enables Ambient Intelligence

PGElectrical · Principle of Function · Universal Gripper1044Modular RoboticsModular-Standardized interfaces for mechatronics and control for rapid and simple assembly without complicated designs-Cube geometry with diverse possibilities for creating individual solutions from the modular systemIntegrated-The control and power electronics are fully integrated in the modules for minimal space requirements and interfering contours-Single-cable technology combines data transmission and the power supply for minimal assembly and start-up costs Intelligent-Integrated high-end microcontroller for rapid data processing -Decentralized control system for digital signal processing -Universal communication interfaces for rapid incorporation in existing servo-controlled conceptsYour advantages and benefitsThe modules of the PowerCube series provide the basis for flexible combinatorics in automation. Complex systems and multiple-axis robot structures with several degrees of freedom can be achieved with minimum time and expenditure spent on design and programming.Module overviewThe innovative technology of the PowerCube modules already forms the basis of numerous applications in the fields of measuring and testing systems, laboratory automation, service robotics and flexiblerobot technology.PGServo-electric2-Finger Parallel Gripper PRServo-electric Rotary Actuators PWServo-electricRotary Pan Tilt ActuatorsPSMServo-motors with integrated position controlPDUServo-positioning motor with precision gearsPLSServo-electric Linear Axes withball-and-screw spindle drivePG·Universal Gripper1045Method of actuationThe PowerCube modules work completely independently. The master control system is only required for generating the sequential program and sending it step by step to the connected modules. Therefore, only the current sequential command is ever stored in the modules, and the subsequent command is stored in the buffer. The current, rotational speed and positioning are controlled in the module itself. Likewise, functions such as temperature and limit monitoring are performed in the module itself. Real-time capability is not absolutely essential for the master control or bus system. For the communication over Bus-System the SMP - SCHUNK Motion Protocol - is used. This enables you to create industrial bus networks,and ensures easy integration in control systems.Control version AB Hardware Control with PLC (S7)Control with PC Interface Profibus DP CAN bus / RS-232SoftwareWindows (from Windows 98) operating systemLINUX operating systemDevelopment platforms MC-Demo Operating Software PowerCube (LabView, Diadem)with Online documentation, standard softwaregsd-file, programming examples(gsd file, programming examples)on requeston requestIncluded with the ''Mechatronik DVD'' (ID 9949633): Assembly and Operating Manual with manufacturer's declaration, MCDemo software and description and gsd-file for S7 use.1234567889ᕃ24VDC / 48VDC power supply provided by the customerᕄControl system provided by the customer (see control versions A, B and C)ᕅPAE 130 TB terminal block for connecting the voltage supply, the communication and the hybrid cable (Option for easy connection)ᕆPDU servo-motorᕇLinear axis with PLS ball-and-screw spindle drive and PSM servo-motorᕈHybrid cable (single-cable technology) for connecting the PowerCube modules (voltage supply and communication). Not recommended for the use in Profibus applications ᕉPW Servo-electric Rotary Pan Tilt Actuator ᕊPG Servo-electric 2-Finger Parallel Gripper ᕋPR Servo-electric Rotary ActuatorPG· Universal Gripper1046Size 70Weight 1.4 kg Gripping force up to 200 N Stroke per finger 35 mm Workpiece weight1 kgApplication exampleDouble rotary gripper module for loading and unloading of sensitive componentsPG 70 Servo-electric 2-Finger Parallel Gripper PR 70 Servo-electric Rotary ActuatorPGUniversal Gripper1047Gripping force control in the range of 30 - 200 N for the delicate gripping of sensitive workpieces Long stroke of 70 mm for flexible workpiece handlingFully integrated control and power electronics for creating a decentralized control systemVersatile actuation optionsfor simple integration in existing servo-controlled concepts via Profibus-DP, CAN bus or RS-232Standard connecting elements and uniform servo-controlled conceptfor extensive combinatorics with other PowerCube modules (see explanation of the PowerCube system)Single-cable technology for data transmission and power supplyfor low assembly and start-up costsServo-electric 2-finger parallel gripper with highly precise gripping force control and long strokeUniversal GripperArea of applicationUniversal, ultra-flexible gripper for great part variety and sensitive components in clean working environmentsYour advantages and benefitsGeneral information on the seriesWorking principle Ball screw driveHousing materialAluminum alloy, hard-anodized Base jaw materialAluminum alloy, hard-anodized ActuationServo-electric, by brushless DC servo-motorWarranty 24 monthsScope of deliveryGuide centering sleeves and ‘’Mechatronik DVD’’ (contains an Assembly and Operating Manual with manufacturer’s declarartion and MC-Demo software withdescription)PG· Universal Gripper1048Control electronicsintegrated control and power electronics for controlling the servo-motorEncoderfor gripper positioning and position evaluationDrivebrushless DC servo-motorGear mechanismtransfers power from the servo-motor to the drive spindleSpindletransforms the rotational movement into the linear movement of the base jaw Humidity protection cap link to the customer’s systemThe brushless servo-motor drives the ball screw by means of the gear mechanism.The rotational movement is transformed into the linear movement of the base jaw by base jaws mounted on the spindles.Function descriptionThe PG gripper is electrically actuated by the fully integrated control and power electronics. In this way, the module does not require any additional external control units.A varied range of interfaces, such as Profibus-DP, CAN-Bus or RS-232 are available as methods of communication. For the communication over Bus-System the SMP - SCHUNK Motion Protocol - is used. This enables you to create industrial bus networks, and ensures easy integration in control systems.If you wish to create combined systems (e.g. a rotary gripper module), various other modules from the Mechatronik-Portfolio are at your disposal.Electrical actuationSectional diagramPGUniversal Gripper1049Gripping forceis the arithmetic total of the gripping force applied to each base jaw at distance P (see illustration), measured from the upper edge of the gripper.Finger lengthis measured from the upper edge of the gripper housing in the direction of the main axis.Repeat accuracyis defined as the spread of the limit position after 100 consecutive strokes.Workpiece weightThe recommended workpiece weight is calculated for a force-type connection with a coefficient of friction of 0.1 and a safety factor of 2 against slippage of theworkpiece on acceleration due to gravity g. Considerably heavier workpiece weights are permitted with form-fit gripping.Closing and opening timesClosing and opening times are purely the times that the base jaws or fingers are in motion. Control or PLC reaction times are not included in the above times and must be taken into consideration when determining cycle times.General information on the seriesCentering sleevesElectrical accessories PAE terminal blockPAM standardconnecting elementsAccessoriesHybrid cableFor the exact size of the required accessories, availability of this size and the designation and ID, please refer to the additional views at the end of the size in question. You will find more detailed information on our accessory range in the …Accessories“ catalog section.PG 70· Universal Gripper1050Technical dataFinger loadMoments and forces apply per base jaw and may occur simultaneously. M y may arise in addition to the moment generated by the gripping force itself. If the max.permitted finger weight is exceeded, it is imperative to throttle the air pressure so that the jaw movement occurs without any hitting or bouncing. Service life may bereduced.Gripping force, I.D. grippingDescriptionPG 70Mechanical gripper operating data ID 0306090Stroke per finger [mm]35.0Constant gripping force (100 % continuous duty)[N]200.0Max. gripping force [N]200.0Min. gripping force [N]30.0Weight [kg] 1.4Recommended workpiece weight [kg] 1.0Closing time [s] 1.1Opening time [s] 1.1Max. permitted finger length [mm]140.0IP class20Min. ambient temperature [°C] 5.0Max. ambient temperature [°C]55.0Repeat accuracy [mm]0.05Positioning accuracy [mm]on request Max. velocity [mm/s]82.0Max. acceleration [mm/s 2]328.0Electrical operating data for gripper Terminal voltage [V]24.0Nominal power current [A] 1.8Maximum current [A] 6.5Resolution [µm] 1.0Controller operating data Integrated electronics Yes Voltage supply [VDC]24.0Nominal power current [A]0.5Sensor system EncoderInterfaceI/O, RS 232, CAN-Bus, Profibus DPPG 70Universal Gripper1051ᕃ24 VDC power supply provided by thecustomerᕄControl (PLC or similar) provided bythe customerᕅPAE 130 TB terminal block(ID No. 0307725) for connecting the power supply, the communication and the hybrid cableᕆHybrid cable for connecting thePowerCube modulesMain viewsThe drawing shows the gripper in the basic version with closed jaws, the dimensions do not include the options described below.ᕃGripper connection ᕄFinger connectionᕓᕗM16x1.5 for cable glandActuation DescriptionID Length PowerCube Hybrid cable, coiled 03077530.3 m PowerCube Hybrid cable, coiled03077540.5 mPowerCube Hybrid cable, straight (per meter)9941120The ‘Hybrid cable’ is recommended for the use in CAN-Bus- or RS232-systems. For Profibus applications we recommend to use a separate standardized Profibus cable for the communication.You can find further cables in the …Accessories“ catalog section.Interconnecting cablePG 70· Universal Gripper1052Special lengths on requestRight-angle standard element for connecting size 70 PowerCube modulesSpecial lengths on requestConical standard element for connecting size 70 and 90 PowerCube modulesSpecial lengths on requestStraight standard element for connecting size 70 PowerCube modules Right-angle connecting elements Description ID DimensionsPAM 120030782090°/70.5x98Conical connecting elements Description ID DimensionsPAM 110030781090x90/45/70x70 mm PAM 111030781190x90/90/70x70 mmStraight connecting elements Description ID DimensionsPAM 100030780070x70/35/70x70 mm PAM 101030780170x70/70/70x70 mmMechanical accessoriesYou can find more detailed information and individual parts of the above-mentioned accessories in the …Accessories“ catalog section.。

TI TMS320F280025C实时微控制器(MCU)开发方案TI公司的TMS320F280025C(F28002x)是C2000™实时微控制器系列,具有可升级超低延迟器件,设计用在高效的功率电子学包括但不限于高功率密度高开关频率,支持使用GaN和SiC技术.实时控制子系统是基于32位C28x DSP核,提供浮点或定点核的100MHz 信号处理性能,运营片上闪存回SRAM.C28xCPU核还可从三角数学单元(TMU)和循环冗余校验(VCRC)扩展指令集进行引导,从而加速实时控制系统的共通算法.F28002x实时微控制器(MCU)还集成了高性能模拟区块,和处理和PWM单元密切配合,以提供最佳实时信号链信能.十四个PWM通路,都支持独立与频率的分辨率模式,使得控制3相逆变器的各个功率级,以达到先进的多级功率拓扑.主要应用在工业马达驱动,马达控制,太阳能逆变器,数字功率,电动汽车和交通,检测和信号处理.本文介绍了TMS320F280025C主要特性,功能框图和时钟系统图,模拟子系统框图,ADC模块框图以及开发板LAUNCHXL-F280025C主要特性,框图,电路图,材料清单和PCB设计图.The TMS320F28002x (F28002x) is a member of the C2000™ real-time microcontroller family of scalable, ultralowlatency devices designed for efficiency in power electronics, including but not limited to: high power density,high switching frequencies, and supporting the use of GaN and SiC technologies.These include such applications as:• Industrial motor drives• Motor control• Solar inverters• Digital power• Electrical vehicles and transportat ion• Sensing and signal processingThe real-time control subsystem is based on TIs 32-bit C28x DSP core, which provides 100 MHz of signalprocessingperformance for floating- or fixed-point code running from either on-chip flash or SRAM. The C28xCPU is further boosted by the Trigonometric Math Unit (TMU) and VCRC (Cyclical Redundancy Check)extended instruction sets, speeding up common algorithms key to real-time control systems. High-performance analog blocks are integrated on the F28002x real-time microcontroller (MCU) and are closelycoupled with the processing and PWM units to provide optimal real-time signal chain performance. FourteenPWM channels, all supporting frequency-independent resolution modes, enable control of various power stagesfrom a 3-phase inverter to advanced multi-level power topologies.The inclusion of the Configurable Logic Block (CLB) allows the user to add custom logic and potentially integrateFPGA-like functions into the C2000 real-time MCU.Interfacing is supported through various industry-standard communication ports (such as SPI, SCI, I2C, PMBus,LIN, and CAN) and offers multiple pin-muxing options for optimal signal placement. The Fast Serial Interface(FSI) enables up to 200 Mbps of robust communications across an isolation boundary. New to the C2000 platform is the Host Interface Controller (HIC), a high-throughput interface that allows anexternal host to access the resources of the TMS320F28002x directly.TMS320F280025C主要特性:• TMS320C28x 32-bit DSP core at 100 MHz– IEEE 754 Floating-Point Unit (FPU)• Support for Fast Integer Division (FINTDIV)– Trigonometric Math Unit (TMU)• Support for Nonlinear Proportional IntegralDerivative (NLPID) control– CRC Engine and Instructions (VCRC)– Ten hardware breakpoints (with ERAD)• On-chip memory– 128KB (64KW) of flash (ECC-protected)– 24KB (12KW) of RAM (ECC or parity-protected)– Dual-zone security• Clock and system control– Two internal zero-pin 10-MHz oscillators– On-chip crystal oscillator or external clock input– Windowed watchdog timer module– Missing clock detection circuitry– Dual-clock Comparator (DCC)• Single 3.3-V supply– Internal VREG generation– Brownout reset (BOR) circuit• System peripherals– 6-channel Direct Memory Access (DMA)controller– 39 individually programmable multiplexedGeneral-Purpose Input/Output (GPIO) pins – 16 digital inputs on analog pins– Enhanced Peripheral Interrupt Expansion(ePIE)– Multiple low-power mode (LPM) support– Embedded Real-time Analysis and Diagnostic(ERAD)– Unique Identification (UID) number• Communications peripherals– One Power-Management Bus (PMBus)interface– Two Inter-integrated Circuit (I2C) interfaces– One Controller Area Network (CAN) bus port– Two Serial Peripheral Interface (SPI) ports– One UART-compatible Serial CommunicationInterface (SCI)– Two UART-compatible Local InterconnectNetwork (LIN) interfaces– Fast Serial Interface (FSI) with one transmitterand one receiver (up to 200Mbps)• Analog system– Two 3.45-MSPS, 12-bit Analog-to-DigitalConverters (ADCs)• Up to 16 external channels• Four integrated Post-Processing Blocks(PPB) per ADC– Four windowed comparators (CMPSS) with12-bit reference Digital-to-Analog Converters(DACs) • Digital glitch filters• Enhanced control peripherals– 14 ePWM channels with eight channels thathave high-resolution capability (150-ps resolution)• Integrated dead-band support• Integrated hardware trip zones (TZs)– Three Enhanced Capture (eCAP) modules• High-resolution Capture (HRCAP) availableon one of the three eCAP modules– Two Enhanced Quadrature Encoder Pulse(eQEP) modules with support for CW/CCW operation modes• Configurable Logic Block (CLB)– Augments existing peripheral capability– Supports position manager solutions• Host Interface Controller (HIC)– Access to internal memory from an externalhost• Background CRC (BGCRC)– One cycle CRC computation on 32 bits of data• Diagnostic features– Memory Power OnSelf Test (MPOST)– Hardware Built-in Self Test (HWBIST)• Package options:– 80-pin Low-profile Quad Flatpack (LQFP)[PN suffix]– 64-pin LQFP [PM suffix]– 48-pin LQFP [PT suffix]• Temperature options:– S: –40C to 125C junction– Q: –40C to 125C free-air(AEC Q100 qualification for automotiveapplications)TMS320F280025C应用:• Appliances– Air conditioner outdoor unit• Building automation– Door operator drive control• Industrial machine & machine tools– Automated sorting equipment– Textile machine• EV charging infrastructure– AC charging (pile) station– DC charging (pile) station– EV charging station power module– Wireless EV charging station• Renewable energy storage– Energy storage power conversion system(PCS) • Solar energy– Central inverter– Micro inverter– Solar power optimizer– Solar arc protection– Rapid shutdown– Electricity meter– String inverter• Hybrids, electric & powertrain systems– DC/DC converter– Inverter & motor control– On-board (OBC) & wireless charger• Body electronics & lighting– Automotive HVAC compressor module– DC/AC inverter– Headlight• AC inverter & V F drives– AC drive control module– AC drive position feedback– AC drive power stage module• Linear motor transport systems– Linear motor power stage• Single & multi axis servo drives– Servo drive position feedback– Servo drive power stage module• Speed controlled BLDC drives– AC-input BLDC motor drive– DC-input BLDC motor drive • Industrial power– Industrial AC-DC• UPS– Three phase UPS– Single phase online UPS• Telecom & server power– Merchant DC/DC– Merchant network & server PSU – Merchant telecom rectifiers图1.TMS320F280025C功能框图图2.TMS320F280025C时钟系统图图3.TMS320F280025C模拟子系统框图(80引脚PN和64引脚PM LQFP)图4.TMS320F280025C模拟子系统框图(48引脚PT LQFP)图5.TMS320F280025C ADC模块框图开发板LAUNCHXL-F280025CThe LAUNCHXL-F280025C is a low-cost development bo ard for the Texas Instruments C2000™ Real-TimeMicrocontroller series of F28002x devices. It is designed around the TMS320F280025C real-time MCU andhighlights the control, analog, and communications peripherals, as well as the integrated nonvolatile memory.The LaunchPad also features two independent BoosterPack XL expansion connectors (80-pins),on-boardController Area Network (CAN) transceiver, two 5 V encoder interface (eQEP) connectors, FSI connector, and anon-board XDS110 debug probe.图6.开发板LAUNCHXL-F280025C外形图开发板LAUNCHXL-F280025C主要特性:The F28002x LaunchPad has these features:• C2000 Series F280025CPNS (80-pin) microcontroller:– With Configurable Logic Block (CLB) capability• On-board XDS110 debug probe• Two user-controlled LEDs• One mi crocontroller reset switch• Selectable power domains:– USB (isolated)– BoosterPack– External power supply• CAN connector with on-board CAN transceiver• Two independent Enhanced Quadrature Encoder Pulse (QEP)-based encoder connectors• FSI peripheral connector• Two independent BoosterPack XL standard connectors (80-pins) featuring stackable headers to maximizeexpansion through the BoosterPack ecosystem开发板LAUNCHXL-F280025C包括:The F28002x Series LaunchPad Development Kit contains these items:• C2000 F28002x Series LaunchPad development board (LAUNCHXL-F280025C)• USB micro-B plug to USB-A plug cable• Quick Start Guide图7.开发板LAUNCHXL-F280025C框图图8.开发板LAUNCHXL-F280025C电路图(1)图9.开发板LAUNCHXL-F280025C电路图(2)图10.开发板LAUNCHXL-F280025C电路图(3)图11.开发板LAUNCHXL-F280025C电路图(4)图12.开发板LAUNCHXL-F280025C电路图(5)图13.开发板LAUNCHXL-F280025C PCB设计图(1):信号,层1图14.开发板LAUNCHXL-F280025C电路图(2):GND,层2图15.开发板LAUNCHXL-F280025C电路图(3):PWR,层3图16.开发板LAUNCHXL-F280025C电路图(4):底层信号,层4。

SWITCH SYSTEMIS503036-port Non-blocking Managed 40Gb/s InfiniBand Switch SystemIS5030©2011 Mellanox Technologies. All rights reserved.350 Oakmead Parkway, Suite 100, Sunnyvale, CA 94085Tel: 408-970-3400 • Fax: 3348PB Rev 1.1© Copyright 2011. Mellanox Technologies. All rights reserved.Mellanox, BridgeX, ConnectX, CORE-Direct, InfiniBlast, InfiniBridge, InfiniHost, InfiniRISC, InfiniScale, InfiniPCI, PhyX, Virtual Protocol Interconnect and Voltaire are registered trademarks of Mellanox Technologies, Ltd.FabricIT is a trademark of Mellanox Technologies, Ltd. All other trademarks are property of their respective owners.* Also available through Mellanox Certified Resellers and Distributors* Also available in short depth form factor and with 2 power supplies. Consult your Mellanox Sales Representative for further details.SAFETY–US/Canada: cTUVus –EU: IEC60950 –International: CB EMC (EMISSIONS) –USA: FCC, Class A –Canada: ICES, Class A –EU: EN55022, Class A –EU: EN55024, Class A –EU: EN61000-3-2, Class A –EU: EN61000-3-3, Class A –Japan: VCCI, Class A ENVIRONMENTAL–EU: IEC 60068-2-64: Random Vibration –EU: IEC 60068-2-29: Shocks, Type I / II –EU: IEC 60068-2-32: Fall TestOPERATING CONDITIONS –Operating 0ºC to 45ºC, Non Operating -40ºC to 70ºC –Humidity: Operating 5% to 95%, –Altitude: Operating -60 to 2000m,–Noise: 55dB - Noise reduction by controlling fan speed ACCOUSTIC –ISO 7779 –ETS 300 753 OTHERS–RoHS-5 compliant –Rack-mountable, 1U –1-year warrantyINFINIBAND SWITCH–36 QDFP non blocking switch with aggregate throughput of up to 2.88 Tb/s –Port-to-port latency < 100ns –IBTA 1.21 compliant–9 Virtual lanes: 8 data + 1 management –Adaptive routing –Congestion control –Port mirroring–48K entry linear forwarding data base MANAGEMENT PORTS –RS232 Console (RJ45) –Ethernet (RJ45) –USB portCONNECTORS AND CABLING –QSFP connectors–Passive/Active copper or fiber cable –Fiber media adapters INDICATORS–Per port status LED: Link, Activity –System status LED:Fan and power supplies LEDs POWER SUPPLY –Dual redundant slots –Hot plug operation–Input range: 100 - 240VAC–Frequency: 50-60Hz, single phase AC FANS–Front-to-rear or rear-to-front cooling option –Hot-swappable fan unit–Auto-heat sensing for silent fan operation –Fan speed controlled through management softwareCOMPLIANCEHARDWAREINFINIBAND–IBTA Specification 1.2.1 compliant–Integrated subnet manager agent–Adaptive routing–Congestion control–256 to 4Kbyte MTU–9 virtual lanes: 8 data + 1 management –48K entry linear forwarding data base –Port Mirroring MANAGEMENT–Fast and efficient fabric bring-up–Fabric-wide bandwidth verification–Comprehensive chassis management –Mellanox API for 3rd party integration –Intuitive CLI and GUI for easy access ©2011 Mellanox Technologies. All rights reserved.。

S32R372141EVBQUICK START GUIDE (QSG)Ultra-Reliable MCUs for Industrial and Automotive ApplicationsS32R372141EVB WebpageContents•Quick Start Package Overview •Step-by-Step Installation Instructions •Hardware: S32R372141EVB Board −Features−S32R372141EVB Overview−S32R372141EVB Pinout Settings−Communication and Debug Interfaces−Power Supply•Software:−Software Development Tools−Pre-compiled Code Examples•Documentation•Radar Family Comparison •RecommendationsQuick Start Package OverviewBoard:S32R372141EVB S32R372 evaluation board for 141 BGA package. Can run standalone or with Radar front-end Documents:Name DescriptionQuick Start Guide(QSG)Detailed description on availability of Hardware,Software and Documents to quick start with S32R372project (this document)Software Installation Guide(SWIG)Detailed walk through on how to install and use S32 Design Studio for Power Architecture Application Notes Detailed documents covering topics from‘how to design hardware’ to ‘how to write software’Fact Sheets, Reference Manuals and Data Sheets Detailed manuals for S32R family of MCU and S32R372141EVB boardDownloads:Name DescriptionIntegrated Development Environment (IDE)Eclipse based S32DS IDE with free GCC compiler and Debugger supportS32R372141EVB Quick Start Package Software examples and supporting documents for getting started with the S32R372141EVBS32R372141EVB Schematics PDF schematic files for the S32R372141EVB boardS32R372141EVB PCB Design Package Gerber files and Bill of MaterialStep-by-Step Installation Instructions1Install Software and ToolsInstall S32 Design Studio IDE for Power Architecture.S32 Design Studio for PowerSee Software Installation Guide (SWIG) for detailed procedure2Connect the DebuggerConnect the debugger (e.g. P&E USB Multilink) to the board.3Observe the Default Program reactionThe pre-loaded example project utilizes the S32R’s multiple cores. Once the board is plugged in, the S32R’s PLLs will be programmed to max frequency. The CLKOUT pin will display the frequency of each PLL in a round-robin fashion as each core takes turns controlling CLKOUT.4Learn More About the S32R37x-141BGA Read release notes and documentation on the S32R372 Product PageS32R274RRUEVB Product PageIn this quick start guide,you will learn how to set up the S32R372141EVB board and run the default program.S32R372141EVB Board : Features•S32R27 has 2 x 240 MHz Power Architecture® e200Z7 computation cores•S32Rx qualified to AEC-Q100 Grade 1 and ambient temperature of -40 to+150 °C•S32R372141EVB is a low cost standalone radar EVB. Attach a radar transceiver to the MIPI-CSI2 connector to take advantage of its radar processing capability•Integrated JTAG interface for easy debugging•Easy access to the MCU I/O header pins for prototyping•Nexus traceport•Solder points for Gb Ethernet port•MIPI_CSI2 connector•Flexible power supply options•12V and GND pins to allow you to supply from DC generator •12V External power supply via barrel connector •Box includes:−S32R372141EVB Board •Downloads includes:−Quick Start Package−S32 Design Studio IDE−Application notesS32R372141EVB Board : OverviewThe S32R372141EVB is NXP’s evaluation board for the S32R372 radar processor. It is designed to be paired with an analog front end. NXP supports the TEF810 and MR3003 radartransceivers, but third-party options are possible.This EVB features I/O headers, trace ports, and CAN ports to meet any prototyping needs at a low cost.NXP MicrocontrollerS32R372JTAGEthernet Port (DNP)MIPI-CSI2 ConnectorGPIO PinsPower Supply CAN PHYNexus Trace PortReset ButtonNote: “DNP” stands for “Do not populate”, meaning pin is disconnected by default. You mustP3FUNCTION PORT PIN PIN PORT FUNCTION GND GND GND GND GPIO[62]PD14P4-16P4-15PD6GPIO[54]GPIO[51]PD3P4-14P4-13PD1ETIMER_ETC2ETIMER_ETC0PC15P4-12P4-11PC12ETIMER_ETC2GPIO[32]PC0P4-10P4-9PB15ADC1_AN2ADC1_AN0PB13P4-8P4-7PB6GPIO[22]_CLKOUT TDI PB5P4-6P4-5PB4TDO GPIO[19]PB3P4-4P4-3PB2GPIO[18]CAN0_RXDPB1P4-2P4-1PB0CAN0_TXDFUNCTIONPORT PIN PIN PORT FUNCTIONGND GND GND GND GPIO[15]PA15P3-16P3-15PA14SIUL_EIRQ13DSPI2_SIN PA13P3-14P3-13PA12DSPI2_SOUT DSPI2_SCK PA11P3-12P3-11PA10DSPI2_CS0GPIO[9]PA9P3-10P3-9PA8TX1_PS TX2_PS PA7P3-8P3-7PA6TX3_PS EIRQ_5PA5P3-6P3-5PA4ERROR_RST SSN-MEM PA3P3-4P3-3PA2SBC_FS0B EIRQ_1PA1P3-2P3-1PA0ERROR_NP3P4P4FUNCTIONPORT PIN PIN PORT FUNCTIONGND GND GND GND NCP5-16P5-15NCFCCU_1FCCU_F1P5-14P5-13FCCU_F0FCCU_0NMI NMI P5-12P5-11PI5CAN2_TXD RESETPI4P5-10P5-9PH7GPIO[119]GPIO[104]PG8P5-8P5-7PF15CAN2_RXD CTE_RCS PF0P5-6P5-5PE15GPIO[79]_CLKOUT GPIO[77]PE13P5-4P5-3PE6GPIO[70]GPIO[68]PE4P5-2P5-1PE2GPIO[66]P5P5CAN2CAN_2DESCRIPTION NAME PIN Port PI5 & PF15CANL J35-03GND J35-02CANH J35-01CAN_0DESCRIPTION NAME PIN Port PB0 & PB1CANLJ31-03GND J31-02CANHJ31-01CAN0EthernetEthernet (DNP)DESCRIPTION PORTMTI_P0_IUC MTI_P0MTI_N0_IUC MTI_N0MTI_N2_IUC MTI_N2MTI_P1_IUC MTI_P1MTI_N1_IUC MTI_N1MTI_P2_IUC MTI_P2MTI_N3_IUC MTI_N3MTI_P3_IUC MTI_P3*These pins map to special purpose pads on the S32R274 MCU instead of general purposeMIPI-CSI2MIPI-CSI2DESCRIPTION PORT GND GND ETIMER_ETC0PC15 GND GNDCTE_RCS PF0GND GNDCTE_RFS PE13 GND GND SIUL_EIRQ13PA14 GND GND DSPI2_SCK PA11 GND GND DSPI2_CS0PA10 GND GND DSPI2_SIN PA13 GND GND DSPI2_SOUT PA12 GND GND ETIMER_ETC2PD1 GND GND GND GND GND GND GND GND GND GND GND GNDADC1_AN_0PB13 GND GND GND GND GND GND GND GND GND GNDSD_0_ADCP TP4 (EVB Test Pt.) SD_0_ADCN TP3 (EVB Test Pt.) GND GND GND GND GND GND MCU_CLK_SE TP1 (EVB Test Pt.) GND GND GND GND MCU_CLK_N XOSC_XTAL MCU_CLK_P XOSC_EXTAL GND GND GND GND GND GND GND GNDMIPI-CSI2DESCRIPTION PORT GND GND GND GND GND GNDTX2_PS PA7 GND GNDTX3_PS PA6 GND GNDTX1_PS PA8 GND GND RESET PI4 GND GND ERROR_N PA1 GND GND ERROR_RST PA4 GND GND SSN_MEM PA3 GND GND GND GND RESET_B RESET_B GND GND GND GND GND GND GND GND GND GND GND GND EIRQ_5PA5 GND GND GND GND GND GNDCSI_LANE1P CSI_LANE1P CSI_LANE1N CSI_LANE1N GND GNDCSI_LANE0N CSI_LANE0N CSI_LANE0P CSI_LANE0P GND GNDCSI_CLKP CSI_CLKP CSI_CLKN CSI_CLKN GND GND FRNT_END_REG FRNT_END_REG FRNT_END_REG FRNT_END_REG FRNT_END_REG FRNT_END_REG FRNT_END_REG FRNT_END_REG FRNT_END_REG FRNT_END_REG GND GNDEthernet Ethernet (DNP)DESCRIPTION PORTMTI_P0_IUC MTI_P0MTI_N0_IUC MTI_N0MTI_N2_IUC MTI_N2MTI_P1_IUC MTI_P1MTI_N1_IUC MTI_N1 MTI_P2_IUC MTI_P2 MTI_N3_IUC MTI_N3 MTI_P3_IUC MTI_P3MIPI-CSI2MIPI-CSI2DESCRIPTION PORTETIMER2_ETC3PC12SD_0_ADCN*SDADC0 Neg. Inp.SD_0_ADCP*SDADC0 Pos. Inp.CTE_RFS PE13DSPI2_SOUT PA12DSPI2_SIN PA13DSPI2_CS0PA10DSPI2_SCK PA11SIUL_EIRQ5PA5MCU_CLK_P*XOSC_XTAL (DNP)MCU_CLK_N*XOSC_EXTAL (DNP)ETIMER2_ETC0PB2MCU_CLK_SE*XOSC_EXTAL (DNP)ADC0_AN_0PB7RESET_B*RESET_BCTE_RCS PF0CSI_LANE2N*Lane2 Neg. Inp.CSI_LANE2P*Lane2 Pos. Inp.CSI_LANE0P*Lane0 Neg. Inp.CSI_LANE0N*Lane0 Pos. Inp.CSI_CLKN*Clock Neg. Inp.CSI_CLKP*Clock Pos. Inp.CSI_LANE1P*Lane1 Pos. Inp.CSI_LANE1N*Lane1 Neg. Inp.CSI_LANE3N*Lane3 Neg. Inp.CSI_LANE3P*Lane3 Pos. Inp.*These pins map to special purpose pads on the S32R274 MCU instead of general purposeS32R372141EVB: Programing InterfaceJTAGDESCRIPTION PINSupport for JTAG-capabledebugger such as USB Multilink J28JTAGS32R372141EVB: Power SupplyThe S32R372141EVB supports two power options. You can generate 12V from a DC generator and connect that to P2; or you can plug in a 12V power supply through the barrel connector P1. NXP does not directly sell 12V power supplies. You can obtain a power supply through a third-party vendor.Power supply specifications:Fully regulated Switching Power Supply Input Voltage 100-240V AC 50/60Hz Output 12V 1A/2A DCPlug size: 5.5mm x 2.1 mm, Center PositiveP1P2Package Level Pinout Diagram –S32R372 (141 BGA)Software Development Tools•S32 Design Studio IDE for Power Architecture•IDE & Compilers−Free S32 Design Studio IDE with GCC compiler−GHS MULTI Integrated Development Environment−Cosmic IDE−iSystems winIDEA IDE−Sourcery TM CodeBench Development Tools•Debuggers−Free OpenSDA debugger on board and supported by S32DS IDE −P&E USB Multilink−iSystems iC6000−Lauterbach TRACE32 JTAG DebuggerPre-Compiled Code Examples •Quick start examples forS32R372141EVB are available in the Quick Start Package to help familiarize you to the board•The QSP also includes application examples that demonstrate theS32R37’s radar capabilities. These include tutorial videos and a radar transceiver (COMING SOON)List of code examples:1.Hello World2.Hello World + PLL3.Hello World + PLL +Interrupts4.FlexCAN(coming soon)NOTE: Run these examples with S32DS for Power Architecture v2017.R1 or laterDocumentation and Reference Material•Documentation Links−S32R372 Datasheet−S32R372 Factsheet•Application Notes−S32R Radar Signal Compression−S32R27/37 Hardware Design Guide−Clock Monitor Unit Guide−e200 Core Memory Protection Unit Guide •Reference Manuals−S32R372 Family Reference Manual−S32R372 Family Safety ManualRadar Family –Product Feature Differences•S32R372 is the low-cost counterpart to the S32R274 radar processor •Selected features belowMCUFEATURESFlash*RAMEEPROMSecurity Transceiver InterfaceS32R274 2.0MB 1.5MB Emulate Yes 1 x 4-lane MIPI-CSI2 S32R372*Differences in memory are all in the Large Flash BlockRecommendations•For faster debugging, debug from RAM, because this cuts down the lengthy Flash erase operation cycles. Follow the Software Integration Guide (SWIG) for details.•By default “New Project” in S32 Design Studio IDE makes application to run at 16 MHz Internal RC (IRC) oscillator. For faster performance, configure PLL to desired frequency and switch clock source to PLL before executing application code.•Keep S32 Design Studio IDE and OpenSDA firmware Up-to-date for best results•Post Technical Questions on NXP community for MPC5xxx.•Useful Links:−S32R372 Webpage−S32R372141EVB Webpage−/s32ds−/community。

ST Solutions for IoTEMEA Marketing & ApplicationSeptember2017ST blocs for IoT2

SensingConnectivityPowerSecurityAnalogMCUEnvironmentalMotionMicrophonesSub-GHzBT, BLEWifi

Wireless chargingBat. ChargersSmart On/Off

Signal conditioningInterfacesBio-sensing

Low-powerSensor fusionAuthentication

Contactless paymentFast evaluation & prototyping3ST Augmenting the IoT Development

4

Hardware bricksSenseConnectTranslatePowerProcessActuateApplication ExamplesMiddleware LibrariesBoard Support PackageHardware Abstraction LayerVarious Dev. EnvironmentSoftware bricksCloud servicesWireless Sensor Nodes (WSN) Overview5

SensorsProduce a measurable response to a change in a physical condition like movement or pressureSignal is typically digitized in sensor device by an ADC and sent to controller for further processingSmart sensor device can do also data processing functionalities to save system power

假如我是纳米技术科学家英语作文If I Were a Nanoscientist.In the realm of scientific exploration, where the boundaries of human knowledge are constantly pushed, nanoscience emerges as a captivating and promising frontier. As a nanoscientist, I would embark on an extraordinary journey into the enigmatic world of the infinitesimally small, where the laws of nature take on a different dimension and the potential for transformative applications knows no bounds.Nanoscience delves into the manipulation of matter at the atomic and molecular scale, enabling the creation of materials and devices with unprecedented properties. As a nanoscientist, I would have the opportunity to unlock the mysteries of these microscopic building blocks and harness their unique characteristics to address some of the world's most pressing challenges.One area of particular interest to me is the development of advanced medical technologies. By manipulating nanoparticles, I could design targeted drug delivery systems that deliver therapeutic agents directly to diseased cells, minimizing side effects and maximizing treatment efficacy. Such advancements could revolutionize the treatment of chronic diseases like cancer, diabetes, and Alzheimer's, offering hope to millions of patients.Another promising application of nanoscience lies in the field of energy storage. The world is facing an urgent need for sustainable and efficient energy solutions. As a nanoscientist, I would strive to create high-performance batteries and fuel cells by engineering new nanomaterials with enhanced energy density and lifespan. These innovations could pave the way for a cleaner and more sustainable future.Nanoscience also has the potential to transform the electronics industry. By miniaturizing electronic devices to the nanoscale, I could create ultra-fast and energy-efficient computers, sensors, and communication devices.These miniaturized technologies would enable us to push the limits of computation, connect devices seamlessly, and enhance human-machine interaction in unprecedented ways.Beyond these tangible applications, nanoscience also holds immense potential for fundamental scientific discoveries. By exploring the behavior of matter at the nanoscale, I could contribute to our understanding of the basic laws of physics and chemistry. Such discoveries could lead to breakthroughs in fields ranging from cosmology to quantum computing.The path of a nanoscientist is not without its challenges. The tiny dimensions with which we work demand precision and ingenuity. But it is in overcoming these challenges that the greatest rewards lie. The ability to manipulate and understand the world at the nanoscale empowers us to create technologies that will shape the future of humanity.As a nanoscientist, I would be driven by a deep-seated curiosity and an unyielding passion for pushing theboundaries of human knowledge. I would embrace the opportunity to work alongside brilliant minds from diverse backgrounds, collaborating to solve complex problems and create solutions that will benefit society.The field of nanoscience is a testament to thelimitless potential of human ingenuity. As I embark on this extraordinary journey, I am filled with both excitement and trepidation. I am eager to explore the unknown, to make meaningful contributions to the scientific community, and to play a part in shaping a better future for all.In the words of the renowned physicist Richard Feynman, "There's plenty of room at the bottom." As a nanoscientist, I am eager to venture into this vast and uncharted realm, where the smallest of things hold the promise of transformative discoveries and the potential to change the world for the better.。

For Ultra-Pure Water Control in Semiconductor and Liquid Crystal ProcessesFeaturesWith the HE-960RW-GC, two sensors can now be connected to a single converter. The converter employs 2 independent built-in circuits, allowing simultaneous measurement ofresistivity at 2 different locations and the simultaneous display of the results for both Channel 1 and Channel 2 as well. The HE-960RW-GC is equipped with a function for inputting the deviation of the platinum temperature resistor (Pt1000 ). By using the temperature-certified TRD or TRL Series sensors, which already have the deviation entered, an accuracy within ±0.2°C can be obtained in temperature measurement even without temperature calibration. Temperature calibration can also be performed by comparing with a normal reference thermometer.Two transmission output systems are built into theHE-960RW-GC, allowing the desired data to be assigned from among the resistivity and temperature of each channel.2-channel simultaneous measurementHigh precision temperature compensation2-channel transmission outputsCE Marking compliant2-Channel Resistivity MeterSimultaneous Measurement and Simultaneous Output ofResistivity in 2 Locations Employs Chemical-Resistant SensorHE-960RW-GC2-C h a n n e l S i m u l t a n e o u s M e a s u r e m e n t & S i mu l t a n e o u s O u t p ut W o r l d 'sF i r s t A C h e m i c a l -r e s i s t a n tG l as s C a r b o n S e n s o r The HE-960RW-GC is a 2-channel simultaneous-measurement,resistivity meter that can be connected with two sensors.High performance and high precision is maintained while simultaneously measurement and simultaneously output of the resistivity of different 2 locations is carried out in a single converter for overall cost efficient performance. TheInstrument status on the HE-960RW-GC is indicated through an easy-to-understand icon display that eliminates operational errors. And, by setting a passcode, all key operation can be locked to prevent measurement errors caused by inadvertent operation. Icon-based status display & security functionBecause the electrode material is 100% carbon, theHE-960RW-GC’s sensor exhibits superior chemical resistance to various cleaning solutions, starting with hydrofluoric acid and hydrogen peroxide.Chemically resistant glass carbon sensorDC 24 V power source The HE-960RW-GC is also an environmentally-friendly product that uses lead-free solder for mounting chips on the PCB.http://www.horiba-adt.jp/index_e.htmHead Office 31 Miyanonishicho, Kisshoin Minami-ku, Kyoto, Japan Phone: 81-75-321-7184Fax: 81-75-321-7291Tokyo Sales Office Arute-Bldg. HigashiKanda.4th Fl, 1-7-8 Higashi-Kanda Chiyoda-ku, Tokyo, Japan Phone: 81-3-3851-3150Fax: 81-3-3851-3140Shanghai Office Room 1701, United Plaza,1468 Nanjing Rd. West,Shanghai 200040, ChinaPhone: 21-6289-6060Fax: 21-6289-5553Beijing OfficeRoom 1801, Capital Tower, Beijing, Tower 1 No. 6Jin,Jianguomenwai Ave.,Chaoyang District, Beijing,100022 China Phone: 10-8567-9966Fax: 10-8567-9066 HORIBA / STEC INCORPORATEDSanta Clara Head Office3265 Scott BoulevardSanta Clara,CA 95054, U.S.A.Phone: 1-408-730-4772Fax: 1-408-730-8975HORIBA EUROPE GmbH Head Office Hans-Mess-Str.6D-61440 Oberursel/Ts.GermanyPhone: 49-6172-1396-0 Fax: 49-6172-137385HORIBA KOREA L t d .112-6 Sogong-DongChoong-ku, Seoul, Korea Phone: 82-2-753-7911Fax: 82-2-756-4972HORIBA TRADING (SHANGHAI) Co., Ltd. HORIBA Advanced Techno, Co., Ltd. HORIBA Ltd.Taiwan Representative Office 3F NO.18 Lane 676, Chung Hua Rd, Chupei City,Hsinchu Hsien, 302, Taiwan Phone: 886-3-656-1012Fax: 886-3-656-8231HORIBA INSTRUMENTS Pte. Ltd.SINGAPORE 10 Ubi Crescent#05-11/12 Ubi Techpark Singapore 408564Phone: 65-745-8300Fax: 65-745-81550806SK23Bulletin:HAE-T0138C[Recycled Paper] Printed in JapanAustine Office 9701 Dessau Road Suite 605, Austin,TX 78754, U.S.A.Phone: 1-512-836-9560Fax: 1-512-836-8054HORIBA FRANCERue L. et A. Lumiere TechnoparcF-01630 St-Genis-Pouilly FrancePhone: 33-4-50-42-27-63Fax: 33-4-50-42-07-74HORIBA INSTRUMENTS LIMITED Kyoto CloseSummerhouse RoadMoulton Park, Northampton NN3 6FL, EnglandPhone: 44-1604-542600Fax: 44-1604-542696e-mail:*********************.jp225510202535115.5TT21EOpposite side 291632 26R3/4EFA-30 Series35251004034SpecificationsExternal dimensionsUnit: mm (in)Carbon SensorCarbon SensorConverterFlow Type HolderRc(PT)3/4Rc(PT)3/4Outlet for measured liquidInlet for measured liquid Low limit ofliquid levelPanel Cut SizeFlow type holder(min.)(m i n .)92+0.892+0.8 0118130HE-960RW-GCModelMeasuring method Sensor input Cell constantTemperature compensation element Measuring rangeRepeatability Linearity Transmission output Contact outputCommunication outputCalibration functionTransmission output holdfeatureSelf-diagnosis functionTemperature compensation Temperature compensation range Ultra-pure water specific resistance selection Clipping function Ambient environment Power supply Protective structureExternal dimensionsWeightConforming standardsCompatible sensorsHE-960RW-GCElectrode method (2-electrode method) 2-channel (Simultaneous Measurement) 0.1/cmPlatinum resistance 1000 / 0°CResistivity :0 to 2.00, 0 to 20.00, 0 to 100.0 M cm (0 to 20.00, 0 to 200.00, 0 to 1000 k m) Temperature :0 to 100°CWithin ±0.5% of the full scale (in equivalent input) Within ±0.5% of the full scale (in equivalent input) Number of outputs : 24mA to 20mA DC/0mA to 20mA DC : input/output isolated type Maximum load resistance : 900Transmission output range : Freely selectable within the measurement rangeHowever, repeatability and linearity will remain accurate to the separately set measuring range.(Negative terminals of each transmission output channel are connected inside and thus have the same electric potential.)Number of output : 4 points Alarm contact output (R1,R2,R3,R4)Contact type : relay contact, R1, R2, R3 : SPST R4 : SPDTContact rating : 240V AC 3A and 30V DC, 3A(resistance load)Contact function : selectable from upper/lower limit action (ON/OFF control), delay, and hysteresisOutput contents : selectable from the selected measurement, anomaly alarm, and maintenance.(However, R1 and R2, R3 and R4 share the COMMON contacts respectively.) RS-485 input/output Resistivity :input of cell constant correction coefficient (parameter input) Temperature : Calibrated by comparing with the reference thermometer Selectable from the Previous value hold and the Optional value hold.(However, only the previous value hold is available in the maintenance mode.) Sensor diagnosis error (short-circuit and disconnection of the temperature sensor ) Out of the measurement range Converter errorBased on the temperature characteristics of ultra-pure water (reference temperature:25°C)Based on the reference temperature and user-defined temperature coefficient (reference temperature :5 to 95°C, temperature coefficient : ±5%/°C) No temperature compensation0 to 100°CSelectable from 18.23(standard), 18.18, 18.24M cm(Selectable from 182.3, 181.8, 182.4k m) When the measured value is above the upper limit of the measurement range derived fromthe specified specific resisitance, the specified resistance is used as the measured value.Temperature: -5°C to 45°C, Relative humidity: 20% to 85%(without dew condensation) Rated voltage 24V DC, 10W(max)Panel: IP65, Rear case: IP20, Terminal: IP00 (Indoor-use panel installation type)96(W)×96(H)×115(D)mm, Case depth :approx.105mm (when panel-mounted) Approx.550g CE marking, FCC Part15 ERF-series specific resistance GC(Glass carbon)sensor, cell constant 0.1/cm Please read the operation manual before using this product to assure safe and proper handling of the product.The contents of this catalog are subject to change without prior notice, and without any subsequent liability to this company.It is strictly forbidden to copy the content of this catalog in part or in full.Measurement for the range of 0 to 100.0M cm(1000k m)is measurable without temperature coefficient. ERF-01-L-GC20 to 80°C 0 to 0.05MPa 10 m (Standard)PFAFlow type EFA-30 series PVDF 0.1/cm approx.Glass Carbon Perfluor rubber Threaded diameter : R(PT)3/4EFA-30P 0 to 100°C 0 to 0.1MPa 0 to 10L/minPVDF Inlet: Rc(PT)3/4, Outlet: Rc(PT)3/4Cell constantLiquidendmaterials Electrode Body Seal Cable length ModelModelLiquid temperature range Liquid pressure rangeLiquid temperature range Liquid pressure range InstallationCombined holder Connected pipe diameterLiquid flow rateLiquid end materials。

LBlock:A Lightweight Block CipherWenling Wu and Lei ZhangState Key Laboratory of Information Security,Institute of Software,Chinese Academy of Sciences,Beijing100190,P.R.China{wwl,zhanglei}@Abstract.In this paper,we propose a new lightweight block ciphercalled LBlock.Similar to many other lightweight block ciphers,the blocksize of LBlock is64-bit and the key size is80-bit.Our security evaluationshows that LBlock can achieve enough security margin against knownattacks,such as differential cryptanalysis,linear cryptanalysis,impossi-ble differential cryptanalysis and related-key attacks etc.Furthermore,LBlock can be implemented efficiently not only in hardware environ-ments but also in software platforms such as8-bit microcontroller.Ourhardware implementation of LBlock requires about1320GE on0.18μmtechnology with a throughput of200Kbps at100KHz.The softwareimplementation of LBlock on8-bit microcontroller requires about3955clock cycles to encrypt a plaintext block.Keywords:Block cipher,Lightweight,Hardware efficiency,Design,Cryptanalysis.1IntroductionWith the development of electronic and communication applications,RFID tech-nology has been used in many aspects of life,such as access control,parking management,identification,goods tracking etc.In this kind of new cryptogra-phy environment,the applications of RFID technology and sensor networking both have similar features,such as weak computation ability,small storage space, and strict power constraints.Therefore,traditional block ciphers such as AES are not suitable for this kind of extremely constrained environment.Hence,in recent years,research on lightweight ciphers has received a lot of pared with traditional block ciphers,lightweight ciphers have the following three main properties.Firstly,applications for constrained devices are unlikely to require the encryption of large amounts of data,and hence there is no requirement of high throughput for lightweight ciphers.Secondly,in this cryptography environment, attackers are lack of data and computing ability,which means lightweight ciphers only need to achieve moderate stly,lightweight ciphers are usually implemented in hardware environment,and small part of them are also imple-mented on software platforms such as8-bit microcontroller.Therefore,hardware performance will be the primary consideration for lightweight ciphers.Hardware efficiency can be measured in many different ways:the length of the critical path, J.Lopez and G.Tsudik(Eds.):ACNS2011,LNCS6715,pp.327–344,2011.c Springer-Verlag Berlin Heidelberg2011328W.Wu and L.Zhanglatency,clock cycles,power consumption,throughput,area requirements,and so on.Among them area requirement is the most important parameter,since small area requirement can minimize both the cost and the power consumption effi-ciently.Therefore,it has become common to use the term hardware efficient as a synonym for small area requirements,and the area requirements are usually measured as gate equivalents(GE).At present,for the hardware implementation of lightweight cipher,area requirements are usually dominated by the registers storing the data state and the key,since registers typically consist offlipflops which have a rather high area and power demand.For example,when using the standard cell library it requires between6and12GE to store a single bit[26]. Therefore,in the design of lightweight block ciphers,64-bit block size and80-bit key size are popular parameters.While there is a growing requirement of ciphers suited for resource-constraint applications,a series of lightweight block ciphers have been proposed recently, e.g.PRESENT[9],HIGHT[14],mCrypton[21],DESL[19],CGEN[28],MIBS[15], KATAN&KTANTAN[10],TWIS[23],SEA[30]etc.All of these ciphers are de-signed and targeted specifically for extremely constrained environments such as RFID tags and sensor networks.Among them,PRESENT is supposed to be very competitive,since its hardware requirement is comparable with today’s leading compact stream ciphers,and it is called an ultra-lightweight block cipher.Since its publication,only a few cryptanalytic results have been proposed against PRESENT,including the related-key rectangle attack on17-round PRESENT in[24]and the side-channel attacks described in[27,35].HIGHT has a32-round generalized Feistel structure.Its main feature is the compact round function which contains no S-box and all the operations are simple computations such as XOR,rotation,and addition operating on8-bit input.In respect of crypt-analysis,a related-key attack on full-round HIGHT was presented in ICISC2010, and an impossible differential attack on26-round HIGHT were presented in[24]. mCrypton can be considered as a miniature of the block cipher Crypton[20],and a related-key rectangle attack on8-round mCrypton has been reported in[25]. DESL and DESXL are lightweight modified versions of the well-known DES,and they adopt only one single S-box in order to minimize the hardware implementa-tion.CGEN employs a compact round function called mixtable operation,and the main design strategies include using afixed and per-device seed key which reduces the key scheduling and the decryption operation is not needed either. MIBS is a32-round Feistel cipher,and its round function employs SP-network with XOR operations as diffusion layer,whose hardware requirements are more expensive than the bitwise permutation used in PRESENT etc.KATAN and KTANTAN are a family of lightweight block ciphers which contain six vari-ants altogether.The KATAN family of ciphers all employ the same components, whose design strategy exploits some features of stream cipher[11].Meet-in-the-middle attacks to the KTANTAN family with a key of80bits were presented in [36].TWIS is inspired from the existing block cipher CLEFIA[29].However,a differential distinguisher with probability1for full-round TWIS was presented in[31].SEA is a Feistel cipher with scalable block and key sizes,and its roundLBlock:A Lightweight Block Cipher 329function only consists of rotation,XOR,and a single 3-bit S-box operations.TEA [33]and XTEA [34]are lightweight block ciphers proposed several years earlier.In this paper we propose a new lightweight block cipher called LBlock.The design of its structure and components,such as S-box layer,P permutation layer etc,all represent the trade-offbetween security and performance.Our se-curity analysis shows that full-round LBlock can provide enough security margin against known cryptanalytic techniques,such as differential cryptanalysis,linear cryptanalysis,impossible differential cryptanalysis,related-key attack etc.Fur-thermore,the performance evaluation of LBlock shows that not only hardware efficiency but also software implementations on 8-bit/32-bit platforms are ultra lightweight.The rest of this paper is organized as follows.Sect.2presents the specification of LBlock.Sect.3introduces the design rationale briefly.Sect.4and Sect.5describe the security analysis and performance evaluation of LBlock respectively.Finally,Sect.6concludes the paper.2Specification of LBlockThe block length of LBlock is 64-bit,and the key length is 80-bit.It employs a variant Feistel structure and consists of 32rounds.The specification of LBlock consists of three parts:encryption algorithm,decryption algorithm and key scheduling.2.1NotationsIn the specification of LBlock,we use the following notations:−M :64-bit plaintext −C :64-bit ciphertext −K :80-bit master key −K i :32-bit round subkey −F :Round function −s :4×4S-box −S :S-box layer consists of eight s in parallel −P,P 1:Permutations operate on 32-bit − :Bitwise exclusive-OR operation−<<<8:8-bit left cyclic shift operation −>>>8:8-bit right cyclic shift operation −||:Concatenation of two binary strings −[i ]2:Binary form of an integer i 2.2Encryption AlgorithmThe encryption algorithm of LBlock consists of a 32-round iterative structure which is a variant of Feistel network.The encryption procedure is illustrated in Fig.1.Let M =X 1||X 0denote a 64-bit plaintext,and then the data processing procedure can be expressed as follows.330W.Wu and L.ZhangX 1X 0<<<8cc K 1E F E h h h h h h h h h@@@@@@@@@h h h h h h h h h@@@@@@@@@c <<<8c c c K 32E F E X 32X 33Fig.1.Encryption procedure of LBlock1.For i =2,3,...,33,doX i =F (X i −1,K i −1)⊕(X i −2<<<8)2.Output C =X 32||X 33as the 64-bit ciphertextSpecifically,the components used in each round are defined as follows.(1)Round function FThe round function F is defined as follows,where S and P denote the confu-sion and diffusion functions which will be defined later.F :{0,1}32×{0,1}32−→{0,1}32(X,K i )−→U =P (S (X ⊕K i ))Fig.2illustrates the structure of round function F in detail.(2)Confusion function SConfusion function S denotes the non-linear layer of round function F ,and it consists of eight 4-bit S-boxes s i in parallel.S :{0,1}32−→{0,1}32Y =Y 7||Y 6||Y 5||Y 4||Y 3||Y 2||Y 1||Y 0−→Z =Z 7||Z 6||Z 5||Z 4||Z 3||Z 2||Z 1||Z 0Z 7=s 7(Y 7),Z 6=s 6(Y 6),Z 5=s 5(Y 5),Z 4=s 4(Y 4),Z 3=s 3(Y 3),Z 2=s 2(Y 2),Z 1=s 1(Y 1),Z 0=s 0(Y 0).LBlock:A Lightweight Block Cipher 331XK ic 'c c c c c c c c s 7s 6s 5s 4s 3s 2s 1s 0 ¨¨¨r r r$$$$$$ ¨¨¨r r r $$$$$$c c c c c c c c Fig.2.Round function FThe contents of eight 4-bit S-boxes are listed in Table 1.(3)Diffusion function PDiffusion function P is defined as a permutation of eight 4-bit words,and it can be expressed as the following equations.P :{0,1}32−→{0,1}32Z =Z 7||Z 6||Z 5||Z 4||Z 3||Z 2||Z 1||Z 0−→U =U 7||U 6||U 5||U 4||U 3||U 2||U 1||U 0U 7=Z 6,U 6=Z 4,U 5=Z 7,U 4=Z 5,U 3=Z 2,U 2=Z 0,U 1=Z 3,U 0=Z 1.2.3Decryption AlgorithmThe decryption algorithm of LBlock is the inverse of encryption procedure,and it consists of a 32-round variant Feistel structure too.Let C =X 32||X 33denotes a 64-bit ciphertext,and then the decryption procedure can be expressed as follows.1.For j =31,30,...,0,doX j =(F (X j +1,K j +1)⊕X j +2)>>>82.Output M =X 1||X 0as the 64-bit plaintext.2.4Key SchedulingThe 80-bit master key K is stored in a key register and denoted as K =k 79k 78k 77k 76......k 1k 0.Output the leftmost 32bits of current content of register K as round subkey K 1,and then operate as follows:1.For i =1,2,...,31,update the key register K as follows:(a)K <<<29(b)[k 79k 78k 77k 76]=s 9[k 79k 78k 77k 76][k 75k 74k 73k 72]=s 8[k 75k 74k 73k 72](c)[k 50k 49k 48k 47k 46]⊕[i ]2332W.Wu and L.Zhang(d)Output the leftmost32bits of current content of register K as roundsubkey K i+1.where s8and s9are two4-bit S-boxes,and they are defined in Table1.Table1.Contents of the S-boxes used in LBlocks014,9,15,0,13,4,10,11,1,2,8,3,7,6,12,5s14,11,14,9,15,13,0,10,7,12,5,6,2,8,1,3s21,14,7,12,15,13,0,6,11,5,9,3,2,4,8,10s37,6,8,11,0,15,3,14,9,10,12,13,5,2,4,1s414,5,15,0,7,2,12,13,1,8,4,9,11,10,6,3s52,13,11,12,15,14,0,9,7,10,6,3,1,8,4,5s611,9,4,14,0,15,10,13,6,12,5,7,3,8,1,2s713,10,15,0,14,4,9,11,2,1,8,3,7,5,12,6s814,9,15,0,13,4,10,11,1,2,8,3,7,6,12,5s94,11,14,9,15,13,0,10,7,12,5,6,2,8,1,33Design Rationale3.1StructureThe structure of LBlock is a variant of Feistel network,and its design decisions contain a lot of considerations about security and efficient implementations(such as area,cost and performance etc.).In the aspect of implementation,the most important consideration is the area requirement when implemented in hardware. Therefore,we try to reduce the number of S-boxes used in each round and also min-imize the size of each S-box used.Hence a Feistel-type structure seems a proper choice.Furthermore,for all kinds of generalized Feistel structures which operate less bits in each round,to achieve enough security margin they must take more rounds iteration which will affect its performance(such as speed and throughput). Therefore,in each round of LBlock,we choose only half of the data to go through round function F,and the other half applies a simple rotation operation.In the diffusion layer,we also choose to use permutation which can be implemented with no cost in hardware.However,instead of the bitwise permutation usually used, we apply a4-bit word-wise permutation which can be implemented cheaply not only in hardware but also in software environments such as8-bit microprocessor platforms.For example,the word-wise permutation in round function F can be combined with the S-box layer to form8×8table lookups.Moreover,we specif-ically choose the rotation offsets of right half in each round as8bits which can be omitted in8-bit platform implementation.On the other hand,in the aspect of security requirement,we choose the word-wise permutation carefully so that the structure of LBlock satisfies that in both encryption and decryption directions it can achieve best diffusion[32]in8rounds.Furthermore,the number of differential and linear active S-boxes both increase quickly,and the following Table2lists the guaranteed number of active S-boxes before20rounds.LBlock:A Lightweight Block Cipher333 Table2.Guaranteed number of active S-boxes of LBlockRounds DS LS Rounds DS LS10011222221112242432213272743314303054515323266616353578817363681111183939914141941411018182044443.2Diffusion LayerThe diffusion permutation of LBlock consists of two parts,namely the word-wise permutation in round function which is denoted as P,and the rotation of right half data in each round which is denoted as P1.Both of these permutations can be implemented by wiring in hardware which needs no additional area cost. For software environments such as8-bit and32-bit microprocessor platforms, P can be combined with the S-box layer in round function as table lookups and P1(8-bit rotation)can be implemented quite easily.Therefore,the diffusion permutations of LBlock can be implemented efficiently both in hardware and in software environments.Furthermore,the combination of P and P1can guarantee the best diffusion rounds and the least number of active S-boxes of LBlock.For example,there already exist at least32active S-boxes for15-round LBlock.3.3S-Box LayerOn the pursuit of hardware efficiency,we use4×4S-boxes s:F42→F42in pared with the regular8×8S-box,small S-box has much more advantage when implemented in hardware.For example,to implement the S-box of AES in hardware more than200GE are needed.On the other hand,for the4×4S-boxes used in LBlock,all of them can be implemented in hardware with only about22GE.Furthermore,in the aspect of security,the S-boxes used in LBlock are carefully chosen so that they all fulfill the following conditions:no fix point,completed,best non linearity,best differential probability,and good algebraic order etc.3.4Key SchedulingSimilar to many other lightweight block ciphers,the key scheduling of LBlock is also designed in a stream cipher way.We only apply simple rotation and non-linear operations to generate the round subkeys.First of all,the operation of 29-bit left rotation can be implemented freely in hardware,and it can also break the4-bit word structure,which helps to improve the security of LBlock against334W.Wu and L.Zhangrelated-key attacks.Secondly,we choose to use two4×4S-boxes as the non-linear operation which represents a trade-offbetween security and stly, the exact values of rotation offset,constants and positions of constant addition are carefully chosen,so as to avoid weak relations between round subkeys.4Security Evaluation4.1Differential CryptanalysisFor differential cryptanalysis,we adopt an approach to count the number of ac-tive S-boxes of differential characteristics.This is a regular method to evaluate the security against differential attack,which were adopted by many other block ciphers,such as AES[12],Camellia[1]and CLEFIA[29]etc.We found the guaranteed number of differential active S-boxes of LBlock by computer pro-gram,and the results before20-round are listed in Table2.Considering that there are at least32active S-boxes for15-round LBlock and the best differential probabilities of s i are all equal to2−2,then the maximum probability of differ-ential characteristics for15-round LBlock satisfies DCP15rmax ≤232×(−2)=2−64.This means there is no useful15-round differential characteristic for LBlock, since the block length of LBlock is only64-bit.Therefore,we believe that the full32-round LBlock is secure against differential cryptanalysis.4.2Linear CryptanalysisWe also apply the method of counting active S-boxes for the evaluation of LBlock against linear cryptanalysis.Since there are at least32active S-boxes for15-round LBlock and the best linear bias of each s i is2−2,the maximum bias oflinear approximations for15-round LBlock satisfies LCP15rmax ≤232−1·232×(−2)=2−33.Therefore,according to the complexity estimation of linear cryptanalysis, we can conclude that it is difficult tofind useful15-round linear-hulls which can be used to distinguish LBlock from a random permutation.As a result,we believe that the full32-round LBlock has enough security margin against linear cryptanalysis.4.3Impossible Differential CryptanalysisImpossible differential attack[3]is one of the most powerful cryptanalytic tech-niques,and its applications to many block ciphers(such as Camellia and CLEFIA etc.)represent the best cryptanalytic results obtained so far.We search for the impossible differential characteristic of LBlock using the algorithm proposed by Kim et al.[16].The best distinguisher found is the following14-round impossible differential characteristic:(00000000,00α00000)14r→(0β000000,00000000),(1)whereα,β∈{0,1}4\{0}represent non-zero differences.Note that by changing the positions ofα,β,we can construct other14-round impossible differential characteristics in a similar way.LBlock:A Lightweight Block Cipher335 Based on the14-round impossible differential distinguishers,we can mount a key recovery attack on20-round LBlock.The attack procedure can be described as follows.1.Choose a set of212plaintexts to construct a structure,where the4-bit wordsX0,1,X0,3and X1,2take all possible values and all the other words take con-stants.Then each structure can generate about223plaintext pairs satisfying the input difference(ΔX1,ΔX0)=(00000∗00,0000∗0∗0).Choose251 different structures which can generate about274candidate plaintext pairs.2.For each corresponding ciphertext structure after20-round encryption,choose the pairs satisfying the output difference(ΔX21,ΔX20)=(∗∗00∗∗0∗,000∗0∗∗0),where∗denotes non-zero difference.After this test,there remains about274×2−32=242candidate pairs.3.For every guess of28-bit subkey K20,0,K20,1,K20,2,K20,4,K20,5,K20,6,K20,7,partially decrypt Round20to check if the pairs satisfying(ΔX20,ΔX19)= (000∗0∗∗0,00∗0000∗).After this test,there remains about242×2−12=230 pairs.4.For every guess of the16-bit subkey K19,0,K19,2,K19,3,K19,5,partially de-crypt Round19to check if the pairs satisfying(ΔX19,ΔX18)=(00∗0000∗,∗0000000).After this test,there remains230×2−8=222pairs.5.For every guess of the8-bit subkey K18,1,K18,7,partially decrypt Round18to check if the candidate pairs satisfying(ΔX18,ΔX17)=(∗0000000,0∗000000).After this test,there remains about222×2−4=218pairs.6.For every guess of the4-bit subkey K17,6,partially decrypt Round17to checkif the candidate pairs satisfying(ΔX17,ΔX16)=(0∗000000,00000000).After this test,there remains about218×2−4=214pairs.7.For every guess of the8-bit subkey K1,2,K1,7,partially encrypt Round1tocheck if the candidate pairs satisfying(ΔX2,ΔX1)=(00∗00000,00000∗00).After this test,there remains about214×2−4=210pairs.8.For every guess of the4-bit subkey K2,5,partially encrypt Round2to checkif the candidate pairs satisfying the following equation:(ΔX3,ΔX2)=(00000000,00∗00000).9.If there still remains a pair satisfying the impossible differential,then the68-bit subkey guessed must be wrong.Delete it from the candidate subkey table.If the table of candidate subkey is not empty after analyzing all the remaining pairs,output the subkey remained in table as correct subkey. For each of the candidate pair in Step8,the probability that it satisfies the filtering condition is about2−4.Therefore,for a wrong subkey guess,the prob-ability of its remaining after Step8is about(1−2−4)210≈2−95.Then we can expect that after all thesefiltering,there remains about268×2−95≈2−27wrong subkey guess,and only the correct subkey will be output.The data and time complexities of above attack can be estimated as follows. First of all,we choose251structures and the data complexity is251×212=263 chosen plaintexts.The time complexity is dominated by Step7to Step8,and336W.Wu and L.Zhangeach step needs about278S-box operations.Therefore,the time complexity of the attack is about2×2×278×18×120≈272.720-round encryptions.According to the complexities of impossible differential attack on20-round LBlock,we expect that the full32-round LBlock has enough security margin against this attack.4.4Integral AttackSince LBlock is a4-bit word oriented cipher,we also consider that integral attack[18]may be one of the most powerful attacks against LBlock.The best integral characteristic found is the15-round distinguisher.Table3illustrates one of the15-round integral distinguisher in detail,where C denotes a constant word,A denotes an active word and B denotes a balanced word respectively. Note that by changing the position of C in plaintext,we can obtain similar integral distinguishers easily.Based on the15-round integral distinguisher,we can mount a key recovery attack up to20-round LBlock.For simplicity,wefirst give the integral attack on 18-round LBlock,and the attack procedure is as follows.1.Choose a set of260plaintexts to construct a structure,where only4-bitword takes a constant and all the other words take all the possible values of{0,1}60.Obtain the corresponding ciphertext after18-round encryption.Count the number of value X18,6,X18,4,X18,1,X19,6,X19,0occurs,and dis-card the values which occur even times.2.Guess corresponding subkeys to decrypt the ciphertexts.(a)For every guess of the8-bit subkey(K18,1,K18,4),partially decryptRound18to compute X17,4=s4(X18,4⊕K18,4)⊕X19,6and X17,6= s1(X18,1⊕K18,1)⊕X19,0.Table3.15-Round integral distinguisher of LBlockRounds Integral characterisitcs0AAAC AAAA AAAA AAAA1AAAC ACAC AAAC AAAA2CCCC AAAC AAAC ACAC3ACAC CCCC CCCC AAAC4CCCC ACCC ACAC CCCC5ACCC CCCC CCCC ACCC6CCCC CCCC ACCC CCCC7CCCC CCAC CCCC CCCC8CCCC CCCA CCCC CCAC9CCCC AACC CCCC CCCA10CCCC AAAC CCCC AACC11CCAA ACAA CCCC AAAC12CAAB AAAA CCAA ACAA13B?AA BBAA CAAB AAAA14?B?B?B?B B?AA BBAA15?????????B?B?B?BLBlock:A Lightweight Block Cipher 337(b)For every guess of the 4-bit subkey K 17,4,partially decrypt Round 17tocompute X 16,4=s 4(X 17,4⊕K 17,4)⊕X 18,6.(c)For every guess of the 4-bit subkey K 16,4,partially decrypt Round 16tocompute X 15,4=s 4(X 16,4⊕K 16,4)⊕X 17,6.3.Check if the equation ⊕lX 15,4=0is satisfied,where l is the number of plain-texts.If the equation is satisfied,then X 15,4is a balance word.Otherwise,guess another subkey and repeat until we get the correct subkey.The complexity of this attack can be estimated as follows.Step 1needs about 260plaintexts which requires 260encryptions.For the five words counted in Step 1,there are at most 220values.Therefore,the time complexity of Step 1to Step 3are less than 220×216encryptions.For a wrong subkey guess,the probability that equation ⊕lX 15,4=0is satisfied is about 2−4.Therefore,to discard all the wrong 16-bit subkey guesses,we need about five plaintext structures.Therefore,the total data and time complexities of this attack are both 5×260.Moreover,we can mount an integral attack on 20-round LBlock based on the 15-round integral distinguisher.The attack procedure is similar with the attack on 18-round LBlock,and we add two additional rounds in the end.Therefore,12subkey words need to be guessed and the data and time complexities will increase to about 13×260≈263.7.4.5Related-Key AttacksRecently,the combination of related-key [2,17]and traditional cryptanalysis has become one of the most powerful attacks,and its application to some ciphers has improved the cryptanalytic results significantly [4,6,7,8,13].Therefore,we have studied the possible related-key differential characteristic of LBlock so as to evaluate the security of LBlock against related-key attacks.In order to get related-key differential characteristic with high probability,we have to control the number of active S-boxes.Therefore,we first choose the output differences of 10S-boxes (8S-boxes in round function and 2S-boxes in key scheduling)in Round i all have hamming weight less than 2.Then we search for the related-key differential before Round i in the decryption direction and after Round i in the encryption direction respectively,and count the total number of active S-boxes.The best related-key differential obtained so far is a 13-round distinguisher with 26active S-boxes,and its probability is (2−2)25·(2−3)=2−53.For the 14-round related-key differential obtained,there are 32active S-boxes and its probability is less than (2−2)31·(2−3)=2−65.Table 4illustrates the propagation of 14-round related-key differential of LBlock in detail.5Performance Evaluation5.1Hardware PerformanceWe implemented LBlock in VHDL and synthesized it on 0.18μm CMOS tech-nology to check for its hardware complexity.Figure 3in Appendix III shows338W.Wu and L.ZhangTable4.14-Round related-key differential characteristic of LBlock RoundsΔX LΔRKΔI SΔO PΔX R 101200101000000000120010120012100012221212022000010000000002200001200101000120010130000000102000000020000012000010002200001400000002000000000000000200000100000000015000000000000000800000008000002000000000260000000000000000000000000000000000000000700000000000000000000000000000000000000008000000000000040000000400000010000000000090000100000000000000010000000001000000000100000001000000000000000100000000200001000110010000200020000001200020101010000000010120101110000000000010111002100201000100002133100221000000000310022102010201201011100142101201304000000250120134120021231002210parison of lightweight block cipher implementationsAlgorithm Block Key Area Speed LogicSize Size#GE kbps@100KHz Process XTEA64128349057.10.13μmHIGHT641283048188.20.25μmmCrypton641282500492.30.13μm DES6456230044.40.18μmDESXL64184216844.40.18μmKATAN6480105425.10.13μmKTANTAN648068825.10.13μmPRESENT648015702000.18μmLBlock648013202000.18μmthe datapath of an parallelization implementation of LBlock,which performs one round in one clock cycle.In this optimized implementation,we use a64-bit width datapath and implement the eight S-boxes of round function in parallel. Then,to encrypt64-bit plaintext with an80-bit key occupies about1320GE and requires32clock cycles.Table5compares the hardware performances of LBlock with other lightweight block ciphers.Specifically,in the above implementation the area requirement is occupied by flip-flops for storing the key and the data state.To store the80-bit key requires about480GE and to store the64-bit data state requires two32-bit registers (denoted as memleft and memright)which are about384GE.For round function F,it is consisted of the following three parts.The KeyAddition is a32-bit XOR operation which requires about87GE.The S-box layer consists of eight4×4 S-boxes in parallel,which requires about21.84×8=174.8GE.The diffusion layer P can be implemented by simple wiring and costs no area.Then in the end of each round,another32-bit XOR operation of two halves is needed which。

Compressed Sensing for Real-Time Energy-Efficient ECG Compression on Wireless Body Sensor Nodes Hossein Mamaghanian*,Student Member,IEEE,Nadia Khaled,Member,IEEE,David Atienza,Member,IEEE,and Pierre Vandergheynst,Senior Member,IEEEAbstract—Wireless body sensor networks(WBSN)hold the promise to be a key enabling information and communications technology for next-generation patient-centric telecardiology or mobile cardiology solutions.Through enabling continuous remote cardiac monitoring,they have the potential to achieve improved personalization and quality of care,increased ability of prevention and early diagnosis,and enhanced patient autonomy,mobility,and safety.However,state-of-the-art WBSN-enabled ECG monitors still fall short of the required functionality,miniaturization,and energy efficiency.Among others,energy efficiency can be improved through embedded ECG compression,in order to reduce airtime over energy-hungry wireless links.In this paper,we quantify the potential of the emerging compressed sensing(CS)signal acqui-sition/compression paradigm for low-complexity energy-efficient ECG compression on the state-of-the-art Shimmer WBSN mote. Interestingly,our results show that CS represents a competitive al-ternative to state-of-the-art digital wavelet transform(DWT)-based ECG compression solutions in the context of WBSN-based ECG monitoring systems.More specifically,while expectedly exhibit-ing inferior compression performance than its DWT-based coun-terpart for a given reconstructed signal quality,its substantially lower complexity and CPU execution time enables it to ultimately outperform DWT-based ECG compression in terms of overall en-ergy efficiency.CS-based ECG compression is accordingly shown to achieve a37.1%extension in node lifetime relative to its DWT-based counterpart for“good”reconstruction quality.Index Terms—Compressed sensing(CS),ECG compression, real-time ambulatory ECG monitoring,wireless body sensor nodes.I.I NTRODUCTIONO UR modern society is today threatened by an incipient health care delivery crisis caused by the current demo-graphic and lifestyle trends.On the one hand,the world’s popu-lation is fast aging resulting into an increased prevalence of car-diac disorders.On the other hand,our busy and often unhealthy lifestyles are fueling the rise of the number of people unsus-Manuscript received September23,2010;revised March8,2011;accepted April12,2011.Date of publication May19,2011;date of current version Au-gust19,2011.This work was supported in part by the the Swiss Confederation under the Nano-Tera.ch NTF Project BioCS-Node.This paper was presented in part at the Conference on Design,Automation and Test,Europe,2011.Asterisk indicates corresponding author.*H.Mamaghanian is with the School of Engineering,Ecole Polytech-nique F´e d´e rale de Lausanne,1015Lausanne,Switzerland(e-mail:hossein. mamaghanian@epfl.ch).N.Khaled,D.Atienza,and P.Vandergheynst are with the School of Engineer-ing,Ecole Polytechnique F´e d´e rale de Lausanne,1015Lausanne,Switzerland (e-mail:nadia.khaled@epfl.ch;david.atienza@epfl.ch;pierre.vandergheynst@ epfl.ch).Digital Object Identifier10.1109/TBME.2011.2156795pectingly developing or living with chronic cardiovascular con-ditions for decades.As a matter of fact,according to the World Health Organization,cardiovascular diseases are the number one cause of death worldwide,responsible for an estimated17.1 million deaths in2004(i.e.,29%of all deaths worldwide)and economic fallout in billions of dollars[1].These increasingly prevalent cardiac diseases are requiring escalating levels of su-pervision and medical management,which are contributing to skyrocketing health care costs and,more importantly,are un-sustainable for traditional health care infrastructures.Wireless body sensor network(WBSN)technologies promise to offer large-scale and cost-effective solutions to this problem.These solutions consist in outfitting patients with wearable,minia-turized and wireless sensors able to measure and wirelessly report cardiac signals to telehealth providers.They are poised to enable the required personalized,real-time and long-term ambulatory monitoring of chronic patients,its seamless integra-tion with the patient’s medical record and its coordination with nursing/medical support.While the resting ECG monitoring is standard practice in hospitals,its ambulatory counterpart is still facing many tech-nical challenges.For instance,the three-lead ECG is still nowa-days recorded on a rather bulky and obtrusive commercial data-logging(Holter)device during one tofive days of normal daily activities of a patient.These systems suffer from important lim-itations:limited autonomy,bulkiness,and no or limited wire-less connectivity.Recently,the realization of wireless-enabled low-power ECG monitors for ambulatory use has received sig-nificant industrial and academic interest.The most important highlights of these research and development efforts are:1) Toumaz’s Sensium Life Pebble TZ203082[2],an ultra-small and ultra-low-power monitor for heart rate,physical activity, and skin temperature measurements with a reported autonomy offive days on a hearing aid battery;2)Intel’s Shimmer[3], a small wireless wearable sensor platform able to record and wirelessly transmit three-lead ECG data as well as accelerom-eter,gyroscope,and galvanic skin response information;(3) IMEC’s wireless single-lead bipolar ECG patch[4]for ambu-latory monitoring claiming over ten days of monitoring on a 160mAh Li-ion battery(for undisclosed use conditions).The clinical relevance of thefirst system is still being validated,as Toumaz aims to achieve more than the system’s so far estab-lished accurate measurement of heart rate.The second system, which is based on commercial off-the-shelf components such as the TI MSP430microcontroller and the CC2420radio chip-set,operates on a Li-ion battery that provides about1Wh of energy.According to our measurements,it is able to support a0018-9294/$26.00©2011IEEEmaximum of6.5-day single-lead raw ECG sensing and storage on local memory.This autonomyfigure is reduced by25%,when the raw ECG data are wirelessly streamed using the ultra-low-power CC2420in a perfect point-to-point link with no wireless protocol overhead.More importantly,this autonomyfigure will undoubtedly dramatically decrease under realistic ambulatory monitoring.Finally,IMEC ultra-low-power wireless biopoten-tial sensor node achieves its enhanced autonomy due to a propri-etary customized ultra-low-power analog read-out ASIC[sig-nal acquisition,amplification,and analog-to-digital conversion (ADC)],a proprietary ultra-low-power ultra-wideband wireless transceiver,and more importantly,dedicated signal processors to preprocess and compress the sensed data using state-of-the-art techniques,in order to reduce the airtime over power-hungry wireless links.Based on these premises,it is today acknowledged that the achievement of truly WBSN-enabled ambulatory monitoring systems requires more breakthroughs not only in terms of ultra-low-power read-out electronics and radios,but also and increas-ingly so,in terms of ultra-low-power dedicated digital pro-cessors and associated embedded feature extraction and data compression algorithms.In this study,we explore a novel and promising approach based on the emerging compressed sens-ing(CS)framework to tackle the challenge of ultra-low-power embedded compression of ECG signals.More specifically,we quantify the potential of the CS signal acquisition/compression paradigm for low-complexity energy-efficient ECG compres-sion and show that it represents a competitive alternative to state-of-the-art ECG compression solutions in the context of WBSN-based monitoring systems.Since its early days in the1970s,ECG data compression has witnessed remarkable advances fueled by,on the one hand,the everincreasing wish of physicians to store the huge amounts of ECG data acquired in clinical practice,and on the other hand,the emergence of mobile telecardiology over bandwidth-limited public wireless networks.Until recently(and still practi-cally today),“mobile”telecardiology,however,referred to wire-less ECG communication from an ambulance or a patient’s home to the hospital.In these scenarios,the device imple-menting ECG data compression in real time is assumed to be a portable device with enough processing power and stor-age space to deploy powerful,but,complex algorithms.This explains the rich body of ECG compression techniques with ever-greater compression ratios(CRs)at the cost of ever-higher computational complexity.A concise overview of the most rel-evant techniques can be found in[5]–[7].Since our focus is on ECG compression solutions implementable in real time on WBSN nodes for future“personal”or“wearable”telecardi-ology,we will limit our review to those state-of-the-art algo-rithms that were shown to achieve competitive CRs while being amenable to efficient,fast,and low-memory-footprint imple-mentation on our target platforms.Interestingly,these algo-rithms are all based on the digital wavelet transform(DWT), namely,the embedded zerotree wavelet(EZW)[8],the set parti-tioning in hierarchical trees(SPIHT)[9],and thresholding-based algorithms[10],[11].Furthermore,the latter thresholding-based algorithm[11],where afixed percentage of wavelet coefficients are zeroed,was shown to outperform EZW and SPIHT at a lower computational cost.Therefore,it is the baseline algo-rithm against which the performance,computational complex-ity,and energy consumption of CS-based ECG compression are benchmarked.The prior art established the largely compressible nature of the ECG,as it can be very well approximated by a compact representation in the wavelet domain.Capitalizing on this spar-sity,we thus propose to apply the emerging CS approach to the acquisition and compression of this class of signals.This approach promises significant CRs while using computation-ally light linear encoders.It is particularly attractive for our target energy-constrained WBSN-based ECG monitoring sys-tems because:1)the sensor node can efficiently compress the acquired ECG signal through a small number of linear signal-independent measurements while preserving their underlying information;2)only this small number of measurements will be wirelessly transmitted to the remote telecardiology center,where the full record can be accurately reconstructed using complex, yet computationally feasible and numerically stable,nonlinear decoding.To the best of our knowledge,CS has never been applied to ECG.It has,however,been recently considered for efficient EEG acquisition and compression[12]–[14].The twofirst works have only focused on the sparse modeling of EEG signals and on assessing the efficiency of CS-based compression in terms of signal reconstruction errors.The work in[14]tried to estimate the low-power potential of CS for portable EEG systems using datasheet-extracted power consumptionfigures for the various components as well as estimates for the required amount of processing and wireless transmission.The measurement results reported in the present work for CS-based single-lead ECG compression on the commercial Shimmer indicate that their estimates are inaccurate.To the best of our knowledge,the present work introduces three main contributions:1)It is thefirst to thoroughly quan-tify the potential of CS for low-complexity energy-efficient ECG compression on resource-constrained WBSN platforms;2)to quantify this potential,it provides an exhaustive system-level comparison between CS-based and state-of-the-art DWT-based embedded ECG compression.This system-level compar-ison is based on embedded implementations of the two consid-ered ECG compression algorithms,which have been optimized for real-time implementation on a representative state-of-the-art WBSN mote,namely,Shimmer.In addition to the careful motivation of the various underlying tradeoffs and implementa-tion choices,this study proposes a comparative study of these algorithms in terms of signal reconstruction metrics,embedded memory usage,CPU execution time,and energy consumption;3)beyond the comparative study,our results reveal that the widely used general-purpose MSP430microcontroller[15]fails to efficiently support embedded processing and as such effec-tively limits the WBSN lifetime.More interestingly,our results show that outfitting WBSN platforms with more competitive ultra-low-power processors with advanced signal processing capabilities can substantially boost their energy efficiency and lifetime.Fig.1.Block diagram of the two ECG compression schemes implemented on the Shimmer wireless mote.II.M ETHODSThis study proposes a thorough system-level performance comparison between the state-of-the-art thresholding-based DWT algorithm of[11]and a CS-based algorithm in the context of ECG data compression on the embedded Shimmer wireless mote.These two algorithms are schematized in Fig.1.They both consist of three processing stages:a linear transformation isfirst applied to the original ECG signal,followed by an op-tional“sparsification”stage,and afinal encoding stage outputs the compressed signal to be wirelessly transmitted.As high-lighted in Fig.1,the fundamental difference between the two approaches lies in the fact that the former algorithm explicitly exploits the sparsity of the ECG signal by computing its sparse expansion and adaptively encoding the coefficients of this ex-pansion,while the latter algorithm nonadaptively acquires a few random measurements of the ECG signal and only implicitly re-lies on ECG signal sparsity to guarantee accurate reconstruction. This section describes further in detail the two algorithms and introduces the corresponding data models.Notation:In all the following,normal letters designate scalar quantities,boldface lower-case letters indicate column vectors, and boldface capitals represent matrices. a,b stands for the inner product of vectors a and b.Moreover,m i and M i,j are the i th entry of vector m and the(i,j)th entry of matrix M,respec-tively.Finally,(.)H and||.||p denote the conjugate transpose,and the l p-norm of a vector,respectively.A.Thresholding-Based DWT Compression AlgorithmFig.1(top)depicts the block diagram of this algorithm,as originally introduced in[11].Due to the limited on-chip mem-ory and real-time constraints,the digitized ECG signal is pro-cessed in nonoverlapping windows of N samples.Let x be the real-valued N-dimensional ECG signal vector corresponding to such a window(i.e.,x∈R N).x expands in an orthonormal Daubechies1wavelet basisΨ=[ψ1|ψ2|···|ψN]as follows:x=Ψα(1) whereαrepresents the N-dimensional coefficient vector.Given the highly sparse nature of x in the wavelet domain,most co-efficients inαcan be zeroed without much signal quality loss. Accordingly,for a target CR,the thresholding-based DWT com-pression algorithm[11]computesαS the S-sparse approxima-tion ofα,where all coefficients have been zeroed except the S 1While[11]used the biorthogonal bior4.4wavelet,we herein utilize the orthogonal Daubechies wavelets(db10)as the most popular wavelet family for ECG compression[16].largest values(S N),as illustrated in Fig.1.Then,thefinal encoding stage further removes any remaining redundancy be-tween consecutiveαS through a redundancy removal module. The output of this module,z,is subsequently uniformly quan-tized yielding the N-dimensional vectorˆz.The latter is encoded using lossless Huffman coding to produce the encoded vector c.B.CS-Based Compression AlgorithmSensing and processing information have traditionally relied on the Shannon sampling theorem,one of the central tenets of digital signal processing.This theorem states that,given a signal of bandwidthΩ,it is sufficient to sample it at2Ωsamples per second(i.e.,the Nyquist rate)to ensure faithful representation and reconstruction.However,this traditional ADC paradigm has been challenged lately.First,there are many situations where Ωis so large that constraints put on sampling architectures are simply unbearable.Second,even for relatively low signal band-widths such as our target wearable ECG application,given the established sparsity of the ECG signal,(above)Nyquist-rate sampling produces a large amount of redundant digital sam-ples,which are costly to wirelessly transmit,and severely limit the sensor nodes lifetime.If one sets course to design energy-efficient embedded ECG sensors,it is desirable to reduce the number of acquired ECG samples by taking advantage of the sparsity,or,the reduced“information rate”of the ECG signal. Compressed sensing is a methodology that has been recently proposed to address this problem[17]–[19].But,as we ar-gue herein,it is also particularly well suited for low-power implementations because it dramatically reduces the need for resource-(both processing and storage)intensive digital signal processing operations.The main idea behind CS is relatively simple and will be subsequently illustrated using the discrete-time data model introduced in Section II-A and Fig.1.As afore-mentioned,the original ECG signal x has a sparse approxima-tion,i.e.,it can be represented by a linear superposition of S elements of an orthonormal wavelet basis,x≈Sk=1αkψk2, with S N.Conventionally(as in Section II-A),one would collect ECG samples at the Nyquist rate forming x and then compress it using nonlinear digital compression techniques.CS offers a striking alternative by showing that you can collect roughly S samples using simple analog measurement wave-forms,thus sensing/sampling and compressing at the same time. Moreover,by merging the sampling and compression steps,CS removes a large part of the digital architecture.This so-called “analog CS,”where the compression occurs in the analog sen-sor read-out electronics prior to ADC is our ultimate goal.Its demonstration still requires extensive work on the analog sen-sor read-out electronics.Consequently,in the present work,we propose to approach it through“digital CS,”where the linear CS compression is applied after the ADC.Accordingly,as depicted in Fig.1(bottom),we collect M samples using simple measurement vectors{φi}1≤i≤M as y i=φH i x= φi,x ,i=1,...,M.Consequently,the CS lin-early compressed data vector y∈R M is described by y=Φx, 2For notational simplicity,the entries ofαare considered to be in a decreasing order.where Φdenotes the M ×N measurement or sensing matrixwith the vectors φH 1,···,φHM as rows.Then,the measurement vector y is directly encoded following the same steps as the DWT-based compression scheme of Section II-A.It is impor-tant to notice that the sensing matrix Φdoes not depend on the signal:CS proposes a simple linear sampling strategy that is only marginally off the optimal but complex best adaptive strategy.To guarantee the robust and efficient recovery of the S -sparse signal αS ,the sensing matrix Φmust obey the key restricted isometry property (RIP)[20],[21](1−δS )||α||2≤||ΦΨα||2≤(1+δS )||α||2(2)for all S -sparse vectors α.δS is the isometry constant of matrix Φ,which must be not too close to one.This property is difficult to verify.Practically,it is replaced by the requirement that the sensing matrix Φmust be such that its coherence μ(Φ,Ψ)with the sparsity basis Ψdefined as [22],[23]:μ(Φ,Ψ)=√N.max 1≤k,j ≤N| φk ,ψj |(3)is small enough.A universal good choice for the sensing matrix Φare random matrices,such as random matrices with indepen-dent identically distributed (i.i.d.)entries formed by sampling:1)a Gaussian distribution N (0,1/N );(2)a symmetric Bernoulli distribution (P (Φi,j =±1/√N )=1/2).Interestingly,many efficient sensing matrices can be constructed with simple pseu-dorandom design that can be generated and applied using a small amount of onboard memory and computational power.The price to pay for these advantages is a more complex decoder:the state of the art consists in recovering the original signal by solving a convex optimization problem.One important benefit of de-coding by optimization,though,is that CS decoders are notably robust to noise and quantization errors.This robustness makes it possible to work with lower precision digital arithmetic,and further enhances compression and reduces demands on digital back end and onboard memory.This is a feature that will be extensively exploited in our hardware implementation.If the RIP holds,then accurate reconstruction can be accom-plished by solving the following convex optimization problem:min ˜α∈R N ||˜α||1subject to||ΦΨ˜α−y ||2≤σ(4)where σbounds the amount of noise unavoidably corrupting thedata.Many algorithms were introduced to solve this reconstruc-tion problem,including interior-point algorithms [24],[25],gra-dient projection [26],iterative thresholding [27],and greedy ap-proaches such as orthogonal matching pursuit (OMP)[28],[29].Our results are based on the basis pursuit denoise algorithm pro-vided in the SPGL1solver [30].III.ECG D ATABASE AND P ERFORMANCE M ETRICSTo validate the performance of the considered compression schemes,we use the MIT-BIH Arrhythmia Database [31]that is the most commonly used database for the comparative study of ECG compression algorithms.This database contains 48half-hour excerpts of two-channel ambulatory ECG recordings,ob-tained from 47subjects studied by the BIH Arrhythmia Labora-TABLE IPRD AND CORRESPONDING QUALITY CLASS[32]tory.The recordings were digitized at 360samples per secondper channel with 11-bit resolution over a 10-mV range.Moreover,to quantify the compression performance while assessing the diagnostic quality of the compressed ECG records,we employ the two most widely used performance metrics,namely,the compression ratio and percentage root-mean-square difference (P RD )[5].CR is defined asCR =b orig −b compb orig×100(5)where b orig and b comp represent the number of bits requiredfor the original and compressed signals,respectively.The PRD,and associated SNR,quantifies the percent error between theoriginal signal vector x and the reconstructed ˜x:PRD =||x −˜x||2||x ||2×100(6)SNR =−20log 10(0.01PRD ).(7)The link between the measured PRD and the diagnostic dis-tortion is established based on the work of Zigel et al.on the weighted diagnostic measure for ECG signal compression [32],which classifies the different values of PRD based on the signal quality perceived by a specialist.Table I reports the resulting different quality classes and corresponding PRD.It is worth-while mentioning that x consistently refers to the original ECG signal with its dc component removed,which guarantees the relevance of the classification of Table I.IV .R EAL -T IME E MBEDDED C OMPRESSIONThis section first describes the target embedded sensor plat-form for which the two compression algorithms of Section II are optimized,implemented,and demonstrated.Then,it reports the most relevant platform-dependent optimizations introduced on the two original algorithms to achieve real-time execution and optimized processing and memory footprint.A.The Shimmer Embedded PlatformFrom the hardware viewpoint,the Shimmer mainboard in-cludes the low-power Texas Instrument 16-bit MSP430F1611microcontroller,a low-power CC2420IEEE 802.15.4-compliant radio,and a Bluetooth module.The MSP430mi-crocontroller runs at 8MHz,has 10kB of RAM,48kB of Flash and includes a fast hardware multiplier,but does not in-clude a floating-point unit.A three-lead ECG daughterboard may be connected to the internal connector pin of the Shimmer mainboard,with application to the skin via four conventional disposable electrodes.The ECG daughterboard was validated for ambulatory ECG for research purposes [3].Since our aim is to comparatively study the two compression algorithms onparison of the output SNR and PRD versus CR of the MATLAB version and the MSP430implementation for DWT-based compression.the standard MIT-BIH arrhythmia database,we did not perform real-time ECG acquisition via the ECG daughterboard,but al-ternatively used the Shimmer serial port to read in the database records resampled at256Hz,and to read out the encoded ECG data.From the software viewpoint,the open-source FreeRTOS ker-nel[33]was used to implement the real-time wireless communi-cation protocol.FreeRTOS is a light,real-time operating system for embedded devices that allows a strict control over the tim-ing of tasks and their relative priorities.We also chose Code Composer Essentials v3.2.0.24.2[34]from Texas Instruments to generate the binaries of both compression algorithms,for its superior and customizable optimization levels for assembly code generation.The compiler uses automatically the hardware mul-tiplier of the MSP430for multiplication operations,but since the MSP430does not include afloating-point unit,the compiler has to replace many arithmetic operations in the DWT-based compression algorithm by software emulation code,which im-plies a significant performance penalty if the proposed algorithm is simply compiled for Shimmer.Thus,we performed several implementation optimizations for improved execution time,as subsequently explained.B.Thresholding-Based DWT Compression Algorithm1)Linear transformation and sparsification:The ECG sam-ples in x are stored using12-bit resolution,their original and sparse wavelet expansion coefficientsαandαS,respectively, are both represented using12bits.Due to the limited10-kB RAM memory,it was determined that the largest processing window is of length N=512ECG samples acquired at the above-Nyquist sampling rate of256Hz.Moreover,due to the inefficient implementation offloating-point operations on the MSP430,the DWT had to be implemented on the plat-form using16-bit integer operations.This integer implementa-tion was instrumental to achieve real-time operation;it,how-ever,unavoidably introduced additional quantization errors. Fig.2depicts the output SNR and PRD of the double-precision MATLAB version and the MSP430integer implementation of the DWT-based compression algorithm,respectively.It clearly shows that the quantization error introduced in the MSP430 yields a reduction in signal quality.However,this reduction is marginal for high CRs that are the ones of interest for this study.2)Interpacket redundancy removal:Since no beat synchro-nization was performed3,there is no interpacket redundancy to be exploited between consecutiveαS.3)Huffman coding:Since the N-dimensional vectorαS is exactly S-sparse;we can either directly encode it or only encode its S nonzero entries and their corresponding indexes.The latter approach requires different codebooks for the coefficients and indexes,whereas the former obviously avoids the index code-book.Our simulations(omitted for lack of space)showed that thefirst approach has better performance for higher CRs due to the larger number of zeros in the coefficient vector,which are more efficiently encoded.The implementation of thresholding-based DWT compression requires4.6kB of RAM memory and 10kB of Flash memory,5kB of which is used for Huffman codebook storage.C.CS-Based Compression Algorithm1)Linear transformation:The implementation of Gaussian random sensing with matrixΦ∈R M×N requires the imple-mentation of a Gaussian-distributed random number generator on the embedded platform and the computation of a large ma-trix multiplication.This is too complex,time consuming,and is certainly not a real-time task for the MSP430.To address this problem,we explored three different approaches to the imple-mentation of the random sensing matrixΦ.a)Quantized Gaussian random sensing:We imple-mented an8-bit quantized version of a normal random number generator to formΦ.Our simulations showed no meaningful loss in signal quality between the quantized and the original floating-point normal random number generation.While this quantized version can be implemented on the MSP430,it was discarded for its important drawbacks:1)it uses the complex log and sqrt functions;2)for each input ECG vector,it requires the generation of and the multiplication by a large number of normal random numbers;3)it is clearly not real time,as it re-quires over1min to process a2-s ECG vector(i.e.,N=512 samples at the rate of256Hz).b)Pseudorandom sensing:We try to circumvent the on-board generation of the normal random numbers by storing them on the platform.Due to the memory constraints,which make it impossible to store the full Gaussian sensing matrix of size (M×N),we instead store one normal random column vector and generate the other columns of our sensing matrix by shuf-fling the positions of the entries of this vector.The shuffling process is as follows:The generated random vector is sorted, and the sorted index vector is used for successively reordering the original vector.Unfortunately,this process is also time con-suming as it summons a sorting algorithm in each iteration;a 2-s ECG vector is processed in16s.This is why we end up gen-erating a random index vector for shuffling the original vector. 3Beat synchronization entails a higher complexity and does not make sense for CS-based compression which in essence makes no attempt to comprehend the acquired signal.。