Power Supply Layout Considerations
Seminar Paper at: https://www.doczj.com/doc/f64246530.html,/lit/ml/slup230/slup230.pdf
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Agenda
DC Parasitics (Resistance) AC Parasitics Grounds and Grounding Thermal Considerations Design Examples
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You Mean Copper is Not a Perfect Conductor?
Since it is not, it impacts
Regulation Efficiency Temperature rise
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Sample Resistance Calculation
Material μΩ-cm 1.70 2.2 22.0 1.5 15 11 μΩ-in 0.67 0.87 8.66 0.59 5.91 4.3 Copper
tF low
Cu rre n
l
Gold Lead Silver Tin -Lead
A
Palladium
A ρ = resistivity
R=
ρl
The numbers given for Plated Copper are worst-case values. Typically, they will lie somewhere between pure copper and these values.
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Count Squares to Estimate Trace Resistance
Copper resistivity is 0.67 μΩ in. at 25°C and doubles for 254°C rise
Current Flow
l l
Thickness (mm/mils) 0.02/0.7 0.04/1.4 0.07/2.8 mΩ per Square (25oC) 1.0 0.5 0.2
R= R=
ρ (l ) ρ
t
1.3 0.65 0.26
t (l )
t
Copper Weight (Oz.) 1/2 1 2
mΩ per Square (100oC)
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Vias Have Resistance Too
Typical rule of thumb is 1 A to 3 A per via
Current Flow A
R=
1.5 mm (60 mils)
ρl
A
l
R=
ρl π (ro ? ri 2 )
2
4.5 mm (18 mils) 5 mm (20 mils)
2.36 × 10?6 × 0.06 R= = 2.4 mΩ π (0.012 ? 0.0092 )
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Agenda
DC parasitics (resistance) AC parasitics
When is a capacitor not a capacitor ?
Grounds and grounding Thermal considerations Design examples
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Capacitors Are Inductive…
Above Their Self-Resonant Frequency Measured ESL correlates well with rule of thumb inductance of 15 nH/inch
10 10 μF Ceramic
1 ZCAP - Impedance - Ω 5 nH 0.1 1000 μF OSCON 1 nH
0.01 180 μF Solid Polymer 470 μF Tantalum
0.001 0.1
1
10
100
1000
10000
f - Frequency - kHz
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Bypass Capacitor Layout
Minimize lead inductance
Minimize bypass loop area Short lengths on high di/dt paths Use ground planes where possible Bring current path across capacitor terminals
Parallel different capacitor types for reduced impedance across a frequency band Parallel different ceramic capacitors values and sizes to reduce impedance in the 2-20 MHz frequency range (0.1 μF & 0.01 μF) Draw your schematic so the layout person knows the critical routes
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Sample Capacitance Calculation
Consider two 10 mil traces crossing with 10 mil PWB thickness
A = 0.00025 m x 0.00025 m
t ? 10?9 ? ? 0.000252 ? C = 5? ? 36π ? ? 0.00025 ? ?? ? ? ?? ?
t Note: 10 mils = 0.00025 m
C=
ε R × εO × A
C = 0.01 pF
Not much capacitance but consider the area of all those components connected to the summing node
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Chaos Created by Noise Injection
Ten 0.05 x 0.02 in2 pads in summing junction can increase parasitic capacitance to 2 pF
VIN + 2 1 C5 C6 2 6 R9 C7 3 4 Critical Components R4 R6 R5 7 8 COMP FB RT GND + C9 SCP 5 L2 VOUT VCC R3 DTC OUT 1 C4 U1 TL5001D R1 Q1 C8
R7
C13
D1
CPARASITIC
GND
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And Inductors Turn Into Capacitors
Inductive at low frequency High frequency, distributed capacitance and μr reduction
100 C = 23 pF 10 L = 28 mH
Impedance - kΩ
1
1k
10 k
100 k Frequency - Hz
1M
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Self Inductance of PWB Traces
Due to the natural logarithmic relationship, large changes in conductor width have minimal impact on inductance
tF lo
l
w
Cu r
? ? l ? 1? L = 2l? ln? ? + ? nH (cm) ? ? ? ?t + w? 2? ? ? l ? 1? L = 5l? ln? ? + ? nH (in) ? ? ? ?t + w? 2?
T(mm/in) 0.07/0.0028 0.07/0.0028 0.07/0.0028 Inductance (nH/cm or nH/in) 10/24 6/14 2/6
t
w (mm/in) 0.25/0.01 2.5/0.1 12.5/0.5
re n
w
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PWB Traces Over Ground Planes
Substantial inductance reduction Inductance inversely proportional to width
w h
Current Flow
L= L=
2hl nH/cm w 5hl nH/in w
Inductance (nH/in) 0.5 3.0
Metric h (cm) 0.25 1.5 w (cm) 2.5 2.5 Inductance (nH/cm) 0.2 1.2 h (in) 0.01 0.06
English w (in) 0.1 0.1
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Magnetic Coupling
Consider alternate orientation of second inductor to minimize coupling
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Watch Out for Parasitic Components
Wiring inductance
Especially low impedance circuits-filters, power switching, timing Use ground planes and wide conductors to minimize
Board capacitance
High impedance or noise sensitive circuits Watch out for coupling between planes and to component pads
Magnetic coupling
Inductor to inductor, especially toroids, consider alternate mounting directions Loop to loop, minimize loop areas, use ground planes
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Agenda
DC parasitics (resistance) AC parasitics Grounds and grounding
Construction from the ground up
Thermal considerations Design examples
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Single Point Grounds
Series
1 2 3 1
Parallel
2 3
Simple wiring Common impedance causes different potentials High impedance at high frequency (>10 kHz)
Complicated wiring Low differential potentials at low frequencies High impedance at high frequency (>10 kHz)
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Multipoint Grounding
1 2 3
Ground Plane
Ground plane provides low impedance between circuits to minimize potential differences Also, reduces inductance of circuit traces Goal is to contain high frequency currents in individual circuits and keep out of ground plane
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Ground Planes
Don’t route ground plane under common mode inductors
CIND_PARASITIC 23 pF
3 cm2 (0.5 in2) area with 0.25 mm (0.01 in) thickness or 1 Layer of PWB
L1 28 mH
CPWB_A 50 pF Ground Plane
CPWB_B 50 pF
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