Telegraphos High-Speed Communications Architecture for Parallel and Distributed Computer Sy

毕 业 设 计（论 文）外 文 参 考资 料 及 译 文译文题目： CIC MegaCore Function 学生姓名： 高佳 学 号： 1021129024 专 业： 通信工程 所在学院： 龙蟠学院 指导教师： 姜志鹏 职 称： 讲师2013年11月06日CIC MegaCore Function----From DescriptionThis document describes the Altera CIC MegaCore function. The Altera CIC MegaCore function implements a cascaded integrator-comb filter with data ports that are compatible with the Avalon Streaming interface. CIC filters (also known as Hogenauer filters) are computationally efficient for extracting baseband signals from narrow-band sources using decimation, and for constructing narrow-band signals from processed baseband signals using interpolation.CIC filters use only adders and registers, and require no multipliers to handle large rate changes. Therefore, CIC is a suitable and economical filter architecture for hardware implementation, and is widely used in sample rate conversion designs such as digital down converters (DDC) and digital up converters (DUC).The Altera CIC MegaCore function supports the following features:■Support for interpolation and decimation filters with variable rate change factors (2 to 32,000), a configurable number of stages (1 to 12), and two differential delay options (1 or 2).■Single clock domain with selectable number of interfaces and a maximum of 1,024 channels.■Selectable data storage options with an option to use pipelined integrators.■Configurable input data width (1 to 32 bits) and output data width (1 to full resolution data width).■Selectable output rounding modes (truncation, convergent rounding, rounding up, or saturation) and Hogenauer pruning support.■Optimization for speed by specifying the number of pipeline stages used by each integrator.■Compensation filter coefficients generation.■Easy-to-use MegaWizard interface for parameterization and hardware generation.■IP functional simulation models for use in Altera-supported VHDL and Verilog HDL simulators.■DSP Builder ready.Cascaded Integrator Comb (CIC) filters are widely used in modern communication systems. As the signal processing in all aspects of requirements are constantly improve, in digital technology, the design of the filter appears increasingly important.Those who have signal processing ability of device can be referred to as a filter.In the modern telecommunications equipment and all kinds of control system, filter is widely used.Of all the electronic devices, using the most, the most widely used, technology is the most complex filter.Filter quality directly decides the product quality, good performance of filter can make the system more stable, so the filter of the countries all over the research and production has always been highly valued.With the wide application of digital technology, field programmable gate array (FPGA) has been the rapid development, integration and speed is growing.FPGA has high integration and reliability of the gate array (FPGA), and programmable resistance, maximum limit reduces the design cost, shorten the development cycle.Using CIC filters provides a silicon efficient architecture for performing sample rate conversion. This is achieved by extracting baseband signals from narrow-band sources using decimation, and constructing narrow-band signals from processed baseband signals using interpolation. The key advantage of CIC filters is that they use only adders and registers,and do not require multipliers to implement in hardware for handling large rate changes.A CIC filter (also known as a Hogenauer filter) can be used to perform either decimation or interpolation. A decimation CIC filter comprises a cascade of integrators (called the integrator section), followed by a down sampling block (decimator) and a cascade of differentiators (called the differentiator or comb section). Similarly an interpolation CIC filter comprises a cascade of differentiators, followed by an up sampling block (interpolator) and a cascade of integrators .In a CIC filter, both the integrator and comb sections have the same number of integrators and differentiators. Each pairing of integrator and differentiator is called a stage. The number of stages ( N ) has a direct effect on the frequency response of a CIC filter. The response of the filter is determined by configuring the number of stages N , therate change factor R and the number of delays in the differentiators (called the differential delay) M . In practice, the differential delay is set to 1 or 2.The MegaWizard interface only allows you to select legal combinations of parameters, and warns you of any invalid configurations .For high rate change factors, the maximum required data width for no data loss is large for many practical cases. To reduce the output data width to the input level, quantization is normally applied at the end of the output stage. In this case, the following rounding or saturation options are available:■Truncation : The LSBs are dropped. (This is equivalent to rounding to minus infinity.)■Convergent rounding . Also known as unbiased rounding . Rounds to the nearest even number . If the most significant deleted bit is one, and either the least significant of the remaining bits or at least one of the other deleted bits is one, then one is added to the remaining bits.■Round up: Also known as rounding to plus infinity. Adds the MSB of the discarded bits for positive and negative numbers via the carry in.■Saturation: Puts a limit value (upper limit in the case of overflow, or lower limit in the case of negative overflow) at the output when the input exceeds the allowed range. The upper limit is+2n-1 and lower limit is –2n.These rounding options can only be applied to the output st age of the filter. The data widths at the intermediate stages are not changed. The next section describes cases where the data width at the intermediate stages can be changed.Hogenauer pruning [Reference ] is a technique that utilizes truncation or rounding in intermediate stages with the retained numb er of bits decreasing monotonically from stage to stage, while the total error introduced is still no greater than the quantization error introduced by rounding the full precision output. This technique helps to reduce the number of logic cells used by the filter and gives better performance.The existing algorithms for computing the Hogenauer bit width growth for large N and R values are computationally expensive.For more information about these algorithms, refer to U. Meyer-Baese, Digital Signal Processing with Field Programmable Gate Arrays, 2nd Edition, Spinger, 2004.The CIC MegaCore function has pre-calculated Hogenauer pruning bit widths stored within the MegaCore function. There is no need to wait for Hogenauer pruning bit widths to be calculated if Hogenauer pruning is enabled for a decimation filter. Hogenauer pruning is only available to decimation filters when the selected output data width is smaller than the full output resolution data width.There are often many channels of data in a digital signal processing (DSP) system that require filtering by CIC filters with the same configuration. These can be combined into one filter, which shares the adders that exist in each stage and reduces the overall resource utilization. This combined filter uses fewer resources than using many individual CIC filters. For example, a two-channel parallel filter requires two clock cycles to calculate two outputs. The resulting hardware would need to run at twice the data rate of an individual filter. This is especially useful for higher rate changes where adders grow particularly large.To minimize the number of logic elements , a multiple input single output (MISO) architecture can be used for decimation filters, and a single input multiple output (SIMO) architecture for interpolation filters as described in the following sections.In many practical designs, channel signals come from different input interfaces. On each input interface, the same parameters including rate change factors are applied to the channel data that the CIC filter is going to process. The CIC MegaCore function allows the flexibility to exploit time sharing of the low rate differentiator sections. This is achieved by providing multiple input interfaces and processing chains for the high rate portions, then combining all of the processing associated with the lower rate portions into a single processing chain. This strategy can lead to full utilization of the resources and represents the most efficient hardware implementation. These architectures are known as multiple input single output (MISO) decimation filters.Single input multiple output (SIMO) is a feature associated with interpolation CIC filters. In this architecture, all the channel signals presented for filtering come from a single input interface.Like the MISO case, it is possible to share the low sampling rate differentiator section amongst more channels than the higher sampling frequency integrator sections. Therefore, this architecture features a single instance of the differentiator section, and multiple parallel instances of the integrator sections.After processing by the differentiator section, the channel signals are split into multiple parallel sections for processing in a high sampling frequency by the integrator sections. The sampling frequency of the input data is such that it is only possible to time multiplex two channels per bus, therefore the CIC filter must be configured with two input interfaces. Because two interfaces are required, the rate change factor must also be at least two to exploit this architecture. Up to 1,024 channels can be supported by using multiple input interfaces in this way.Single input multiple output (SIMO) is a feature associated with interpolation CIC filters. In this architecture, all the channel signals presented for filtering come from a single input interface. Like the MISO case, it is possible to share the low sampling rate differentiator section amongst more channels than the higher sampling frequency integrator sections.Therefore, this architecture features a single instance of the differentiator section, and multiple parallel instances of the integrator sections.After processing by the differentiator section, the channel signals are split into multiple parallel sections for processing in a high sampling frequency by the integrator sections.The required sampling frequency of the output data is such that it is only possible to time multiplex two channels per bus. Therefore the CIC filter must be configured with four output interfaces. Because four interfaces are required, the rate change factor must also be at least four to exploit this architecture, but in this example a rate change of eight is illustrated.SIMO architecture is applied when an interpolation filter type is chosen and the number of interfaces selected in the MegaWizard interface is greater than one.The total number of input channels must be a multiple of the number of interfaces. To satisfy this requirement, you may need to either insert dummy channels or use more than one CIC MegaCore function. Data is transferred as packets using AvalonStreaming interfaces. CIC filters have a low-pass filter characteristic. There are only three parameters (the rate change factor R , the number of stages N , and the differential delay M ) that can be modified to alter the passband characteristics and aliasing/imaging rejection. However, due to their drooping passband gains and wide transition regions, CIC filters alone cannot provide the flat passband and narrow transition region filter performance that is typically required in decimation or interpolation filtering applications.This problem can be alleviated by connecting the decimation or interpolation CIC filter to a compensation FIR filter which narrows the output bandwidth and flattens the passband gain.You can use a frequency sampling method to determine the coefficients of a FIR filter that equalizes the undesirable passband droop of the CIC and construct an ideal frequency response.The ideal frequency response is determined by sampling the normalized magnitude response of the CIC filter before inverting the response.Generally, it is only necessary to equalize the response in the passband, but you can sample further than the passband to fine tune the cascaded response of the filter chain.The Avalon-ST interface can also support more complex protocols for burst and packet transfers with packets interleaved across multiple channels.The Avalon-ST interface inherently synchronizes multi-channel designs, which allows you to achieve efficient, time-multiplexed implementations without having to implement complex control logic.CIC MegaCore函数----摘自 描述这篇文章对Altera公司的CIC 宏函数作了说明。

QAM is a widely used multilevel modulation technique,with a variety of applications in data radio communication systems.Most existing implementations of QAM-based systems use high levels of modulation in order to meet the high data rate constraints of emerging applications.This work presents the architecture of a highly parallel QAM modulator,using MPSoC-based design flow and design methodology,which offers multirate modulation.The proposed MPSoC architecture is modular and provides dynamic reconfiguration of the QAM utilizing on-chip interconnection networks,offering high data rates(more than1 Gbps),even at low modulation levels(16-QAM).Furthermore,the proposed QAM implementation integrates a hardware-based resource allocation algorithm that can provide better throughput and fault tolerance,depending on the on-chip interconnection network congestion and run-time faults.Preliminary results from this work have been published in the Proceedings of the18th IEEE/IFIP International Conference on VLSI and System-on-Chip(VLSI-SoC2010).The current version of the work includes a detailed description of the proposed system architecture,extends the results significantly using more test cases,and investigates the impact of various design parameters.Furthermore,this work investigates the use of the hardware resource allocation algorithm as a graceful degradation mechanism,providing simulation results about the performance of the QAM in the presence of faulty components.Quadrature Amplitude Modulation(QAM)is a popular modulation scheme,widely used in various communication protocols such as Wi-Fi and Digital Video Broadcasting(DVB).The architecture of a digital QAM modulator/demodulator is typically constrained by several, often conflicting,requirements.Such requirements may include demanding throughput, high immunity to noise,flexibility for various communication standards,and low on-chip power.The majority of existing QAM implementations follow a sequential implementation approach and rely on high modulation levels in order to meet the emerging high data rate constraints.These techniques,however,are vulnerable to noise at a given transmission power,which reduces the reliable communication distance.The problem is addressed by increasing the number of modulators in a system,through emerging Software-Defined Radio (SDR)systems,which are mapped on MPSoCs in an effort to boost parallelism.These works, however,treat the QAM modulator as an individual system task,whereas it is a task that can further be optimized and designed with further parallelism in order to achieve high data rates,even at low modulation levels.Designing the QAM modulator in a parallel manner can be beneficial in many ways.Firstly, the resulting parallel streams(modulated)can be combined at the output,resulting in a system whose majority of logic runs at lower clock frequencies,while allowing for high throughput even at low modulation levels.This is particularly important as lower modulation levels are less susceptible to multipath distortion,provide power-efficiency and achieve low bit error rate(BER).Furthermore,a parallel modulation architecture can benefit multiple-input multiple-output(MIMO)communication systems,where information is sent and received over two or more antennas often shared among many ing multiple antennas at both transmitter and receiver offers significant capacity enhancement on many modern applications,including IEEE802.11n,3GPP LTE,and mobile WiMAX systems, providing increased throughput at the same channel bandwidth and transmit power.Inorder to achieve the benefit of MIMO systems,appropriate design aspects on the modulation and demodulation architectures have to be taken into consideration.It is obvious that transmitter architectures with multiple output ports,and the more complicated receiver architectures with multiple input ports,are mainly required.However,the demodulation architecture is beyond the scope of this work and is part of future work.This work presents an MPSoC implementation of the QAM modulator that can provide a modular and reconfigurable architecture to facilitate integration of the different processing units involved in QAM modulation.The work attempts to investigate how the performance of a sequential QAM modulator can be improved,by exploiting parallelism in two forms:first by developing a simple,pipelined version of the conventional QAM modulator,and second, by using design methodologies employed in present-day MPSoCs in order to map multiple QAM modulators on an underlying MPSoC interconnected via packet-based network-on-chip (NoC).Furthermore,this work presents a hardware-based resource allocation algorithm, enabling the system to further gain performance through dynamic load balancing.The resource allocation algorithm can also act as a graceful degradation mechanism,limiting the influence of run-time faults on the average system throughput.Additionally,the proposed MPSoC-based system can adopt variable data rates and protocols simultaneously,taking advantage of resource sharing mechanisms.The proposed system architecture was simulated using a high-level simulator and implemented/evaluated on an FPGA platform.Moreover, although this work currently targets QAM-based modulation scenarios,the methodology and reconfiguration mechanisms can target QAM-based demodulation scenarios as well. However,the design and implementation of an MPSoC-based demodulator was left as future work.While an MPSoC implementation of the QAM modulator is beneficial in terms of throughput, there are overheads associated with the on-chip network.As such,the MPSoC-based modulator was compared to a straightforward implementation featuring multiple QAM modulators,in an effort to identify the conditions that favor the MPSoC implementation. Comparison was carried out under variable incoming rates,system configurations and fault conditions,and simulation results showed on average double throughput rates during normal operation and~25%less throughput degradation at the presence of faulty components,at the cost of approximately35%more area,obtained from an FPGA implementation and synthesis results.The hardware overheads,which stem from the NoC and the resource allocation algorithm,are well within the typical values for NoC-based systems and are adequately balanced by the high throughput rates obtained.Most of the existing hardware implementations involving QAM modulation/demodulation follow a sequential approach and simply consider the QAM as an individual module.There has been limited design exploration,and most works allow limited reconfiguration,offering inadequate data rates when using low modulation levels.The latter has been addressed through emerging SDR implementations mapped on MPSoCs,that also treat the QAM modulation as an individual system task,integrated as part of the system,rather than focusing on optimizing the performance of the modulator.Works inuse a specific modulation type;they can,however,be extended to use higher modulation levels in order toincrease the resulting data rate.Higher modulation levels,though,involve more divisions of both amplitude and phase and can potentially introduce decoding errors at the receiver,as the symbols are very close together(for a given transmission power level)and one level of amplitude may be confused(due to the effect of noise)with a higher level,thus,distorting the received signal.In order to avoid this,it is necessary to allow for wide margins,and this can be done by increasing the available amplitude range through power amplification of the RF signal at the transmitter(to effectively spread the symbols out more);otherwise,data bits may be decoded incorrectly at the receiver,resulting in increased bit error rate(BER). However,increasing the amplitude range will operate the RF amplifiers well within their nonlinear(compression)region causing distortion.Alternative QAM implementations try to avoid the use of multipliers and sine/cosine memories,by using the CORDIC algorithm, however,still follow a sequential approach.Software-based solutions lie in designing SDR systems mapped on general purpose processors and/or digital signal processors(DSPs),and the QAM modulator is usually considered as a system task,to be scheduled on an available processing unit.Works inutilize the MPSoC design methodology to implement SDR systems,treating the modulator as an individual system task.Results in show that the problem with this approach is that several competing tasks running in parallel with QAM may hurt the performance of the modulation, making this approach inadequate for demanding wireless communications in terms of throughput and energy efficiency.Another particular issue,raised in,is the efficiency of the allocation algorithm.The allocation algorithm is implemented on a processor,which makes allocation slow.Moreover,the policies used to allocate tasks(random allocation and distance-based allocation)to processors may lead to on-chip contention and unbalanced loads at each processor,since the utilization of each processor is not taken into account.In,a hardware unit called CoreManager for run-time scheduling of tasks is used,which aims in speeding up the allocation algorithm.The conclusions stemming from motivate the use of exporting more tasks such as reconfiguration and resource allocation in hardware rather than using software running on dedicated CPUs,in an effort to reduce power consumption and improve the flexibility of the system.This work presents a reconfigurable QAM modulator using MPSoC design methodologies and an on-chip network,with an integrated hardware resource allocation mechanism for dynamic reconfiguration.The allocation algorithm takes into consideration not only the distance between partitioned blocks(hop count)but also the utilization of each block,in attempt to make the proposed MPSoC-based QAM modulator able to achieve robust performance under different incoming rates of data streams and different modulation levels. Moreover,the allocation algorithm inherently acts as a graceful degradation mechanism, limiting the influence of run-time faults on the average system throughput.we used MPSoC design methodologies to map the QAM modulator onto an MPSoC architecture,which uses an on-chip,packet-based NoC.This allows a modular, "plug-and-play"approach that permits the integration of heterogeneous processing elements, in an attempt to create a reconfigurable QAM modulator.By partitioning the QAM modulator into different stand-alone tasks mapped on Processing Elements(PEs),weown SURF.This would require a context-addressable memory search and would expand the hardware logic of each sender PE's NIRA.Since one of our objectives is scalability,we integrated the hop count inside each destination PE's packet.The source PE polls its host NI for incoming control packets,which are stored in an internal FIFO queue.During each interval T,when the source PE receives the first control packet,a second timer is activatedfor a specified number of clock cycles,W.When this timer expires,the polling is halted and a heuristic algorithm based on the received conditions is run,in order to decide the next destination PE.In the case where a control packet is not received from a source PE in the specified time interval W,this PE is not included in the algorithm.This is a key feature of the proposed MPSoC-based QAM modulator;at extremely loaded conditions,it attempts to maintain a stable data rate by finding alternative PEs which are less busy.QAM是一种广泛应用的多级调制技术，在数据无线电通信系统中应用广泛。

ABI 应用二进制接口(Application Binary Interface)ACSI 国家信息化咨询委员会（advisory committee for state informatization）ADSL 非对称数字用户线路(Asymmetric Digital Subscriber Line)AI 人工智能（artificial intelligence）AMPS 高级移动电话系统(Advanced Mobile Phone System)API 应用程序接口(Application Programming Interface)ASIC 特定用途集成电路（Application Specific Integrated Circuit）ASTM 美国试验材料学会（American Society for Testing Material）AT&T 美国电话电报公司（American Telephone and Telegraph Company）ATM 异步传输模式(Asynchronous Transfer Mode)ATOS Origin 源讯公司Auto-ID 自动识别（Auto-ID）AWS 美国航空气象处（Air Weather Service）；BAP 基本汇编程序（Basic Assembler Program）BGA 集成电路采用有机载板的一种封装法BOINC 伯克利开放式网络计算 (Berkeley Open Infrastructure For Network Computing ) BSP 板级支持包(Board Support Package)Business Processing 业务处理流程CaaS 通信即服务(communication as a Service)CAN 控制器局域网络(Controller Area Network)CAS 中国科学院（Chinese Academy of SciencesCCTV 中国中央电视台（China Central Television）CDMA2000 电信移动通信系统CIP 预编目录（cataloging in publication）CITYNET 城市间合作网络CMU 卡内基梅隆大学（Carnegie Mellon University）CN 通信网络（Communicating Net）CPU 中央处理机（Central Processing Unit）CRA 应答验证 (challenge-response authentication)DARPA 美国国防部高级研究计划局（Defense Advanced Research Projects Agency）DARPA 研究计划署(Defense Advanced Research Projects Agency)DASH7Data mining 数据挖掘技术（即指从资料中发掘资讯或知识）DDoS 分布式拒绝服务（Distributed Denial of Service）DG INFSO 媒体总司DG INFSO/D4 欧盟委员会DGINFSO‐D4DMM 分布式内存多处理器（distributed memory multiprocessor）DNS 域名服务器（Domain Name Server）DoD 美国国防部（Department of Defense of the United States）DRAM 动态随机存取存储器（Dynamic Random Access Memory）DSL 数字用户线路(Digital Subscriber Line)DSP 数字信号处理器（Digital Signal Processor）DSS 决策支持系统（Decision Support Systems）DynDNS 动态DNSEAN 欧洲商品编码(Europ Article Number)EAS 电子防窃系统（Electronic Article Surveillance）ECMA 欧洲电脑制造商协会（European Computer Manufactures Association）EPC 电子产品代码(Electronic Product Code)EPCglobal 国际物品编码协会EAN和美国统一代码委员会（ UCC ）的一个合资公司ERP 企业资源计划（Enterprise Resource Planning）ETSI 欧洲电信标准协会（European Telecommunication Standards Institute）EU-funded CASAGRAS1 coordination 欧盟资助CASAGRAS1协调FAT 文件分配表(File Allocation Table)FP7 欧盟第七框架计划(Framework Program 7)FreeOTFE 免费实时加密FSTC 金融服务技术联盟(Financial Services Technology Consortium)FTP 文件传输协议（File Transfer Protocol）GM 通用汽车公司（General Motors）GMSA 全球移动通信系统协会(global system for mobile communications association) GPRS 通用分组无线业务（General Packet Radio Service）GPS 全球定位系统（Global Position System）GSM 全球移动通信系统（Global System for Mobile Communications）GUI-based 图形用户界面HP 惠普公司HTML5 HTML5是HTML下一个的主要修订版本，现在仍处于发展阶段HTTP 超文本传输协议（Hyper Text Transport Protocol）HTTPS 安全超文本传输协议(Hypertext Transfer Protocol Secure)I²C 两线式串行总线（Inter－Integrated Circuit）IaaS 架构即服务(Infrastructure As A Service)IATA 国际航空运输协会（International Air Transport Association）ICC 集成电路卡(integrated circuit card)ICT 集成电路计算机遥测技术（Integrated Computer Telemetry）iDA 资讯通信发展管理局(infocomm Development Authority)IEC 国际电工技术委员会（International Electrotechnical Commission）IEEE 电气与电子工程师协会（Institute of Electrical and Electronic Engineers）IETF Internet工程任务组（Internet Engineering Task Force）IMT-2000 国际移动电话系统-2000（International Mobile Telecom System-2000）IOT 物联网(Internet Of Things)IPSec 网际协议安全（Internet Protocol Security）IPSO 因特网协议安全选件（Internet protocol security option ）IPv4 IPv4，是互联网协议（Internet Protocol，IP）的第四版IR 指令寄存器（instruction register）ISA 工业标准总线(Industry Standard Architecture)ISM 美国供应管理协会（the Institute for Supply Management , ISM）ISO 国际标准化组织（International Standardization Organization）ISTAG IST咨询集团(IST advisory group)IT 信息技术(Information Technology)ITSO_LtdITU 国际电信联盟（International Telecommunication Union）KAEC 阿卜杜拉国王经济城(King Abdullah Economic City)KVM 基于内核的虚拟机（K Virtual Machine）LAN 局域网（local area network）LCD 液晶显示屏（liquid crystal display）LR-WPAN 低速率无线个人区域网络（Low Rate-Wireless Personal Area Network）LSI 大规模集成电路（Large Scale Integrated circuit）MAC 多路存取计算机（Multi-Access Computer)MAN 城域网(Metropolitan Area Network)MASDAR 马斯达尔MEMS 微电子机械系统（Micro-electromechanical Systems）METI 日本经济贸易产业省（Ministry of Economy， Trade and Industry）MIC 部门内部事务和通讯(the ministry of internal affairs and communications) MIT 麻省理工学院（Massachu-setts Institute of Technology）；MPP 大量信息并行处理机，大规模并行处理机（Massively Parallel Processor）MRI 核磁共振成像（Magnatic Resonance Imaging）；MSI 中规模集成电路（medium-scale integration）MVNO AdicaNaaS 网络即服务(Network As A Service)NASA 美国国家航空和宇宙航行局（National Aeronautics and Space Administration）NetBSD 一个免费的，具有高度移植性的UNIX-like操作系统NFC 近场通讯(Near Field Communication)NFCIPNIC 网络接口卡(Network Interface Card)NMT 北欧移动电话(Nordic Mobile Telephone)NSF （美国）国家科学基金会（National Science Foundation）NTT DoCoMo 移动通信网公司NYU 纽约大学（New York University）OLED 有机发光二极管（Organic Light Emitting Diode）ONS 国家统计局(Office For National Statistics)P2P 点对点技术（peer-to-peer）；PaaS 平台即服务(Platform As A Service)PARC 帕洛阿尔托研究中心（Palo Alto Research Center）PC 个人电脑（Personal Computer）；PCI 外部控制器接口（Peripheral Component Interconnect）PHY 物理层协议（Physical Layer）PKI 公钥基础设施（Public Key Infrastructure）POTS 普通老式电话服务(Plain Old Telephone Service)QNX 嵌入式实时操作系统（Quick Unix ）R&D 研发(Research & Development)RACO 德国雷科resPONDER 响应器RFID 无线射频识别（radio frequency identification devices）RISC 精简指令集计算机（Reduced Instruction-Set Computer）ROM 只读存储器（read only memory）RS-232 串行数据通信的接口标准RTOS 实时操作系统（Real Time Operating System）SaaS 软件即服务（Software as a Service）SAP SAP是目前全世界排名第一的ERP软件SAVVIS 维斯公司SCADA 监测控制和数据采集（supervisory control and data acquisition）SIM 用户身份识别卡（subscriber identity module）SIMD 单指令多数据(Single Instruction Multiple Data)SIMIT 中国科学院上海微系统与信息技术研究所SMP 对称多处理机（SymmetricalMulti-Processing）SOC 片上系统（System on a Chip）SPOM 自动程序单芯片微处理(Self Programmable One Chip Microprocessor)SPT 季票 (season parking ticket)SRI 斯坦福研究院(Stanford Research Institute)SSE 单指令多数据流式扩展 ( streaming SIMD extensions)SSI 小规模集成（电路）（Small Scale Integration）；SSO 单点登录（single sign-on）T2TITTACS 全接入通信系统（Total Access Communication System）TCB 可信计算基(Trusted Computing Base)TCP/IP 传输控制/网络通讯协定（Transmission Control Protocol / Internet Protocol）TD-SCDMA 即时分同步的码分多址技术（Time Division-Synchronization Code Division Multiple Access）TEDS 传感器电子数据表（Transducer Electronic Data Sheet）TLS/SSL SSL（Secure Sockets Layer，安全套接层）TPANSmitterTRON 实时操作系统核心程序（The Realtime Operating System Nucleus）U.S.Department of Defence 美国国防部UCC 统一编码委员会（uniform code council inc）UCLA 加州大学洛杉矶分校（University of California at Los Angeles）UHF 超高频（Ultra High Frequency）UML 统一建模语言（Unified Modeling Language）UNL 无处不在的网络实验室（ubiquitous networking laboratory）USAID 美国国际开发署（United States Agency for International Development）USB 通用串行总线（Universal Serial Bus）USDA 美国农业部（United States Department of Agriculture）VLSI 超大规模积体电路（Very Large Scale Integrated Circuites）VNP-VNOWAN 广域网(Wide Area Network)WCDMA 宽带码分多址移动通信系统（Wideband Code Division Multiple Access）Wi-Fi 无线上网技术WROM 一次写/读很多内存(write once/read many memory)WSN 无线传感网络(wireless sensor network)。

通信工程专业英语词汇来源：李涛的日志动态范围: Dynamic range频率偏值: Frequency offset符号率：Symbol rate码域功率：code domain power频分多址: Frequency Division Multiple Access码分多址: Code Division Multiple Access时分多址: Time Division Multiple Access沃什码：Walsh code误码率：Bit Error Rate，BER帧误码率：Frame Error Rate，FER循环冗余码：Cyclic Redundancy Code，CRC时序分析：timing analyze门限：threshold非同步模式：Asynchronous Mode同步模式：Synchronous Mode邻道功率：ACP D―― Adjacent Channel Power先进移动电话业务：AMPS---Advanced Mobile Phone Service组织协会：ANSI --- American National Standard Institute 美国国家标准局BPT --- British Post and Telecommunication Standard 英国邮政与电信标准CCIR --- International Radio Consultative Committee 国际无线电咨询委员会CCITT --- International Telegraph and Telephone Consultative Committee国际/电报咨询委员会CEPT --- Conference of European Post and Telecommunication Administrations欧洲邮电行政会议EIA --- Electronic Engineers Association 电子工业协会美ETSI --- European Telecommunication Standards Institute欧洲电信标准委员会FCC --- Federal Communications Commission联邦通信委员会美IEC --- International Electrotechnics Committee国际电工委员会IEE --- Institution of Electrical Engineers电气工程师协会英IEEE--- Institution of Electrical and Electronics Engineers, INC电气与电子工程师协会美ITU --- International Telecommunication Union 国际电信联盟联合国MPT --- Ministry of Post and telecommunications邮政与电信部英TIA --- Telecommunications Industries Association电信工业协会美WARC --- World Administrative Radio Conference世界无线电行政大会ZVEI --- Zentralverband der Electechnischen Industrie电气工业中央协会德ACP --- Adjacent Channel Power邻道功率AMPS --- Advanced Mobile Phone Institute先进移动电话业务APOC --- Advanced Paging Operator Code先进寻呼操作码AVL --- Average Voice Level平均话音电平BSC --- Base Site Controller基站控制器CDMA --- Code Division Mulitiple Code码分多址CDPD --- Cellular Digital Packet Data蜂窝分组数据系统CSC --- Cell Site Controllor小区控制器DCCH --- Digital Control Channel数字控制信道DECT --- Digital Enhanced Cordless Telecommunications数字增强无绳电话EDACS --- Enhanced Digital Access Communications System加强的数字接入通信系统ERMES --- European Telecommunications Standards Institute欧洲无线电信息系统ESN --- Electronics Serial Number电子串号FDR --- Frequency Domain Reflectometry频域反射计FLEX --- Flexible Paging System可变速寻呼系统FOCC --- Forward Control Channel前向控制信道FVC --- Forward Voice Channel前向话音信道GSC --- Golay Sequential Coding格雷码GSM --- Global System for Mobile Communications全球移动通信系统IBASIC --- Instrument BASIC仪器BASIC语言IDC --- Instantaneous Deviation Control瞬时频偏控制IMSI --- International Mobile Station Identify国际移动台识别号码LNA --- Low Noise Amplifier低噪声放大器LPF/HPF --- Low/High Pass Filter低通/高通滤波器LSB/USB --- Lower/Upper Side Band下/上边带MCC --- Mobile Country Code移动业务国家号码MCS --- Mobile Control Station移动控制站MIN --- Mobile Identification Number移动识别码MNC --- Mobile Network Code移动电话网号码MSC ---Mobile Switching Center移动交换中心MSIN --- Mobile Station Identification Number移动台识别码MTSO --- Mobile Telephone Switching Office移动电话交换局NMSI --- National Mobile Station Identify国内移动台识别号码NMT --- Nordic Mobile Telephone北欧移动电话系统OTP --- One Time Programmable一次性编程PDC --- Personal Digital Cellular个人数字蜂窝系统PHS --- Personal Handy-Phone System个人手持电话系统PSTN --- Public Switching Telephone Network公用交换电话网RECC --- Reverse Control Channel反向控制信道RVC --- Reverse Voice Channel反向话音信道RSSI --- Receiced Signal Strength Indicator接收信号场强指示SCC --- Signalling Channel Controller信令信道控制器SCM --- Station Class Mark移动台级别标志SID --- Syste Indentification Number系统识别号TACS --- Total Access Communications System全选址通信系统TDMA --- Time Division Multiple Access时分多址UUT --- Under Unit Test被测单元VCC --- Voice Channel Controller话音信道控制器VSWR --- Voltages Standing Wave Ratio电压驻波比1997年，爱立信公司向ETSI（欧洲电信标准委员会）提出了EDGE的可行性研究方案，并在同年得到认可。

科技英语翻译联系200句1.To transmit electromagnetic waves takes energy.传送电磁波需要能量2.Chemical control will do most of things in pest control.化学防治能在病虫害防治中起主要作用。

3.It is not until wires are connected that the path is completed.直到导线接上以后，此电路才接通。

4.The odds are heavily against any man being able to do the work in the field of abstract theory that Einstein is doing.对任何能从事爱因斯坦正在进行的抽象理论研究的人来说，条件都是极为不利的。

5.Oscillator design is of an art rather than an exact science.与其说振荡器的设计是一门严谨的科学，不如说它是一门艺术。

6.A rapid decrease by a factor of 7 was observed.发现迅速减少到（了）1/7。

7.Birds and animals which hunt at night have eyes which contain few or no cones at all,so they cannot see colors.凡是夜间觅食的飞禽走兽，因为眼睛中的视维细胞数量极少或根本没有，所以不能辨别颜色。

8.Tsunami is sometimes powerful enough to destroy a coastwise building it strikes.海啸有时威力很大，足可摧毁它所冲击的沿岸的建筑物。

9.Not everybody is convinced the Leaning Tower of Pisa really can be saved.并非每个人都相信比萨斜塔真的能免于坍塌。

计算机网络(第四版) 习题答案第1 章概述1-3 The performance of a client-server system is influenced by two network factors: the bandwidth of the network (how many bits/sec it can transport) and the latency (how many seconds it takes for the first bit to get from the client to the server). Give an example of a network that exhibits high bandwidth and high latency. Then give an example of one with low bandwidth and low latency.客户-服务器系统的性能会受到两个网络因素的影响：网络的带宽（每秒可以传输多少位数据）和延迟（将第一个数据位从客户端传送到服务器端需要多少秒时间）。

请给出一个网络的例子，它具有高带宽和高延迟。

然后再给出另一个网络的例子，它具有低带宽和低延迟。

答：横贯大陆的光纤连接可以有很多千兆位/秒带宽，但是由于光速度传送要越过数千公里，时延将也高。

相反，使用56 kbps调制解调器呼叫在同一大楼内的计算机则有低带宽和较低的时延。

1-4 Besides bandwidth and latency, what other parameter is needed to give a good characterization of the quality of service offered by a network used for digitized voice traffic?除了带宽和延迟以外，针对数字化的语音流量，想要让网络提供很好的服务质量，还需要哪个参数？声音的传输需要相应的固定时间，因此网络时隙数量是很重要的。