SV2805
4-Channel Video Decoders and Audio Codecs.
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strictly prohibited except by written permission on of SEVIC ?
This is draft information on a new production or undergoing evaluation. Details are subject change without notice. DATA SHEET
Version 1.1
Dated : 2009-06-01
Table Of Contents
1. OVERVIEW (3)
1.1Features (3)
1.2Block Diagram (5)
2. Pin information (6)
2.1SV2805 Pin Diagram (6)
2.2SV2805 100-pin TQFP Package Pin Description (7)
3.FUNCTIONAL DESCRIPTION (9)
3.1Video Decoder (9)
3.1.1Analog-to-Digital Converter (9)
3.1.2Video Standard Detect (10)
3.1.3Video Active Region Control (11)
3.1.4Blue Screen (11)
3.1.5Chroma Kill (11)
3.1.6Software Reset (12)
3.1.7Color Transient Improvement (CTI) (12)
3.1.8Sharpness (12)
3.1.9Chrominance Gain, Offset and Hue Adjustment (13)
3.2Video Output Format (14)
3.2.1ITU-R BT.656 Format (14)
3.2.2Two Channel D1 ITU-R BT.656 Time-multiplexed Format with 54MHz (15)
3.2.3Four Channel D1 BT.656 Time-multiplexed Format with 108MHz (15)
3.2.4Four Channel CIF Time-multiplexed Format with 54MHz (17)
3.3Audio Codec (18)
3.3.1Audio Detection (18)
3.3.2Multi-Chip Operation (19)
3.3.3Serial Audio Interface (21)
3.3.4Playback Input (21)
3.3.5Record Output (22)
3.3.6Mix output (23)
3.4System Clocks (24)
3.5I2C-bus interface (25)
3.6Interrupt Interface (26)
3.7Register Map (27)
3.7.1Register Summary (28)
3.7.2Sharpness, CTI processor (32)
S E V I C C o n f i d e n t i a l1N o D i s c l o s u r e
3.7.3TV-Decoder control registers description (44)
3.7.4MISC. control registers description (53)
4. recommended value (59)
5. ELECTRICAL SPECIFICATION (60)
5.1Absolute Maximum Ratings (60)
5.2AC/DC Characteristics (61)
6. APPLICATION CIRCUIT (68)
7. Package dimension (69)
8. Revision history (72)
S E V I C C o n f i d e n t i a l2N o D i s c l o s u r e
S E V I C C o n f i d e n t i a l 3 N o D i s c l o s u r e
1. OVERVIEW
SV2805 includes 4 Channel Video Decoder and 4 Channel Audio Codec.
4 Channel Video Decoder delivers high quality images. It accepts separate 4 CVBS inputs from Camera, TV, VCR and the other video signal sources. It digitizes and decodes NTSC/PAL video signal into digital components video which represents 8-bit CCIR656 4:2:2 format with 27Mhz, 54MHz and 108Mhz multiplexed.
4 Channel Audio Codec has four ADC and one DAC. Built-in voice controller can generate digital outputs for recording/mixing and accepts digital input for playback.
1.1 F e a t u r e s
Video Decoders
High performance adaptive 4H comb filters for all NTSC/PAL standards Integrated four video analog anti-aliasing filters and 10 bit CMOS ADCs.
Supports the standard ITU-R BT.656 format or time multiplexed output with 27/54/108MHz Provides simultaneous four channel Full D1 and CIF time-multiplexed outputs with 54MHz On Chip Analog DC-restore/AGC and Anti-aliasing Filter.
Supports NTSC – M/J/4.43, PAL – I/B/G/H/D/N/M/60 standards. Automatic white peak control and peak AGC Color Transient Improvement (CTI)
Programmable hue, saturation, contrast, brightness
Sharpness for luminance.
Audio Codec
Integrated 4 CH audio input and one audio DAC Provides multi-channel audio mixed analog output
Supports a standard I2S interface for record output and playback input I2S/DSP Interface (Master/Slave mode) Linear PCM (8/16 bit, 8/16KHz) Input/Output analog gain control
Cascade mode (up to 4 cascade support)
Mute Detection.
S E V I C C o n f i d e n t i a l 4 N o D i s c l o s u r e
Miscellaneous
Supports a I2C-bus serial interface
Internal PLL for audio record and playback. 3.3V , 1.8V power
100-pin TQFP package.
Applications
Video Security System
S E V I C C
o n f
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5
N o D i s c l o s u r e
1.2 B l o
c k D i
a g r a m
Fig. 1 SV2805 Block Diagram
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6
N o D i s c l o s u r e
2. PIN INFORMATION
2.1S V2805P i n D i a g r a m
S E V I C C o n f i d e n t i a l 7 N o D i s c l o s u r e
2.2 S V 2805 100-p i n T Q F P P a c k a g e P i n D e s c r i p t i o n
I = Digital Input; O = Digital Output; IO = Digital input/output AI = Analog Input; AO = Analog Output P = Power; G = Ground
Video Interface
Pin name Number
Type Description
VIN1 88 AI Composite Video input of channel 1. VIN2 91 AI Composite Video input of channel 2. VIN3 94 AI Composite Video input of channel 3. VIN4 97
AI Composite Video input of channel 4. VD1[7:0] 53, 55, 56, 58, 59, 61, 62, 64 O Video data output of channel 1. VD2[7:0] 39, 41, 42, 43, 45, 46, 48, 49 O Video data output of channel 2. VD3[7:4] VD_33 VD[2:0] 21, 23, 24, 27
28, 30, 31, 33 O Video data output of channel 3. VD4[7:0]
8, 9, 11, 12, 14, 15, 17, 18
O
Video data output of channel 4.
Audio Interface
Pin name Number (sv2805)
Type Description
AIN1 85 AI Audio input of channel 1. AIN2 82 AI Audio input of channel 2. AIN3 83 AI Audio input of channel 3. AIN4 84 AI Audio input of channel 4. AOUT 79 AO Audio mixing output.
ACLKR 65 IO Audio serial clock input/output of record. ASYNR 67 IO Audio serial sync input/output of record. ADATR 68 O Audio serial data output of record. ADATM 70 O Audio serial data output of mixing.
ACLKP 71 IO Audio serial clock input/output of playback. ASYNP 73 IO Audio serial sync input/output of playback. ADATP
74 I Audio serial data input of playback.
S E V I C C o n f i d e n t i a l 8 N o D i s c l o s u r e
Host Interface / clock / MPPx
Pin name Number (sv2805)
Type Description
CLK54I 37 I 54MHz system clock input. CLKPO 34 O 27/54/108MHz clock output. CLKNO 35 O 27/54/108Mhz clock output.
MPP1 52 O HS/VS/FLD/ACTIVE/NOVID of channel 1. MPP2 38 O HS/VS/FLD/ACTIVE/NOVID of channel 2. MPP3 20 O HS/VS/FLD/ACTIVE/NOVID of channel 3. MPP4 6 O HS/VS/FLD/ACTIVE/NOVID of channel 4. IRQO 5 O Interrupt request output. RSTB 100 I System reset. (low active)
TEST 99 I Test input pin. Connect to ground. SCLK 2 I I2C interface clock. (5V tolerant) SDAT 3 IO I2C interface data. (5V tolerant) SADD[1:0]
76, 77
I
I2C interface address select.
Power / Ground
Pin name Number (sv2805) Type Description VSS 1, 7, 13, 19, 25, 29, 32, 44, 47, 51, 57, 63
69, 75,
G Digital ground.
VDD 4, 16, 26, 36, 50, 60 72,
P 1.8V Power for internal logic. VD33 10, 22, 40, 54, 66, P 3.3V Digital power for digital I/O port VDDA 78, P 3.3V Power for audio DAC. AGND 80, 81, G Analog ground.
VDDA_A 86,
P 3.3V Analog power for audio ADC. VDDA_V 87, 92, 93, 98 P 3.3V Analog power for video ADC. AGND_V
89, 90, 95, 96,
G
Ground for analog video.
S E V I C C o n f i d e n t i a l 9 N o D i s c l o s u
r e
3. FUNCTIONAL DESCRIPTION
3.1 V i d e o D e c o d e r
SV2805 built in 4 channel 2D Video Decoder with three 4 channel 10-bit ADC. The input video signal can be NTSC or PAL format. The non-decoded signal goes to a programmable 2D comb filter to separate the luminance(Y) and chrominance(C) form CVBS. The YC signal is then demodulated to YCbCr format.
The video decoder can automatically detect the TV signal format (NTSC, PAL) and provide the signal lock/unlock status.
3.1.2 Video Standard Detect
The SV2805 supports all NTSC/PAL standard formats and has built-in automatic standard detection circuit. The following Table 3.1.2 shows the identified standards. Automatic standard detection can be overridden by writing the value into the “det_mode”and “video_format” register. Even in no-video status, the device can be forced to free-run in a particular video standard mode for fast locking by programming “video_format” register.
Table 3.1.2 Input video format support
Format Line/Fv(Hz) Fh (KHz) Fsc (MHz)
NTSC-M*
NTSC-J 525/59.94 15.734 3.579545
NTSC-4.43* 525/59.94 15.734 4.43361875
PAL-IBGHD
PAL-N* 625/50 15.625 4.43361875
PAL-M* 525/59.94 15.734 3.57561149
PAL-CN 625/50 15.625 3.58205625
PAL-60 525/59.94 15.734 4.43361875
Note : * 7.5 IRE Setup
3.1.3
Video Active Region Control
The active video region is determined by havtive_start , hactive_width , vactive_start and vactive_height register as illustrated in Fig 3.1.3. The first active line is defined by the vactive_start register and the first active pixel is defined by the hactive_start register. The vactive_height register can be programmed to define the number of active lines in a video field, and the hactive_width register can be programmed to define the number of active pixels in a video line.
Fig 3.1.3 The effect of video active region registers
3.1.4
Blue Screen
When none of the video input is detected or the video input is too week to be synchronized, the vedeo decoder will
automatically send out the Blue Screen video pattern. The color of Blue Screen is programmable. User can change the he default “Blue Screen” color by setting “blue_screen_y”, “blue_screen_cb” and “blue_screen_cr” registers.
3.1.5
Chroma Kill
When the color component of input video is unstable or too weak, Chroma Killer will automatically filter out the chroma signal and keep display the luma signal.
3.1.6
Software Reset
After power-up or after a hardware reset, TV-decoder will remain in a reset state until a “0” is written to register “0x3F”.
Writing a “1” to “0x3F” will perform a software reset. Note that a software reset affects all TV-decoder modules except for the register interface and the registers themselves. Only a hardware reset can restore the register module’s defaults.
3.1.7
Color Transient Improvement (CTI)
The color transient improvement engine is made to recover this imperfectness of video presentation and adaptively sharpen the transition of chrominance edges to produce clearer video to the viewers.
Fig 3.1.7
CTI Transform function
3.1.8
Sharpness
The sharpness of a picture can be increased by increasing the amplitude of high frequency luminance information. A coring circuit is typically used to remove low-level noise. The modified luminance is then added to the original luminance signal.
Fig 3.1.8 Sharpness Control Block Diagram
3.1.9 Chrominance Gain, Offset and Hue Adjustment
The color saturation can be adjusted by changing the Saturation register. The Cb and Cr gain can be also adjusted independently by programming U_GAIN and V_GAIN register. Likewise, the Cb and Cr offset can be programmed through U_OFF and V_OFF registers. Hue control is achieved with phase shift of the digitally controlled oscillator. The phase shift can be programmed through Hue register.
3.2V i d e o O u t p u t F o r m a t
3.2.1 ITU-R BT.656 Format
In ITU-R BT.656 format, SAV and EAV sequences are inserted into the data stream to indicate the active video time. It is noted that the number of active pixels per line is constant in this mode regardless of the actual incoming line length. The output timing is illustrated in Fig 3.2.1. The SAV and EAV sequences are shown in Table 3.2.1. An optional set of ITU-R BT.656 SAV/EAV code sequence can be enabled to identify no-video status using the NOVID_656 bit.
3.2.2
Two Channel D1 ITU-R BT.656 Time-multiplexed Format with 54MHz
The SV2805 supports two channel ITU-R BT.656 time-multiplexed format with 54MHz that is useful to security application requiring two channel outputs through one channel video port. When the CH_MODE register is 1 enables the dual ITU-R BT.656 time-multiplexed format and the MAIN_CH and SEC_CH register selects two channels to be output multiplexed on each VD pins. To de-multiplex the time-multiplexed data in the back end chip, the channel ID can be inserted in the data stream using the CHID_MD register. Two kinds of channel ID format can be supported. One is horizontal blanking code with channel ID and the other is ITU-R BT.656 sync code with channel ID. The following Fig 3.2.2 illustrates the timing diagram in the case of CH1 and CH2 time-multiplexed output through CH1 video output port.
Fig 3.2.2 Timing Diagram of Two Channel Time-multiplexed Format with 54MHz
3.2.3
Four Channel D1 BT.656 Time-multiplexed Format with 108MHz
Four channel of D1 (720x480) at 27MHz video stream that are time-division-multiplexed at 108MHz data rate format is implemented in SV2805 for security surveillance application.
In order to reduce pin counts (thus shrink chip size) on both decoder’s digital output port and the input port of the back end compression Codec devices, SV2805 implements single 8 bit bus at 4 times the base band pixel clock rate of 27MHz. While quadrupling the data rate on a single bus to meet the new requirement, individually, each channel data arrangement still retains the base band 27MHz BT.656 specification. Embedded timing (SAV-EAV) code and Channel ID are inserted into each channel for de-multiplexing and separation of channel data.
Fig 3.2.3 Timing Diagram of 108MHz 4 CH D1 Time-Multiplexed Video data
Condition 656 FVH Value SAV/EAV Code Sequence
Fourth
Field V time H time F V H First Second Third
CH1 CH2 CH3 CH4 EVEN Blank EAV 1 1 1 0xFF 0x00 0x00 0xF0 0xF1 0xF2 0xF3 EVEN Blank SAV 1 1 0 0xFF 0x00 0x00 0xE0 0xE1 0xE2 0xE3 EVEN Active EAV 1 0 1 0xFF 0x00 0x00 0xD0 0xD1 0xD2 0xD3 EVEN Active SAV 1 0 0 0xFF 0x00 0x00 0xC0 0xC1 0xC2 0xC3 ODD Blank EAV 0 1 1 0xFF 0x00 0x00 0xB0 0xB1 0xB2 0xB3 ODD Blank SAV 0 1 0 0xFF 0x00 0x00 0xA0 0xA1 0xA2 0xA3 ODD Active EAV 0 0 1 0xFF 0x00 0x00 0x90 0x91 0x92 0x93 ODD Active SAV 0 0 0 0xFF 0x00 0x00 0x80 0x81 0x82 0x83
H Blanking Code with Channel ID
Channel
Y Cb Cr CH1 0x10 0x80 0x80
CH2 0x11 0x81 0x81
CH3 0x12 0x82 0x82
CH4 0x13 0x83 0x83
3.2.4 Four Channel CIF Time-multiplexed Format with 54MHz
Four channel CIF (360x480) time-multiplexed format is also provided for specific security application, when the
CH_MODE register is setting to 3. For this format, each channel ITU-R BT.656 data stream is down-sampled into 13.5MHz ITU-R BT.656 data stream except the sync code. Optionally, the half vertical size can also be enabled to support Quad (360x240) format using the VSCL_EN register. These four 13.5MHz ITU-R BT.656 data stream are time-multiplexed into 54MHz data stream. This format requires only one channel video port to transfer whole four channel CIF data independently so that it can be supported simultaneously with two channel Full D1 ITU-R BT.656 time-multiplexed format through the other video ports. To de-multiplex the time-multiplexed data in the back end chip, the channel ID can be inserted in the data stream using the CHID_MD register. Two kinds of channel ID format can be supported. One is horizontal blanking code with channel ID and the other is ITU-R BT.656 sync code with channel ID. Optionally, when the half vertical size is enabled, the ITU-R BT.656 sync code will be skipped in the invalid line through the VSCL_SYNC register. The following Fig 3.2.4 and Table3.2.4 illustrate the timing diagram and detailed channel ID format for four channel CIF time-multiplexed format with 54MHz.
Fig 3.2.4 Timing Diagram of 4 Ch CIF Time-multiplexed Format with 54MHz
3.3A u d i o C o d e c
The audio codec is composed of 4 audio Analog-to-Digital converters, 1 Digital-to-Analog converter, audio mixer, digital serial audio interface and audio detector shown as the Fig 3.3. SV2805 can accept 4 analog audio signals and 1 digital serial audio data and 1 mixing analog audio signal output and 2 digital serial audio data.
Fig 3.3 Block Diagram of Audio Codec
The digital serial audio input data through the ACLKP, ASYNP and ADATP pin are used for playback function. To record audio data, the SV2805 provides the digital serial audio output via the ACLKR, ASYNR and ADATR pin.
The level of analog audio input signal AIN1, AIN2, AIN3 and AIN4 can be adjusted respectively by internal programmable gain amplifiers that are defined by the AI_GAIN1, AI_GAIN2, AI_GAIN3 and AI_GAIN4 registers. For voice codec, 8KHz or
16KHz sampling frequency is used. The level of analog audio output signal AOUT can also be adjusted by internal programmable gain control register AO_GAIN.
The audio codec can mix all of audio inputs including analog audio signal and digital audio data according to the predefined mixing ratio for each audio via the MIX_RATIO1 ~ MIX_RATIO4 and MIX_RATIOP registers. This mixing audio output can be provided through the analog and digital interfaces. The embedded audio Digital-to-Analog converter supports the analog mixing audio output whose level can be controlled by programmable gain amplifier via the AO_GAIN register. The ADATM pin supports the digital mixing audio output and its digital serial audio timings are provided through the ACLKR and ASYNR pins that are shared with the digital serial audio record timing pins.
3.3.1 Audio Detection
The SV2805 has an audio detector for individual 4 channels. There are 2 kinds of audio detection method defined by the ADET_MTH. One is the detection of absolute amplitude and the other is of differential amplitude. For both detection methods, the accumulating period is defined by the ADET_PR1 ~ ADET_PR4 registers and the detecting threshold value is defined by the ADET_TH1 ~ ADET_TH4 registers. The status for audio detection is read by the AVDET_STATE register and it also makes the interrupt request through the IRQ pin with the combination of the status for video loss detection.
3.3.2
Multi-Chip Operation
SV2805 can output 16 channel audio data on ACLKR/ASYNR/ADATR output simultaneously. Therefore, up to 4 chips should be connected on most Multi-Chip application cases. The Fig 3.3.2 shows the example of 16 channel audio connection using 4 chips. Each stage should be defined by the CHIP_STAGE as the following Table 3.3.2.
CHIP_STAGE
Operation Stage 0 First Stage 1 Middle Stage 2 Muti Chip Last Stage
3
Single Chip
-
Table 3.3.2 Definition of Stage for Multi-chip Connection
Each stage chip can accept 4 analog audio signals so that four cascaded chips through the ADATP and ADATR pin will be 16 channel audio controller. The first stage chip provides 16ch digital serial audio data for record. Even though the first stage chip has only 1 digital serial audio data pin ADATR for record, the SV2805 can generate 16 channel data simultaneously using multi-channel method. Also, each stage chip can support 4 channel record outputs that are corresponding with analog audio inputs. This first stage chip can also output 16 channel mixing audio data by the digital serial audio data and analog audio signal. The last stage chip accepts the digital serial audio data for playback. The digital playback data can be converted to analog signal by Digital-to-Analog Converter in the last stage chip.