SNUG-2008 Boston, MA Voted Best Paper 1st Place
World Class Verilog & SystemVerilog Training
Clock Domain Crossing (CDC) Design & Verification Techniques Using SystemVerilog
Clifford E. Cummings
Sunburst Design, Inc. cliffc@https://www.doczj.com/doc/d318054849.html,
ABSTRACT Important design considerations require that multi-clock designs be carefully constructed at Clock Domain Crossing (CDC) boundaries. This paper details some of the latest strategies and best known methods to address passing of one and multiple signals across a CDC boundary. Included in the paper are techniques related to CDC verification and an interesting 2-deep FIFO design for passing multiple control signals between clock domains. Although the design methods described in the paper can be generally implemented using any HDL, the examples are shown using efficient SystemVerilog techniques.
Table of Contents
1.0 2.0 2.1 3.0 3.1 3.2 3.3 3.4 3.5 3.6 4.0 4.1 4.1.1 4.2 4.3 4.4 4.5 5.0 5.1 5.2 5.3 5.3.1 5.4 5.4.1 5.5 5.5.1 5.6 5.6.1 5.6.2 5.6.3 5.7 5.7.1 5.7.2 5.7.3 5.7.4 5.7.5 5.7.6 5.8 5.8.1 5.8.2 6.0 6.1 Introduction........................................................................................................................... 6 Metastability.......................................................................................................................... 6 Why is metastability a problem?........................................................................................... 7 Synchronizers........................................................................................................................ 8 Two synchronization scenarios ............................................................................................. 8 Two flip-flop synchronizer ................................................................................................... 8 MTBF - mean time before failure ......................................................................................... 9 Three flip-flop synchronizer ............................................................................................... 10 Synchronizing signals from the sending clock domain....................................................... 10 Synchronizing signals into the receiving clock domain...................................................... 11 Synchronizing fast signals into slow clock domains .......................................................... 13 Requirement for reliable signal passing between clock domains ....................................... 13 The "three edge" requirement .......................................................................................... 13 Problem - passing a fast CDC pulse ................................................................................... 14 Problem - sampling a long CDC pulse - but not long enough!........................................... 15 Open-loop solution - sampling signals with synchronizers ................................................ 16 Closed loop solution - sampling signals with synchronizers .............................................. 17 Passing multiple signals between clock domains ............................................................... 18 Multi-bit CDC strategies..................................................................................................... 18 Multi-bit signal consolidation ............................................................................................. 18 Problem - Two simultaneously required control signals..................................................... 19 Solution - Consolidation.................................................................................................. 20 Problem - Two phase-shifted sequencing control signals................................................... 21 Solution - consolidation and an extra flip-flop................................................................ 22 Problem - Multiple CDC signals......................................................................................... 23 Solutions for passing multiple CDC signals.................................................................... 23 Multi-Cycle Path (MCP) formulation ................................................................................. 24 MCP formulation using a synchronized enable pulse ..................................................... 25 Closed-loop - MCP formulation with feedback .............................................................. 27 Closed-loop - MCP formulation with acknowledge feedback ........................................ 28 Synchronizing counters....................................................................................................... 29 Binary counters ................................................................................................................ 29 Gray codes ....................................................................................................................... 30 Gray-to-binary conversion ............................................................................................... 30 Binary-to-gray conversion ............................................................................................... 31 Gray code counter style #1 .............................................................................................. 32 Gray code counter style #2 .............................................................................................. 33 Additional multi-bit CDC techniques ................................................................................. 34 Multi-bit CDC signal passing using asynchronous FIFOS.............................................. 34 Multi-bit CDC signal passing using 1-deep / 2-register FIFO synchronizer ................... 35 Naming conventions & design partitioning ........................................................................ 36 Clock & signal naming conventions ................................................................................... 36
2 Clock Domain Crossing (CDC) Design & Verification Techniques Using SystemVerilog
SNUG Boston 2008 Rev 1.0
6.1.1 6.2 6.3 6.3.1 6.4 7.0 7.1 7.2 7.2.1 7.2.2 7.2.3 7.2.4 7.3 7.3.1 7.3.2 7.3.3 7.4 7.5 7.6 7.7 8.0 8.1 8.2 8.3 8.4 9.0 10.0 11.0 12.0 12.1 12.2 12.3
Multi-clock / multi-source modules with no naming convention................................... 37 Timing verification for each clock domain......................................................................... 37 Clock oriented design partitioning...................................................................................... 37 Timing analysis of clock-partitioned modules................................................................. 39 Partitioning with MCP formulations................................................................................... 40 Multi-clock gate-level simulation issues ............................................................................ 41 Synchronizer gate-level CDC simulation issue .................................................................. 41 Strategies to remove X-propagation from gate-level simulations....................................... 41 Simulator command to turn off timing checks ................................................................ 42 Change flip-flop setup and hold times to 0...................................................................... 42 Copy and modify new flip-flop models ........................................................................... 42 Synopsys set_annotated_check command ....................................................................... 42 Additional strategies to remove X-propagation .................................................................. 43 Use multiple SDF files .................................................................................................... 43 Vendor synchronizer cell with supporting SDF generation tools.................................... 43 Vendors with built-in synchronizer support .................................................................... 44 Multiple SDF files for gate-level CDC simulations ........................................................... 44 Force synchronizer notifier inputs to a fixed value............................................................. 44 ASIC & FPGA library cell synchronizers........................................................................... 45 Simulation model with random delay insertion .................................................................. 46 Summary & conclusions ..................................................................................................... 47 Recommended 1-bit CDC techniques................................................................................. 47 Recommended multi-bit CDC techniques .......................................................................... 48 Recommended naming conventions and design partitioning ............................................. 48 Recommended solutions to multi-clock gate-level CDC simulations ................................ 48 Acknowledgements............................................................................................................. 48 References........................................................................................................................... 48 Author & Contact Information............................................................................................ 49 Appendix............................................................................................................................. 50 Common sync2 model - used by MCP formulation and FIFO synchronizer...................... 50 MCP formulation with ready-acknowledge source code .................................................... 50 Multi-bit 1-deep / 2-register FIFO synchronizer source code............................................. 55
SNUG Boston 2008 Rev 1.0
3
Clock Domain Crossing (CDC) Design & Verification Techniques Using SystemVerilog
Table of Figures
Figure 1 - Asynchronous clocks and synchronization failure ......................................................... 6 Figure 2 - Metastable bdat1 output propagating invalid data throughout the design................... 7 Figure 3 - Two flip-flop synchronizer............................................................................................. 9 Figure 4 - Primary contributing factors to short MTBF values..................................................... 10 Figure 5 - Three flip-flop synchronizer used in higher speed designs .......................................... 10 Figure 6 - Unregistered signals sent across a CDC boundary....................................................... 11 Figure 7 - Registered signals sent across a CDC boundary .......................................................... 12 Figure 8 - Short CDC signal pulse missed during synchronization .............................................. 14 Figure 9 - Marginal CDC pulse that violates the destination setup and hold times...................... 15 Figure 10 - Lengthened pulse to guarantee that the control signal will be sampled ..................... 16 Figure 11 - Signal with feedback to acknowledge receipt ............................................................ 17 Figure 12 - Problem - Passing multiple control signals between clock domains.......................... 19 Figure 13 - Solution - Consolidating control signals before passing between clock domains ..... 20 Figure 14 - Problem - Passing sequential control signals between clock domains....................... 21 Figure 15 - Solution - Logic to generate proper sequencing signals in the new clock domains ... 22 Figure 16 - Problem - Encoded control signals passed between clock domains .......................... 23 Figure 17 - Logic to pass a synchronized enable pulse between clock domains .......................... 24 Figure 18 - Synchronized pulse generation logic.......................................................................... 25 Figure 19 - Synchronized enable pulse generation logic and equivalent symbol ......................... 26 Figure 20 - Multi-Cycle Path (MCP ) formulation toggle-pulse generation................................. 26 Figure 21 - Multi-Cycle Path (MCP ) formulation toggle-pulse generation with acknowledge... 27 Figure 22 - Multi-Cycle Path (MCP ) formulation toggle-pulse generation with ready-ack ........ 28 Figure 23 - Binary count values sampled in mid-transition .......................................................... 29 Figure 24 - 4-bit gray-to-binary conversion equations.................................................................. 30 Figure 25 - 4-bit gray-to-binary conversion equations - 2nd method ........................................... 31 Figure 26 - 4-bit binary-to-gray conversion equations.................................................................. 31 Figure 27 - Gray code counter style #1 - only one gray code register........................................... 32 Figure 28 - Gray code counter style #2 - binary register and gray code register........................... 33 Figure 29 - 1-deep / 2-register FIFO synchronizer block diagram................................................ 35 Figure 30 - Design partitioned on clock boundaries ..................................................................... 38 Figure 31 - Partitioned design with MCP formulation ................................................................. 40 Figure 32 - Synchronizer gate-level CDC simulation waveforms ................................................ 41 Figure 33 - Sample ASIC & FPGA synchronizer cell for synthesis and simulation .................... 46
SNUG Boston 2008 Rev 1.0
4
Clock Domain Crossing (CDC) Design & Verification Techniques Using SystemVerilog
Table of Examples
Example 1 - Non-working but conceptually correct gray-to-binary SystemVerilog model ......... 30 Example 2 - Parameterized and correct gray-to-binary SystemVerilog model............................. 31 Example 3 - Parameterized binary-to-gray SystemVerilog model................................................ 32 Example 5 - Parameterized gray-code counter SystemVerilog model.......................................... 33 Example 6 - Parameterized gray-code counter with binary counter ............................................. 34 Example 7 - SystemVerilog model for ASIC & FPGA synchronizer cell.................................... 47 Example 8 - sync2.sv code............................................................................................................ 50 Example 9 - plsgen.sv code .......................................................................................................... 50 Example 10 - asend_fsm.sv code.................................................................................................. 51 Example 11 - back_fsm.sv code ................................................................................................... 51 Example 12 - bmcp_recv.sv code ................................................................................................. 52 Example 13 - mcp_blk.sv code..................................................................................................... 53 Example 14 - acmp_send.sv code................................................................................................. 54 Example 15 - wctl.sv code ............................................................................................................ 55 Example 16 - cdc_syncfifo.sv code .............................................................................................. 55 Example 17 - Dual Port Ram code - dp_ram2.sv ......................................................................... 56 Example 18 - rctl.sv code.............................................................................................................. 56
SNUG Boston 2008 Rev 1.0
5
Clock Domain Crossing (CDC) Design & Verification Techniques Using SystemVerilog
1.0 Introduction
In 2001, I presented my first paper on multi-asynchronous clock design. At that time, I had not found any good sources to describe the design and synthesis techniques required to do proper multi-clock design. The 2001 paper was a collection of techniques that I had gathered over years from actual ASIC and FPGA design experiences. At the conclusion of the 2001 conference presentation, dozens of engineers and colleagues came forward and shared with me enough additional interesting ideas and techniques to write a sequel on the topic. Over the past eight years, I have included instruction on multi-clock design techniques in my Advanced and Expert Verilog and SystemVerilog training courses, and over that same period of time, more colleagues and students have shared with me additional interesting multi-clock design techniques. Since the release of the first multi-clock paper in 2001, the industry has largely identified these types of design methodologies as Clock Domain Crossing (CDC) techniques. I will use this common nomenclature in this paper. This paper includes the best techniques described in the 2001 paper along with an updated collection of interesting and efficient multi-clock design techniques that have been shared with me over the past decade. The actual conference presentation slides will be mostly a collection of the new techniques incorporated since the original 2001 presentation, retaining only enough of the original slides to introduce the fundamental CDC design concepts and issues.
2.0 Metastability
Metastbility refers to signals that do not assume stable 0 or 1 states for some duration of time at some point during normal operation of a design. In a multi-clock design, metastability cannot be avoided but the detrimental effects of metastability can be neutralized.
Figure 1 - Asynchronous clocks and synchronization failure SNUG Boston 2008 Rev 1.0 6 Clock Domain Crossing (CDC) Design & Verification Techniques Using SystemVerilog
Quoting from Dally and Poulton's book[9] concerning metastability: "When sampling a changing data signal with a clock ... the order of the events determines the outcome. The smaller the time difference between the events, the longer it takes to determine which came first. When two events occur very close together, the decision process can take longer than the time allotted, and a synchronization failure occurs." Figure 1 shows a synchronization failure that occurs when a signal generated in one clock domain is sampled too close to the rising edge of a clock signal from a second clock domain. Synchronization failure is caused by an output going metastable and not converging to a legal stable state by the time the output must be sampled again. 2.1 Why is metastability a problem? So why is metastability a problem? Figure 2 shows that a metastable output that traverses additional logic in the receiving clock domain can cause illegal signal values to be propagated throughout the rest of the design. Since the CDC signal can fluctuate for some period of time, the input logic in the receiving clock domain might recognize the logic level of the fluctuating signal to be different values and hence propagate erroneous signals into the receiving clock domain.
Figure 2 - Metastable bdat1 output propagating invalid data throughout the design
Every flip-flop that is used in any design has a specified setup and hold time, or the time in which the data input is not legally permitted to change before and after a rising clock edge. This time
SNUG Boston 2008 Rev 1.0 7 Clock Domain Crossing (CDC) Design & Verification Techniques Using SystemVerilog
window is specified as a design parameter precisely to keep a data signal from changing too close to another synchronizing signal that could cause the output to go metastable.
3.0 Synchronizers
When passing signals between clock domains, an important question to ask is, do I need to sample every value of a signal that is passed from one clock domain to another? 3.1 Two synchronization scenarios There are two scenarios that are possible when passing signals across CDC boundaries, and it is important to determine which scenario applies to your design: (1) It is permitted to miss samples that are passed between clock domains. (2) Every signal passed between clock domains must be sampled. First scenario: sometimes it is not necessary to sample every value, but it is important that the sampled values are accurate. One example is the set of gray code counters used in a standard asynchronous FIFO design. In a properly designed asynchronous FIFO model, synchronized gray code counters do not need to capture every legal value from the opposite clock domain, but it is critical that sampled values be accurate to recognize when full and empty conditions have occurred. Second scenario: a CDC signal must be properly recognized or recognized and acknowledged before a change is permitted on the CDC signal. In both of these scenarios, the CDC signals will require some form of synchronization into the receiving clock domain. 3.2 Two flip-flop synchronizer Quoting again from Dally and Poulton[9] concerning synchronizers: "A synchronizer is a device that samples an asynchronous signal and outputs a version of the signal that has transitions synchronized to a local or sample clock." The simplest and most common synchronizer used by digital designers is a two-flip-flop synchronizer as shown in Figure 3. The first flip-flop samples the asynchronous input signal into the new clock domain and waits for a full clock cycle to permit any metastability on the stage-1 output signal to decay, then the stage1 signal is sampled by the same clock into a second stage flip-flop, with the intended goal that the stage-2 signal is now a stable and valid signal synchronized and ready for distribution within the new clock domain.
SNUG Boston 2008 Rev 1.0
8
Clock Domain Crossing (CDC) Design & Verification Techniques Using SystemVerilog
Figure 3 - Two flip-flop synchronizer
It is theoretically possible for the stage-1 signal to still be sufficiently metastable by the time the signal is clocked into the second stage to cause the stage-2 output signal to also go metastable. The calculation of the probability of the time between synchronization failures (MTBF) is a function of multiple variables including the clock frequencies used to generate the input signal and to clock the synchronizing flip-flops. One description of the MTBF calculation can be found in Dally and Poulton[9]. For most synchronization applications, the two flip-flop synchronizer is sufficient to remove all likely metastability. 3.3 MTBF - mean time before failure For most applications, it is important to run a calculation of the Mean Time Before Failure (MTBF) for any signal crossing a CDC boundary. Failure in this sense means a signal that is passed to a synchronizing flip-flop, goes metastable on the first stage synchronizer flip-flop, and continues to be metastable one cycle later when it is sampled into the second stage synchronizer flip-flop. Since the signal did not settle to a known value after one clock cycle, the signal could still be metastable when sampled and passed to the receiving clock domain, causing potential failures to the corresponding logic. When calculating MTBF numbers, larger numbers are preferred over smaller numbers. Larger MTBF numbers indicate longer periods of time between potential failures, while smaller MTBF
SNUG Boston 2008 Rev 1.0
9
Clock Domain Crossing (CDC) Design & Verification Techniques Using SystemVerilog
numbers indicate that metastability could happen frequently, similarly causing failures within the design. Dally and Poulton[9] give a good equation with very thorough analysis of the calculation that can be performed to calculate the MTBF of a synchronizer circuit. Without repeating the equation and analysis, it should be pointed out that two of the most important factors that directly impact the MTBF of a synchronizer circuit are, the sample clock frequency (how fast are signals being sampled into the receiving clock domain) and the data change frequency (how fast is the data changing that crosses the CDC boundary).
Figure 4 - Primary contributing factors to short MTBF values
From the above partial equation, it can be seen that failures occur more frequently (shorter MTBF) in higher speed designs, or when the sampled data changes more frequently. 3.4 Three flip-flop synchronizer For some very high speed designs, the MTBF of a two-flop synchronizer is too short and a third flop is added to increase the MTBF to a satisfactory duration of time. Of course, satisfactory is determined by the architect of the design.
Figure 5 - Three flip-flop synchronizer used in higher speed designs
3.5 Synchronizing signals from the sending clock domain Frequently asked question regarding CDC design: Is it a good idea to register signals from the sending clock domain before passing the signals to the receiving clock domain? Implied in the question is the assumption that CDC signals will be synchronized into the receiving clock domain; therefore, they do not require synchronization in the sending clock domain. This rationalization is incorrect and registering signals in the sending clock domain should generally be required.
SNUG Boston 2008 Rev 1.0
10
Clock Domain Crossing (CDC) Design & Verification Techniques Using SystemVerilog
Consider an example where the signals in the sending clock domain are not registered before being passed into the receiving clock domain, as shown in Figure 6.
Figure 6 - Unregistered signals sent across a CDC boundary
In this example, the combinational output from the sending clock domain could experience combinational settling at the CDC boundary. This combinational settling effectively increases the data-change frequency potentially creating small bursts of oscillating data and thereby increasing the number of edges that could be sampled while changing, with a corresponding increase in the potential for sampling changing data and generating metastable signals. 3.6 Synchronizing signals into the receiving clock domain Signals in the sending clock domain should be synchronized before being passed to a CDC boundary. The synchronization of signals from the sending clock domain reduces the number of edges that can be sampled in the receiving clock domain, effectively reducing the data-change frequency in the MTBF equation and hence increasing the time between calculated failures (see section 3.3 for a description of the impact of data change frequencies on MTBF).
SNUG Boston 2008 Rev 1.0
11
Clock Domain Crossing (CDC) Design & Verification Techniques Using SystemVerilog
Figure 7 - Registered signals sent across a CDC boundary
In Figure 7, the aclk logic settles and sets up on the adat flip-flop before being passed into the bclk domain. The adat flip-flop filters out the combinational settling on the flip-flop input (a) and passes a clean signal to the bclk logic.
SNUG Boston 2008 Rev 1.0
12
Clock Domain Crossing (CDC) Design & Verification Techniques Using SystemVerilog
4.0 Synchronizing fast signals into slow clock domains
As discussed in section 3.1, if a CDC signal cannot be skipped when passed between clock domains, it is important to consider signal widths or synchronization techniques when they are passed between clock domains. One issue associated with synchronizers is the possibility that a signal from a sending clock domain might change values twice before it can be sampled, or might be too close to the sampling edges of a slower clock domain. This possibility must be considered any time signals are sent from one clock domain to another and a determination must be made whether missed signals are or are not a problem for the design in question. When missed samples are not allowed, there are two general approaches to the problem: (1) An open-loop solution to ensure that signals are captured without acknowledgment. (2) A closed-loop solution that requires acknowledgement of receipt of the signal that crosses a CDC boundary. Both solutions are discussed in this section. 4.1 Requirement for reliable signal passing between clock domains Synchronizing slower control signals into a faster clock domain is generally not a problem if the faster clock domain is 1.5X the frequency (or more) of the slower clock domain, since the faster clock signal will sample the slower CDC signal one or more times. Recognizing that sampling slower signals into faster clock domains causes fewer potential problems than sampling faster signals into slower clock domains, a designer might to take advantage of this fact by using simple two flip-flop synchronizers to pass single CDC signals between clock domains. 4.1.1 The "three edge" requirement
Mark Litterick[4] noted that when passing one CDC signal between clock domains through a two-flip-flop synchronizer, the CDC signal must be wider than 1-1/2 times the cycle width of the receiving domain clock period. Littereick described this requirement as "input data values must be stable for three destination clock edges." For exceptionally long source and destination clock frequencies, this requirement could probably be safely relaxed to 1-1/4 times the cycle time of the receiving clock domain or less, but the "three edge" guideline is the safest initial design condition, and is easier to prove through the use of SystemVerilog assertions than to dynamically measure a fractional width of a CDC signal during simulation. The "three edge" requirement actually applies to both open-loop and closed-loop solutions, but implementations of the closed-loop solution automatically ensure that at least three edges are detected for all CDC signals.
SNUG Boston 2008 Rev 1.0
13
Clock Domain Crossing (CDC) Design & Verification Techniques Using SystemVerilog
4.2 Problem - passing a fast CDC pulse Consider the severely flawed condition where the sending clock domain has a higher frequency than the receiving clock domain and that a CDC pulse is only one cycle wide in the sending clock domain. If the CDC signal is only pulsed for one fast-clock cycle, the CDC signal could go high and low between the rising edges of a slower clock and not be captured into the slower clock domain as shown in Figure 8.
Figure 8 - Short CDC signal pulse missed during synchronization
SNUG Boston 2008 Rev 1.0
14
Clock Domain Crossing (CDC) Design & Verification Techniques Using SystemVerilog
4.3 Problem - sampling a long CDC pulse - but not long enough! Consider the somewhat non-intuitive and flawed condition where the sending clock domain sends a pulse to the receiving clock domain that is slightly wider than the period of the receiving clock frequency. Under most conditions, the signal will be sampled and passed, but there is the small but real chance that the CDC pulse will change too close to the two rising clock edges of the receiving clock domain and thereby violate the setup time on the first clock edge and violate the hold time of the second clock edge and not form the anticipated pulse. This possible failure is shown in Figure 9.
Figure 9 - Marginal CDC pulse that violates the destination setup and hold times
SNUG Boston 2008 Rev 1.0
15
Clock Domain Crossing (CDC) Design & Verification Techniques Using SystemVerilog
4.4 Open-loop solution - sampling signals with synchronizers One potential solution to this problem is to assert CDC signals for a period of time that exceeds the cycle time of the sampling clock as shown in Figure 10. As discussed in section 4.1.1, the minimum pulse width is 1.5X the period of the receiving clock frequency. The assumption is that the CDC signal will be sampled at least once and possibly twice by the receiver clock. Open-loop sampling can be used when relative clock frequencies are fixed and properly analyzed. Advantage: the Open-loop solution is the fastest way to pass signals across CDC boundaries that does not require acknowledgement of the received signal. Disadvantage: the largest potential problem related to an open-loop solution is that another engineer might mistake the solution for a general purpose solution, or the design requirements might change and an engineer might fail to re-analyze the original open loop solution. This problem can be minimized by adding a SystemVerilog Assertion to the model to detect if the input pulse ever fails to exceed the "three edges" design requirement.
Figure 10 - Lengthened pulse to guarantee that the control signal will be sampled
SNUG Boston 2008 Rev 1.0
16
Clock Domain Crossing (CDC) Design & Verification Techniques Using SystemVerilog
4.5 Closed loop solution - sampling signals with synchronizers A second potential solution to this problem is to send an enabling control signal, synchronize it into the new clock domain and then pass the synchronized signal back through another synchronizer to the sending clock domain as an acknowledge signal. Advantage: synchronizing a feedback signal is a very safe technique to acknowledge that the first control signal was recognized and sampled into the new clock domain. Disadvantage: there is potentially considerable delay associated with synchronizing control signals in both directions before allowing the control signal to change.
Figure 11 - Signal with feedback to acknowledge receipt
SNUG Boston 2008 Rev 1.0
17
Clock Domain Crossing (CDC) Design & Verification Techniques Using SystemVerilog
5.0 Passing multiple signals between clock domains
When passing multiple signals between clock domains, simple synchronizers do not guarantee safe delivery of the data. A frequent mistake made by engineers when working on multi-clock designs is passing multiple CDC bits required in the same transaction from one clock domain to another and overlooking the importance of the synchronized sampling of the CDC bits. The problem is that multiple signals that are synchronized to one clock will experience small data changing skews that can occasionally be sampled on different rising clock edges in a second clock domain. Even if we could perfectly control and match the trace lengths of the multiple signals, differences in rise and fall times as well as process variations across a die could introduce enough skew to cause sampling failures on otherwise carefully matched traces. Multi-bit CDC strategies must be employed to avoid skewed sampling of the multi-bit value. 5.1 Multi-bit CDC strategies To avoid multi-bit CDC skewed sampling scenarios, I have classified multi-bit CDC strategies into three main categories: (1) Multi-bit signal consolidation. Where possible, consolidate multiple CDC bits into 1bit CDC signals. (2) Multi-cycle path formulations. Use a synchronized load signal to safely pass multiple CDC bits. (3) Pass multiple CDC bits using gray codes. Each of these strategies is detailed in the remainder of this section. 5.2 Multi-bit signal consolidation Where possible, consolidate multiple CDC signals into a 1bit CDC signal. Ask yourself the question, do I really need multiple bits to control logic across a CDC boundary? Simply using synchronizers on all of the CDC bits is not always good enough as will be shown in the following examples. If the order or alignment of the control signals is significant, care must be taken to correctly pass the signals into the new clock domain. All of the examples shown in this section are overly simplistic but they closely mimic situations that often arise in real designs.
SNUG Boston 2008 Rev 1.0
18
Clock Domain Crossing (CDC) Design & Verification Techniques Using SystemVerilog
5.3 Problem - Two simultaneously required control signals. In the simple example shown in Figure 12, a register in the receiving clock domain requires both a load signal and an enable signal in order to load a data value into the register. If both the load and enable signals are driven on the same sending clock edge, there is a chance that a small skew between the control signals could cause the two signals to be synchronized into different clock cycles within the receiving clock domain. Under these conditions, the data would not be loaded into the register.
Figure 12 - Problem - Passing multiple control signals between clock domains
SNUG Boston 2008 Rev 1.0
19
Clock Domain Crossing (CDC) Design & Verification Techniques Using SystemVerilog
5.3.1
Solution - Consolidation
The solution to the problem in section 5.3 is simple, consolidate the control signals. As shown in Figure 13, drive both the load and enable register input signals in the receiving clock domain from just one load-enable signal. Consolidation will remove the potential of two control signals arriving shifted in time.
Figure 13 - Solution - Consolidating control signals before passing between clock domains
SNUG Boston 2008 Rev 1.0
20
Clock Domain Crossing (CDC) Design & Verification Techniques Using SystemVerilog
基于异步FIFO实现不同时钟域间数据传递的设计 [2006-12-1813:31:00|By:夏虫] 推荐 摘要：数据流在不同时钟域间的传递一直是集成电路芯片设计中的一个重点问题。本文通过采用异步FIFO的方式给出了这个问题的一种解决方法,并采用Verilog硬件描述语言通过前仿真和逻辑综合完成设计。 关键词：异步FIFO;时钟域;Verilog 引言 当今集成电路设计的主导思想之一就是设计同步化,即对所有时钟控制器件(如触发器、RAM等)都采用同一个时钟来控制。但在实际的应用系统中,实现完全同步化的设计非常困难,很多情况下不可避免地要完成数据在不同时钟域间的传递(如高速模块和低速模块之间的数据交换)。这时,如何保持系统的稳定,顺利完成数据的传输就成为一个重要的问题,这也是异步电路设计中最为棘手的问题。通常的做法是采用对每位信号加同步器或增加握手信号来解决这一问题,但这样会增加系统的复杂度且影响传输速度。本文的做法是在两个时钟域的交界处设计一个异步FIFO,通过它来实现数据流的传输。由发送时钟域将数据写入,接收时钟域将数据取出,在数据传输的同时实现了数据的缓存,因此是一种较理想的方法。 不同时钟域间数据传递的 问题及其解决方法 不同时钟域间数据传递的最重要问题就是亚稳态问题。当数据信号通过两个时钟域的交界处时,将会分别由这两个时钟来控制信号的值。此时如果两时钟信号的敏感沿非常接近并超过了允许的额度,则将出现数据信号的不稳定,即电路陷入亚稳态,也称为同步失败。亚稳态是在两时钟敏感沿靠得很近、第二级时钟敏感沿到来时其输入数据不稳时发生,可将其视为仅仅是第二级触发器输入信号不稳定所导致的结果。只要使输入信号稳定,就能解决亚稳态问题。 针对如上所述亚稳态的特点,可设计一个同步器来保证数据的稳定传输以解决这个问题。其原理在于使信号在新的时钟域中先稳定下来再进入相关的逻辑,以保证信号与新的时钟同步。本设计在时钟域的接口处就采用此法。 异步FIFO模块设计及实现 异步FIFO结构设计 本文所设计的异步FIFO采用循环队列方式,由独立的两个时钟Iclk和Oclk来控制读、写指针。模块结构如图1所示。 输入端口：输入端时钟Iclk,输出端时钟Oclk,8位并行输入数据Din,复位信号Rst_。 输出端口：8位并行输出数据Dout,FIFO写满信号Full,FIFO读空信号Empty。信号后缀：i—由输入时钟域控制、o—由输出时钟域控制、g—GRAY码、b—二进制自然码。
快时钟域信号到慢时钟域有可能的情况是： 快时钟域信号宽度比慢时钟信号周期窄，导致漏采。 解决的方法有： 1.将快时钟域信号延长，至少有慢时钟周期的一到两个周期宽 2.使用反馈的方法，快时钟域信号有效直到慢时钟域有反馈信号，表示已经正确采样此信 号，然后快时钟域信号无效。
通过反馈的方式很安全，但是从上图可以看出来延时是非常大的。慢时钟采快时钟信号，然后反馈信号再由快时钟采。 以上是简单的单个信号同步器的基本方法。 多个信号跨时钟域 多个控制信号跨时钟域仅仅通过简单的同步器同步有可能是不安全的。 简单举例，b_load和b_en同步至a_clk时钟域，如果这两个信号有一个小的skew，将导致在a_clk时钟域中两个信号并不是在同一时刻起作用，与在b_clk中的逻辑关系不同。解决的方法应该比较简单，就是将b_load和b_en信号在b_clk时钟域中合并成一个信号，然后同步至a_clk中。 如果遇到不能合并的情况，如译码信号。如下图
如果Bdec[0]、bdec[1]间存在skew将导致同步至a_clk中后译码错误，出现误码。在这种情况下，建议加入另一个控制信号，确保bdec[0]、bec[1]稳定时采。例如在bdec[0]、bec[1]稳定输出后一到两个周期b_clk域输出一个en信号，通知a_clk域此时可以采bdec[0]、bec[1]信号。这样可确保正确采样。 数据路径同步 对数据进行跨时钟域处理时，如果采用控制信号同步的方式进行处理的话，将是非常浩大的工程，而且是不安全的。 简单来说，数据同步有两种常见的方式： 1.握手方式 2.FIFO 简要说下握手方式，无非就是a_clk域中首先将data_valid信号有效，同时数据保持不变，然后等待b_clk中反馈回采样结束的信号，然后data_valid信号无效，数据变化。如有数据需要同步则重复上述过程。握手方式传输效率低，比较适用于数据传输不是很频繁的，数据量不大的情况。 FIFO则适合数据量大的情况，FIFO两端可同时进行读/写操作，效率较高。而且如果控制信号比较多，也可采用fifo方式进行同步，将控制信息与数据打包，写入FIFO，在另一端读取，解码，取得数据和控制信息。
Advanced Verification White Paper Five Steps to Quality CDC Verification Ping Yeung Ph.D. Mentor Graphics
CDC synchronizers are used to reduce the probability of metastable signals. Taking unpredictable metastable sig- nals and creating predictable behavior, they prevent metastable values from reaching the receiving clock domain.Metastability Effects Even when proper CDC synchronizers are used for all clock-domain crossings and all CDC protocols are cor-rectly implemented, metastability inevitably leads to unpredictable cycle-level timing [4, 5]. Traditional RTL simulation does not model metastability, therefore, it cannot be used to find functional problems that may arise when metastability manifests in hardware. We are going to show two scenarios in which the cycle-level timing of RTL simulation differs from the cycle-level timing of the actual hardware in the presence of metastability.In Figure 3, the incoming CDC signal, cdc_d , violates the register setup time. Although it is sampled correctly in RTL simulation, the register is metastable and the output settles to 0. As a result, the hardware transition is delayed by one cycle. Figure 2: A two-register CDC synchronizer. Figure 4: Hold time violation: hardware transition is advanced by one cycle. Figure 3: Setup time violation: hardware transition is delayed by one cycle.
亚稳态 Setup/hold time 是测试芯片对输入信号和时钟信号之间的时间要求。建立时间是指触发器的时钟信号上升沿到来以前，数据稳定不变的时间。输入信号应提前时钟上升沿（如上升沿有效）T时间到达芯片，这个T就是建立时间-Setup time.如不满足setup time,这个数据就不能被这一时钟打入触发器，只有在下一个时钟上升沿，数据才能被打入触发器。保持时间是指触发器的时钟信号上升沿到来以后，数据稳定不变的时间。如果hold time不够，数据同样不能被打入触发器。 建立时间(Setup Time)和保持时间（Hold time）。建立时间是指在时钟边沿前，数据信号需要保持不变的时间。保持时间是指时钟跳变边沿后数据信号需要保持不变的时间。如果不满足建立和保持时间的话，那么DFF将不能正确地采样到数据，将会出现亚稳态(metastability)的情况。如果数据信号在时钟沿触发前后持续的时间均超过建立和保持时间，那么超过量就分别被称为建立时间裕量和保持时间裕量。 在数字集成电路中，触发器要满足setup/hold的时间要求。当一个信号被寄存器锁存时，如果信号和时钟之间不满足这个要求，Q端的值是不确定的，并且在未知的时刻会固定到高电平或低电平。这个过程称为亚稳态
（Metastability）。 一些关于微电子方面的笔试题（zz) 1.FPGA和ASIC的概念，他们的区别。（未知） FPGA是可编程ASIC。 ASIC:专用集成电路，它是面向专门用途的电路，专门为一个用户设计和制造的。根据一个用户的特定要求，能以低研制成本，短、交货周期供货的全定制，半定制集成电路。与门阵列等其它ASIC(Application Specific IC)相比，它们又具有设计开发周期短、设计制造成本低、开发工具先进、标准产品无需测试、质量稳定以及可实时在线检验等优点. 2.建立时间是指触发器的时钟信号上升沿到来以前，数据稳定不变的时间。输入信号应提前时钟上升沿（如上升沿有效）T时间到达芯片，这个T就是建立时间-Setup time.如不满足setup time,这个数据就不能被这一时钟打入触发器，只有在下一个时钟上升沿，数据才能被打入触发器。保持时间是指触发器的时钟信号上升沿到来以后，数据稳定不变的时间。如果hold time不够，数据同样不能被打入触发器。 建立时间是指在时钟边沿前，数据信号需要保持不变的时
浅谈XLINX FPGA设计中跨时钟域的同步设计问题 摘要 本文介绍了FPGA设计中的同步设计原则并对FPG A设计中的触发器亚稳态问题进行了阐述本文通过具体的设计实例论证了跨时钟域同步处理的必要性并介绍了一种实现跨时 钟域同步处理的方法和其具体电路 关键字 同步设计异步设计触发器亚稳态时序稳定 一同步设计的原则 尽量使用同步电路避免使用异步电路这句话是电路设计的几个原则之一同异步设计相比同步设计设计出来的电路更稳定可靠在XILINX FPGA设计中时常 有设计人员遇到如下类似的问题 设计的电路升级困难可移植性差也就是说一些原本工作正常的电路移植到高端的FPGA中就根本工作不起来了 设计的电路一致性差同一电路设计每次布线后工作的结果不同 设计的电路时序仿真正常但实际电路上却工作不起来 设计的电路极易受毛刺的干扰 通常这些类似的问题都于电路的异步设计有关 二亚稳态 图1 触发器的亚稳态示意图 对于触发器当时钟沿到来时其输入要求是稳定的这时其输出也是稳定的但假如时钟沿到来时其输入也正在变化即翻转这时触发器会瞬时进入亚稳态通 常触发器对输入信号都有一个建立时间的要求也即setup时间当这一建立时间得 不到满足时触发器也会进入瞬时亚稳态如图1 通常触发器即使进入亚稳态也会很快进入稳态但其输出值是不定的这有可能对使我们设计的FPGA模块尤其是哪些有复杂状态机的模块产生错误的逻辑对于亚稳态问题我们还应明白亚稳态问题并非指输出结果数据的不确定性而是指输出变化的时序不确定性 遵循同步设计的原则有助于解决亚稳态问题使我们设计出稳定可靠的电路模块对于单时钟系统我们可以很方便地设计出稳定易于设计及仿真的同步单一时钟系统但在电信和数据通讯领域中我们设计的系统中往往具有多个时钟往往需要将数据或时序由一个时钟域传到另一个时钟域这类设计的难点在于实现不同时钟域之间数据和时序变化的稳定可靠地传递采用经验证的设计技术可以实现跨时钟域的同步设计进而设计出可靠工作的电路 三跨时钟域的异步设计案例 本人曾经设计过如下几个模块这些模块中的几个子模块分别工作在各自的时钟域
多时钟域数据传递的FPGA 实现 鲁 玲 (扬州大学能源与动力工程学院江苏扬州 225009) 摘 要:分析了多时钟域数据传递设计中亚稳态的产生以及对整个电路性能和功能的影响,以一款异步并行通信接口芯片的设计为例,详细描述了采用同步器、FIFO 实现8位并行数据到16位并行数据的两时钟域异步转换的过程。电路在 XilinxISE6.0环境下用Modelsim5.7进行了逻辑仿真,结果表明系统稳定可靠。 关键词:多时钟域;亚稳态;FP GA ;异步信号;FIFO 中图分类号:TP391.98 文献标识码:B 文章编号:10042373X (2007)212130203 An Implementation of Communicating Data bet w een Multi 2clock Domain B ased on FPG A L U Ling (Institute of Energy &Power ,Yanghou University ,Yangzhou ,225009,China ) Abstract :The paper analyses the metastability which is caused by communicating data between multi 2clock domain and effect of metastability to the circuit.For example ,the design of asynchronous parallel interface chip is described to make use of synchronizer and FIFO to transfer the data band f rom 8bits to 16bits between two clock domain in details.The circuit is simulated on a Modelsim5.7with Xilinx ISE6.0software and good test result has gotten. K eywords :multi 2clock domain ;metastability ;FP GA ;asynchronous signal ;FIFO 收稿日期:2007207225 随着EDA 技术的发展,由于其在电子系统设计领域中的明显优势,FP GA 已经在许多方面得到了广泛应用,特别是在无线通信领域,FP GA 以其极强的实时性,指令软件编程的极大灵活性赢得了巨大的市场。本文采用 FP GA 来设计一款广泛应用于计算机、Modem 、数据终端 以及许多其他数字设备之间的数据传输的专用异步并行通信接口芯片,实现了某一时钟域(如66M Hz )的8位并行数据到另一低时钟域(如40M Hz )16位并行数据的异步转换,并且客户可以根据自己的要求进行数据定义。完成数据在不同时钟域间的正确传递的同时防止亚稳态的出现,保持系统的稳定,是电路设计的关键。1 时钟域转换中亚稳态的产生 触发器是数字电路设计中的一个重要元件,而触发器工作过程中存在数据建立与保持时间的约束,如果这种约束得不到满足,触发器就会进入某个不确定状态———亚稳态[1]。亚稳态的存在可能导致连锁反应,以致引起整个系统功能混乱。在单时钟域电路设计中由于不存在时钟之间的延迟和错位,所以建立条件和保持条件的时间约束容易满足。而在多时钟域里由于各个模块的非同步性,则必须考虑亚稳态的发生,如图1 所示。 图1 多时钟域亚稳态的产生 2 多时钟域数据传递方案 多时钟域传递的信号有两种,其一为控制信号,其二为数据流信号。针对这两种不同的信号,分别采取不同方案遏制系统堕入亚稳态。对控制信号采用同步器装置,即在2个不同的时钟域之间插入同步器;而对于不同独立时钟域之间的数据流传递,为了避免异步时钟域产生错误的采样电平,采用FIFO 存储器作为其转换接口,在输入端口使用写时钟写数据,在输出端口使用读时钟读数据,这样就完成了异步时钟域之间的数据交换[2]。 芯片的总体逻辑框图如图2所示,图中输入输出信号定义如表1所示。 从逻辑结构上将芯片划分为3块:写时钟域I/O BU FFER 、读时钟域I/O BU FFER 及FIFO 存储器。I/O BU FFER 的主要作用是对外部信号进行预处理,消除外 31自动化技术鲁 玲:多时钟域数据传递的FP GA 实现
Metastability in the asynchronous clocks and Synchronizer 摘要：相较纯粹的单一时钟的同步电路设计，设计人员更多遇到的是多时钟域的异步电路设计。因此，异步电路设计在数字电路设计中的重要性不言而喻。本文主要就异步设计中涉及到的亚稳态问题，作简要介绍，并提出常用的解决办法——即同步器的使用。 关键词：异步电路设计、亚稳态、同步器。 Abstract: Compared with the pure one-clock synchronous designs，the designers more often deal with the multi-clock asychronous designs. Therefore, asynchronous circuit design is very important in the field of digital circuit design. This paper briefly describes the problematic metastability in the asynchronous designs and presents a regular solution——synchronizer. Key words: Asynchronous circuit design, Metastability, Synchronizer. 毫无疑问，单一时钟域的电路设计是数字电路中最基本的技能，其时序分析（Timing Analysis）也是最简单的。与之相对，在多时钟域中跨时钟域传输信号易出现亚稳态，加上自动时序分析工具对异步信号处理的力不从心，这些都使得多时钟域的异步设计和分析较为困难。不幸的是，现实世界是异步的。如我们常常看见的键盘输入、磁盘文件传输、UART（通用异步收发器）等等，都是异步时序的事例。 1 亚稳态（metastability） 时序电路采用触发器和锁存器作为存储单元，这两种器件都易进入亚稳态[1]。所谓亚稳态是指触发器无法在某个规定的时间段内达到一个可确认的状态。如图1所示，对任何一种触发器，在时钟触发沿前后存在一个小的时间窗口（称为判决窗口，decision window），输入信号在判决窗口内必须保持稳定，否则，触发器就会进入亚稳态，既无法预测该单元的的输出电平，也无法预测何时输出才能稳定在某个电平上。 这个判决窗口由建立时间（setup time）和保持时间（hold time）两部分组成。并且时间窗口也是多种因素的函数，包括触发器设计、实现技术、运行环境以及无缓冲输出的负载等。输入信号陡峭的边沿可以将此窗口减至最小，随着时钟频
跨时钟域问题(Clock Domain Crossing) –同两个时钟域打交道！ 引言：设计者有时候需要将处于两个不同时钟域的系统对接，由于接口处是异步（会产生setuptime 和holdtime violation，亚稳态以及不可靠的数据传输）的，因此处理起来较同步逻辑更棘手，需要寻求特殊处理来进行接口界面的设计。 任意的两个系统如果满足以下条件之一，就可称其为异步的： (1)工作在不同的时钟频率上； (2)工作频率相同，但是相位不相同； 处理跨时钟域的数据传输，有两种实现方案： （1）采用握手信号来交互 （2）以异步FIFO来实现 1.1、以握手信号交互： 假设系统A以这种方式向系统B传递数据，握手信号分别为req和ack。 握手协议： Transmitter asserts the req (request) signal, asking the receiver to accept the data on the data bus.
Receiver asserts the ack (acknowledge) signal, asserting that it has accepted the data. 这种处理跨时钟域的方式很直接，但是也最容易产生亚稳态，由于系统A发送的req信号需要系统B中的时钟去sample，而系统B发出的ack信号又需要系统A中的时钟去sample，这样两边都存在着setup time和hold time violation的问题。为了避免由于setup time和hold time vilation所造成的亚稳态，通常我们可以将异步时钟域交互的信号用local system的时钟打两级甚至三级寄存器，以此来消除亚稳态的影响。下图以系统A发送到系统B的req信号示例消除亚稳态的方法： 当然，这种处理方式是以损失传输速率为代价的，加入两到三级寄存器同步异步时钟域的信号，会有许多时钟周期浪费在了系统的“握手”。 有时候，我们也会对数据多打两拍reg来同步，但通常情况下，我们并不会采取这种方式，它不仅需要较多逻辑，而且收效甚微。通常对数据的同步是以异步FIFO来实现的。下图给出了1bit数据传输打两拍reg所做的同步，从中可以发现，与前面的握手信号处理完全一致。 1.2 结合实际工作谈谈以握手信号处理的跨时钟域问题 由于所在项目的逻辑设计相当庞大，超出了最初的预估，同时也鉴于产品化方向考虑可以单独流片，因此对整个逻辑结构进行了划分，在做FPGA原型验证的时候，将这两块逻辑分别映射到不同的器件单元中，这里暂且称它们为wrapper0和wrapper1。实践结果表明，wrapper0和wrapper1的相位需要存在180度的反相，弥补板级走线的延迟影响。
异步FIFO的实现方式 实验目的 本次实验介绍一种异步FIFO的实现方式。使用FIFO存储器可以在两个不同时钟系统之间快速而方便的传输数据。另外，在网络接口，图像处理等方面异步FIFO存储器也得到了广泛的应用。因此，异步FIFO存储器具有较大的研究和应用价值。 异步FIFO的介绍和整体结构 异步FIFO(First In First Out)存储器是指向FIFO缓冲器中写入数据的时钟域和从FIFO缓冲器中读取数据的时钟域是不同的，这两个时钟之间没有必然的因果关系。异步FIFO是一种先进先出的电路，使用在异步时钟域数据接口的部分，用来存储、缓冲在两个异步时钟之间的数据传输。在异步电路中，由于时钟之间周期和相位完全独立，所以数据的丢失概率不为零。如何设计一个高可靠性、高速的异步FIFO存储器便成为一个难点。 异步FIFO的一般结构如图1所示，都是由一个读时钟域电路、一个写时钟域电路和一个双端口的RAM来构成的。异步FIFO与同步FIFO所做的工作是相同的，都是在写信号有效时写数据到RAM中，在读信号有效时把数据从RAM中读出，所以对于中间部分的RAM 设计是比较简单的。另外，读电路和写电路单独实现起来也是比较容易的，只需要按照同步FIFO的工作情况，如果没有写满或读空的状态时每写一个数据就把写地址加1,每读一个数据就把读地址减1。设计难点在于两个时钟域的交叠部分:满、空状态的产生，这也是设计的重点。
图1 异步FIFO结构 针对这个问题，先从对亚稳态的处理开始介绍 亚稳态的处理 一个触发器进入亚稳态时，既无法预测该单元的输出电平，也无法预测何时输出才能稳定在某个正确的电平上。在这个稳定期间，触发器输出一些中间级电平，或者可能处于振荡状态、并且这种无用的输出电平可以沿信号通道上的各个触发器级联式传播下去。亚稳态发生的原因是由于在同步系统中，如果触发器的建立时间或保持时间不满足，就可能产生亚稳态，此时触发器输出端Q在亚稳态是指触发器无法在某个规定时间段内达到一个可确认的状态，逻辑误判有可能通过电路的特殊设计减轻危害(如本设计中将使用的Gray码计数器)，而亚稳态的传播则扩大了故障面，难以处理。 在数字集成电路中寄存器要满足建立时间和保持时间。建立时间是在时钟翻转之前数据输入必须有效的时间，保持时间是在时钟沿之后数据输出必须仍然有效的时间。当一个信号被寄存器锁存时，如果信号和时钟之间不满足这个要求，Q的值是不确定的，并且在未知的时刻会固定到高电平或低电平。此时寄存器进入了亚稳态(Metastability)。解决这一问题的最简单方法是使用同步器，使得在另一个时钟域采样时信号足够稳定。 同步器的设计本身就是一个比较麻烦的问题，本次设计中也不深入讨论一些细节性的问题，直接采用两级采样的同步器，避免了使用一级同步器仍可能出现亚稳态的情况。每个这样的同步器都具有一个等于时钟周期的等待时间。这种同步器可以把一些亚稳态的值同步为确定值，但并不一定是正确值，同时有一些亚稳态也还是无法稳定成确切值的，这种情况称为同步出错。由于同步出错的随机性，很难对它们进行跟踪。如果想进一步降低亚稳态出现的概率、可以再増加同步器的级数，但是太多的同步器会使系统的性能下降，所以系统中不会用太多的同步器，一般使用两个同步器已经足够。 空满状态的判断 之所以在前面介绍了亚稳态的问题，是因为这是判断满状态或空状态无法回避的一个问题。因为读电路在读控制时维持一个地址指针，写电路在写控制时维持一个地址指针，简单来说，这两个地址指针直接一比较，就能得到空满的判断结果，但是实际操作起来非常麻烦。例如对于满状态来说，这是写入电路所关心的状态，因为满状态下不能继续写入数据，但是空状态对于写电路没有影响。如果写入电路要判断当前FIFO是否为满，就需要把写电路自身维持的写指针和读电路维持的读指针做比较，这个读指针就需要送入写电路中，此时就发生了穿过时钟域的问题，也就是说，读指针要从读时钟域同步到写时钟域，然后参与判断，此时就需要前面介绍的同步器。同样，对于空状态来说，这是读出电路所关心的状态，也是由读电路来维持的，因为空状态下再读数就会得到错误的数据，但是满状态下读数是没有影响的。如果读电路要判断当前FIFO是否为空，就需要把写时钟域中的写指针取到读时钟域来，和读时钟域的读指针进行比较得出是否是空状态，同样跨越了时钟域。在跨时钟域系统中希望出现错误的概率越低越好，此时格雷码无疑是最好的一个选择。格雷码属于可靠性编码，是一种误差最小化的编码，它大大减少了由一个状态到下一个状态时电路混淆。由这种编码相邻的两个码组之间只有一位不同，和其他编码同时改变2位和多位的情况相比更为可靠。表1所示是格雷码与二进制码的对应关系。
跨时钟域信号同步方法6种 ASIC中心 1 引言 基于FPGA的数字系统设计中大都推荐采用同步时序的设计，也就是单时钟系统。但是实际的工程中，纯粹单时钟系统设计的情况很少，特别是设计模块与外围芯片的通信中，跨时钟域的情况经常不可避免。如果对跨时钟域带来的亚稳态、采样丢失、潜在逻辑错误等等一系列问题处理不当，将导致系统无法运行。本文总结出了几种同步策略来解决跨时钟域问题。 2 异步设计中的亚稳态 触发器是FPGA设计中最常用的基本器件。触发器工作过程中存在数据的建立(setup)和保持(hold)时间。对于使用上升沿触发的触发器来说，建立时间就是在时钟上升沿到来之前，触发器数据端数据保持稳定的最小时间。而保持时间是时钟上升沿到来之后，触发器数据端数据还应该继续保持稳定的最小时间。我们把这段时间成为setup-hold时间(如图1所示)。在这个时间参数内，输入信号在时钟的上升沿是不允许发生变化的。如果输入信号在这段时间内发生了变化，输出结果将是不可知的，即亚稳态 (Metastability) 图1 一个信号在过渡到另一个时钟域时，如果仅仅用一个触发器将其锁存，那么采样的结果将可能是亚稳态。这也就是信号在跨时钟域时应该注意的问题。如图2所示。 信号dat经过一个锁存器的输出数据为a_dat。用时钟b_clk进行采样的时候，如果a_dat正好在b_clk的setup-hold时间内发生变化，此时b_ dat就既不是逻辑"1"，也不是逻辑"0"，而是处于中间状态。经过一段时间之后，有可能回升到高电平，也有可能降低到低电平。输出信号处于中间状态到恢复为逻辑"1"或逻辑"0"的这段时间，我们
1.1ASYNCHRONOUS INTERFACE – CDC GUIDELINE 1.1.1INTRODUCTION ASIC design is becoming more complex due to more and more IP integrated in a chip, and data is frequently transferred from one clock domain to another domain. Clock domain crossing issue becomes more and more important vector in a multi-clock, stable work chip. This document mainly introduce below topics: a. Where will occur CDC; b. What problem will occur due to CDC issue; c. How to design CDC logic correctly. 1.1.2APPLICATION AREA In a multi-clock design, clock domain crossing occurs whenever data is transferred from a flop driven by one clock to a flop driven by another clock. As it is shown in Figure 1-1, Figure 1-1 Clock domain crossing *Note: definition of terminology: Source clock: Clock A in figure 1-1 is defined as source clock; Destination clock: Clock B in figure 1-1 is defined as destination clock; Source clock domain: All the logic design whose reference clock is Clock A, like flip-flop FA in figure 1-1; Destination clock domain: All the logic design whose reference clock is Clock B, like flip-flop FB in figure 1-1; 1.1.3PROBLEM DEFINITION Meta-stability, glitch, multi-fanout and re-convergence may occur in an asynchronous design, they may cause design entering an un-anticipant state and result in function error.
异步FIFO设计文档 一、概述 在大规模ASIC或FPGA设计中，多时钟系统往往是不可避免的，这样就产生了不同时钟域数据传输的问题，其中一个比较好的解决方案就是使用异步FIFO来作不同时钟域数据传输的缓冲区，这们既可以使相异时钟域数据传输的时序要求变得宽松，也提高了它们之间的传输效率。此文内容就是阐述异步FIFO 的设计。 二、设计原理 2.1结构框图 Fig. 2.1.1 如上图所示的同步模块synchronize to write clk，其作用是把读时钟域的读指针rd_ptr采集到写时钟（wr_clk）域，然后和写指针wr_ptr进行比较从而产生或撤消写满标志位wr_full；类似地，同步模块synchronize to read clk的作用是把写时钟域的写指针wr_ptr采集到读时钟域，然后和读指针rd_ptr进行比较从而产生或撤消读空标志位rd_empty。 另外还有写指针wr_ptr和写满标志位wr_full产生模块，读指针rd_ptr和读空标志位rd_empty产生模块，以及双端口存储RAM模块。
2.2 二进制计数器存在的问题 异步FIFO读写指针需要在数学上的操作和比较才能产生准确的空满标志位，但由于读写指针属于不同的时钟域及读写时钟相位关系的不确定性，同步模块采集另一时钟域的指针时，此指针有可能正处在跳变的过程中，如图Fig.2.2.1所示，那么采集到的值很有可能是不期望的值，当然，不期望的错误结果也会随之发生。 Fig. 2.2.1 上图中，rd_ptr2sync 3和4以及4和5之间的中间态是由于到各寄存器的时钟rd_clk存在偏差而引起的。二进制的递增操作，在大多数情况下都会有两位或者两以上的bit位在同一个递增操作内发生变化，但由于实际电路中会存在时钟偏差和不同的路径延时，二进制计数器在自增时会不可避免地产生错误的中间结果，如图Fig.2.2.2。 Fig.2.2.2 上图是Fig.2.2.1的电路原型以及局部波形的放大。由于rd_clk上升沿到达
一、前言 跨时钟域的同步处理，使用异步FIFO是常用的方式之一，对于异步FIFO的设计，网上的大部分资料来源于《Simulation and Synthesis Techniques for Asynchronous FIFO Design》一文 其异步FIFO的结构如下图所示 本文不是介绍上图描述的设计。我从基本的数字电路时序开始，介绍异步FIFO的相关问题。最后介绍如何用时序约束保证设计的正确性 二、数字电路时序 对于数字电路来讲，我们的信号在时钟边沿发生变化，Dat1信号是一种理想情况，而Dat2是实际情况，其特点是 一、相对时钟边沿有延时 二、信号变化有一段时间(电平转换时间)，在这段时间就是亚稳态 在亚稳态期间进行数据采样，不能获得稳定的值。数字电路中经过时序约束，在T1产生的信号，在T2一定稳定(否则就是不满足时序)，所以对于只有一个时钟的数字电路来说，它在T1和T2都能获得稳定的信号(T1时刻的值为0、T2时刻的值为1)
三、跨时钟域时序问题 对于异步时钟而言(相位不同)，对于CLK1产生的信号，CLK2有可能在任意时刻进行数据采样 在FIFO的设计中，将会产生2种信号，一种是数据本身(用Data表示)，另外一种是指示数据是否有效(用valid表示)，注意(valid不一定是一个比特的寄存器，可以是由FIFO中的读写指针产生而来，例如fifo的full或empty状态) 异步FIFO的问题在于，如果CLK2在时钟T2进行采样，那么有可能得到valid有效，而数据无效的情况。这样在CLK2采样取得的设计就是错误的数据。 四、处理异步FIFO的valid和data（理论基础） 我们假设valid为低电平表示没有数据，高电平为有数据，解决的办法就是，当CLK对valid进行采样时，即使valid处于亚稳态期间，数据信号也是稳定的 如上图所以，在T1时刻进行上升沿采样，虽然valid是一个亚稳态状态，但是此时Data 是一个稳定的值，如果在T1时刻采样的valid为1，那么可以得到稳定的Data信号，如果在T1时刻采样的valid为0，那么控制逻辑认为在T1无法获得数据，从而在下一个时钟获取 注意：T2时刻是在下降沿进行采样，而此时的Data信号也是稳定的
种6跨时钟域信号同步方法． 跨时钟域信号同步方法6种 ASIC中心 1 引言 基于FPGA的数字系统设计中大都推荐采用同步时序的设计，也就是单时钟系统。但是实际的工程中，纯粹单时钟系统设计的情况很少，特别是设计
模块与外围芯片的通信中，跨时钟域的情况经常不可避免。如果对跨时钟域带 来的亚稳态、采样丢失、潜在逻辑错误等等一系列问题处理不当，将导致系统无法运行。本文总结出了几种同步策略来解决跨时钟域问题。 2 异步设计中的亚稳态 触发器是FPGA设计中最常用的基本器件。触发器工作过程中存在数据的建立(setup)和保持(hold)时间。对于使用上升沿触发的触发器来说，建立时间就是在时钟上升沿到来之前，触发器数据端数据保持稳定的最小时间。而保持时间是时钟上升沿到来之后，触发器数据端数据还应该继续保持稳定的最小时间。我们把这段时间成为setup-hold时间(如图1所示)。在这个时间参数内，输入信号在时钟的上升沿是不允许发生变化的。如果输入信号在这段时间内发生了变化，输出结果将是不可知的，即亚稳态 (Metastability) 图1 一个信号在过渡到另一个时钟域时，如果仅仅用一个触发器将其锁存，那么
采样的结果将可能是亚稳态。这也就是信号在跨时钟域时应该注意的问题。如图2所示。 信号dat经过一个锁存器的输出数据为a_dat。用时钟b_clk进行采样的时候，如果a_dat正好在b_clk的setup-hold时间内发生变化，此时b_ dat，而是处于中间状态。经过一段时间之后，ぜ，也不是逻辑?就既不是逻辑． 有可能回升到高电平，也有可能降低到低电平。输出信号处于中间状态到恢复为逻辑?或逻辑ぜ的这段时间，我们称之为亚稳态时间。 触发器进入亚稳态的时间可以用参数MTBF(Mean Time Between Failures)来描述，MTBF即触发器采样失败的时间间隔，表示为：
1. 应用背景 1.1 亚稳态发生原因 在FPGA系统中，如果数据传输中不满足触发器的T su和T h不满足，或者复位过程中复位信号的释放相对于有效时钟沿的恢复时间（recovery time）不满足，就可能产生亚稳态，此时触发器输出端Q在有效时钟沿之后比较长的一段时间处于不确定的状态，在这段时间里Q端在0和1之间处于振荡状态，而不是等于数据输入端D的值。这段时间称为决断时间（resolu tion time）。经过resolution time之后Q端将稳定到0或1上，但是稳定到0或者1，是随机的，与输入没有必然的关系。 1.2 亚稳态发生场合 只要系统中有异步元件，亚稳态就是无法避免的，亚稳态主要发生在异步信号检测、跨时钟域信号传输以及复位电路等常用设计中。 1.3 亚稳态危害 由于产生亚稳态后，寄存器Q端输出在稳定下来之前可能是毛刺、振荡、固定的某一电压值。在信号传输中产生亚稳态就会导致与其相连其他数字部件将其作出不同的判断，有的判断到“1”有的判断到“0”，有的也进入了亚稳态，数字部件就会逻辑混乱。在复位电路中产生亚稳态可能会导致复位失败。怎么降低亚稳态发生的概率成了FPGA设计需要重视的一个注意事项。 2. 理论分析 2.1 信号传输中的亚稳态 在同步系统中，输入信号总是系统时钟同步，能够达到寄存器的时序要求，所以亚稳态不会发生。亚稳态问题通常发生在一些跨时钟域信号传输以及异步信号采集上。 它们发生的原因如下： （1）在跨时钟域信号传输时，由于源寄存器时钟和目的寄存器时钟相移未知，所以源寄存器数据发出数据，数据可能在任何时间到达异步时钟域的目的寄存器，所以无法保证满足目的寄存器Tsu和Th的要求； （2）在异步信号采集中，由于异步信号可以在任意时间点到达目的寄存器，所以也无法保证满足目的寄存器Tsu和Th的要求；
跨时钟域 4.1跨时钟域处理（20160620） 时钟对于FPGA就像我们的心脏，时刻控制着“跳动”的频率以及“血液”的流速；时钟域好比通过心脏的血液血型，不同血型的血液会产生排斥作用。在设计中建议时钟越少越好，好比于人有两个甚至更多的心脏，其内脏工作将会多么混乱。 但是某些情况下多时钟又不可避免，比如从FPGA外部输入的数据，其自带有个随路时钟，数据终归要在FPGA内部时钟域下处理，这来自外部的“血液”如何处理才能与内部的“血液”融合呢？配对及转换工作则是必不可少的，这就引入本节的主题：跨时钟域处理（Clock Domain Crossing）： 跨时钟域处理需要两方面的工作：1、设计者处理；2、FPGA工具（Vivado）处理。 1.设计者处理 首先讲解一下如果不进行跨时钟域处理，会出现什么问题呢？如图1所示路径，QA属于CLKA时钟域的数据输出，另一个时钟CLKB去捕获节点REG A 的输出QA，假定CLKA与CLKB是异步时钟，它们之间的相位并不固定，因此捕获过程中可能会出现建立冲突（setup violation）和保持冲突（hold violation），如图2所示，左右分别为发生建立冲突和保持冲突的情况。 图1
图2 当冲突出现时（我感觉整个人都不好了），会发生什么事情呢？在发生建立冲突或者保持冲突，捕获节点（REG B）会处于一个不定的状态，正常的状态是高电平或者低电平，而此时的状态停留在高电平和低电平的中间，无效的电平X，称这个状态为亚稳态。 如图3所示，捕获节点输出保持在亚稳态，可能在整个时钟周期内都保持在亚稳态，由于不正确的状态，其后连接的逻辑在功能实现上就会出现问题，比如一个判断信号上升沿的逻辑，通常判断D==HIGH&&D_PREV==LOW（D为信号当前电平状态，D_PREV为信号上个时钟的电平状态）是否成立，而发生亚稳态时则D_PREV==X，这个上升沿将会错过。因此，加入跨时钟域处理设计是必须的。 图3 对于单比特信号的跨时钟域处理，常用的方法是“打两拍”，即在捕获时钟域中加入两个寄存器进行时钟转换，如图4所示，加入REG B1和REG B2，虽然REG B1处于亚稳态状态。 但是REG B2的输出QB2能稳定在正常的电平上，由于REG B1和REG B2之间没有多余的逻辑，REG B1能有充裕的时间稳定状态，此情况下REG B2能完美地隐藏REG B1的亚稳态。在捕获时钟的频率比较高的情况下，如果一个REG B2还未能隐藏亚稳态，拍数也可以增加三个或者更多，当然一般情况下，两拍足矣。
异步FIFO结构及FPGA设计---跨时钟域设计 2008/12/17 17:17[未分类 ] 异步FIFO 结构及FPGA 设计 吴自信,张嗣忠. 单片机及嵌入式系统应用,2000 摘要：首先介绍异步FIFO的概念、应用及其结构,然后分析实现异步FIFO的难点问题及其解决办法; 在传统设计的基础上提出一种新颖的电路结构并对其进行综合仿真和FPGA实现。 1、异步FIFO介绍 在现代的集成电路芯片中,随着设计规模的不断扩大,一个系统中往往含有数个时钟。多时钟域带来的一个问题就是,如何设计异步时钟之间的接口电路。异步FIFO（First In First Out）是解决这个问题一种简便、快捷的解决方案。使用异步FIFO可以在两个不同时钟系统之间快速而方便地传输实时数据。在网络接口、图像处理等方面, 异步FIFO得到了广泛的应用。 异步FIFO是一种先进先出的电路,使用在需要产时数据接口的部分,用来存储、缓冲在两个异步时钟之间的数据传输。在异步电路中,由于时钟之间周期和相位完全独立,因而数据的丢失概率不为零。如何设计一个高可靠性、高速的异步FIFO电路便成为一个难点。本文介绍解决这一问题的一种方法。 由图1可以看出：整个系统分为两个完全独立的时钟域--读时钟域和写时间域; FIFO的存储介质为一块双端口RAM,可以同时进行读写操作。在写时钟域部分,由写地址产生逻辑产生写控制信号和写地址; 读时钟部分由读地址产生逻辑产生读控制信号和读地址。在空/满标志产生部分,由读写地址相互比较产生空/满标志。 2、异步FIFO的设计难点 设计异步FIFO有两个难点：一是如何同步异步信号,使触发器不产生亚稳态; 二是如何正确地设计空、满以及几乎满等信号的控制电路。 下面阐述解决问题的具体方法。 2.1 亚稳态问题的解决