共140页文档名称大规模逻辑设计指导书机密1.0密级产品版本文档编号研究管理部文档中心
大规模逻辑设计指导书
第一篇 方法论
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2001-8-28版权所有侵权必究第2页共142页目 录
375.2代码编写中容易出现的问题.............................................365.1.12FSM...........................................................365.1.11Comments.......................................................365.1.10Macros..........................................................355.1.9Combinatorial Vs Sequential Logic ......................................345.1.8Assignment.......................................................335.1.7Writing functions...................................................335.1.6case 语句.........................................................325.1.5IF 语句..........................................................315.1.4Expressions.......................................................315.1.3Net and Register....................................................295.1.2Modules .........................................................285.1.1选择有意义的信号和变量名对设计是十分重要的命名包含信号或变量诸如出处有效状态等基本含义下面给出一些命名的规则..................285.1Verilog 编码风格......................................................285规范内容..............................................................284引用标准和参考资料.....................................................283定义..................................................................282范围..................................................................281目的..................................................................28第二章VERILOG语言编写规范...............................................268.5 参数化元件实例......................................................258.4 程序包书写实例......................................................248.3 函数书写实例.......................................................228.2 VHDL 编写范例......................................................228.1 VHDL保留字........................................................228附录..................................................................217.5 多赋值语句案例三态总线.............................................207.4 避免使用Latch.......................................................207.3 考虑综合的执行时间..................................................207.2组合逻辑描述的多种方式...............................................197.1 资源共享问题.......................................................197 代码编写中容易出现的问题................................................186代码模块划分...........................................................185.1.13 TAB键间隔......................................................185.1.12Comments.......................................................185.1.11 FSM有限状态机...............................................185.1.10package.........................................................175.1.9 类属( generics)....................................................175.1.8 procedure........................................................165.1.7 function.........................................................165.1.6 运算符(operator)...................................................125.1.5 语句............................................................105.1.4实体............................................................95.1.3 信号和变量.......................................................95.1.2数据对象和类型....................................................85.1.1标识符Identifiers)命名习惯...........................................75.1 VHDL编码风格.......................................................75规范内容...............................................................74引用标准和参考资料......................................................73定义...................................................................72范围...................................................................71目的...................................................................7第一章 VHDL语言编写规范.................................................
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2001-8-28版权所有侵权必究第3页共142
页894.1合理选择加法电路....................................................894设计技巧..............................................................883.10时钟电路设计.......................................................873.9异步复位电路设计....................................................863.8三态电路设计........................................................853.7合理使用内部RAM....................................................823.6错误地使用变量或信号.................................................823.5同一个信号在两个或两个以上的process中赋值...............................813.4产生不必要的Latch....................................................803.3错误使用inout........................................................803.2采用std_logic以外的信号类型............................................803.1.2采用时间相关语句仿真语句.......................................803.1.1信号或变量赋初值..................................................803.1不可综合的代码......................................................793常见问题..............................................................782.2代码模块划分........................................................782.1代码编写风格........................................................782VHDL代码风格.........................................................781前言..................................................................78第五章 VHDL数字电路设计指导..............................................778ALTERA参考设计准则....................................................767 时序设计的可靠性保障措施................................................726 全局信号的处理方法.....................................................715 时延电路处理..........................................................704SET和RESET信号处理...................................................693.4 不建议使用电路......................................................593.3 异步设计中常见问题及其解决方法........................................593.2 同步电路的设计规则..................................................583.1同步电路的优越性....................................................583同步电路设计...........................................................572 时序分析基础..........................................................571 设计可靠性...........................................................57第四章同步电路设计技术及规则...............................................544.2ASIC设计如何考虑可靠性...............................................524.1ASIC可靠性设计......................................................524附录..................................................................523.4设计的规范性........................................................523.3设计的可靠性........................................................513.2.5设计验证仿真测试方案...........................................503.2.4具体电路设计详细设计文档.......................................493.2.3确定关键电路时序和模块间接口时序总体方案.........................493.2.2功能模块划分.....................................................493.2.1设计目标分析.....................................................493.2基本设计流程........................................................483.1设计工程师基本素质要求...............................................483可编程ASIC设计........................................................472.3根据市场需求和产品发展策略确定芯片开发策略..............................472.2芯片设计发展趋势....................................................462.1芯片设计类型........................................................462芯片设计发展趋势.......................................................461引言..................................................................45第三章 可编程ASIC设计方法简介.............................................446.2testbench编写示例.....................................................436.1Module 编写示例......................................................436附录.................................................................. 绝密请输入文档编号
2001-8-28版权所有侵权必究第4页共142页
