Director, MSU Manufacturing Research Consortium

A Genetic Algorithm Approach to Compaction, Bin Packing, and Nesting

Problems

? Erik D. Goodman,Alexander Y. Tetelbaum, and Victor M. Kureichik

1994, Michigan State University

July 12, 1994

All Rights Reserved

Erik D. Goodman, Professor and Director

A. H. Case Center for Computer-Aided

Engineering and Manufacturing

Director, MSU Manufacturing Research Consortium

Professor, Electrical Engineering, Mechanical Engineering

College of Engineering

Michigan State University

Alexander Y. Tetelbaum, President and Professor

International Solomon University (Kiev, Ukraine)

Adjunct Professor, Electrical Engineering

College of Engineering

Michigan State University

Victor M. Kureichik, Professor

Taganrog State University of Radio-Engineering (Russia)

Visiting Professor, Electrical Engineering

College of Engineering

Michigan State University

TECHNICAL REPORT # 940702

CASE CENTER FOR COMPUTER-AIDED

ENGINEERING AND MANUFACTURING

MICHIGAN STATE UNIVERSITY

TABLE OF CONTENTS

1. INTRODUCTION (1)

1.1. Report Overview (1)

1.2. Research Tools and Validation (4)

2. BACKGROUND (6)

2.1. Introduction to Layout Compaction (6)

2.2. Basic Definitions and Taxonomy of Compaction (7)

2.3. Algorithms for Compaction (8)

2.3.1. Constraint-graph 1-D Compaction Algorithms (8)

2.3.2. Two-dimensional compaction (2-D compaction) (12)

2.3.3. Constraint-graph hierarchical compaction (13)

2.3.4. Wire length minimization [40,41] (14)

2.4. Layout Approaches Based on Genetic Algorithms (15)

2.5. Bin Packing, Nesting and Compaction Using Genetic Algorithms (17)

2.5.1. 1-D Bin Packing (17)

2.5.2. 2-D Bin Packing and Nesting (23)

2.5.3. 3-D Bin Packing (30)

2.5.4. Compaction (32)

2.6. Conclusions (35)

3. PROJECT DESCRIPTION (53)

3.1. Project Statement (53)

3.2. Goals Statement (53)

3.3. The Approach (54)

3.3.1. The Representation (54)

3.3.2. The Genetic Operators (56)

3.3.3. The Fitness Function (58)

3.3.4. The Parallel GA Architecture (58)

3.4. Sequence of Problem Refinement (60)

3.5. Contribution and Impact (62)

4. BIBLIOGRAPHY (63)

1. INTRODUCTION

This technical report is prepared to record the preliminary work carried out in beginning a research project on the solution of a group of related problems by means of Genetic Algorithms (GA’s). These problems include integrated circuit layout compaction, bin packing, and nesting. The principal problem is compaction, with the others serving to illuminate and guide the compaction work, as well as possibly receiving benefits from new tools developed. Efficient and near-optimal solution of the compaction problem will enhance the linkage between symbolic level modeling of the layout and the mask level design of hierarchical (fragment-based), ultra-fast, low-power analog and logic circuits. The research goals are to develop new methodologies, abstractions, and theory that lead to more efficiently defined and utilized Computer-Aided Design (CAD) algorithms and tools for compaction, bin packing and nesting. These new methodologies will incorporate important improvements in the handling of the physical, technological, and optimization aspects of compaction. More effective solution of the bin packing and nesting problems can help to solve the compaction problem, as well as being valuable in their own right for many practical problems. This will be accomplished by defining a new approach to the use of Genetic Algorithms (GAs)--for the compaction, bin packing, and nesting problems.

The research will concentrate mostly on the application area of high-speed, low-power analog and digital circuits with clock rates up to 20 GHz. In many applications in this high performance area, dramatically reduced chip area and signal delays are important design requirements. The technology area of interest is multi-chip modules (MCM) based on current or advanced silicon and GaAs technologies [1]. These technologies have the potential to deliver improvements in power management, low voltage operation, low crosstalk interconnects, and clock frequencies. The CAD area of concentration deals with the compaction, bin packing, and nesting problems and the solving of them based on GAs. These algorithms, using simple encoding and recombination mechanisms, display complicated behavior, and they turned out to be useful in solving some extremely difficult problems.

1.1. Report Overview

The rapid design of VLSI systems plays an important role in the progress of science and technology. In general, several important problems can be described in VLSI CAD systems. They are typically design specification, functional design, logical design, circuit design, physical design, and fabrication (technology design). To link these problems, we must perform functional and logical simulation, circuit analysis, extraction and verification. Physical design automation of VLSI systems consists of six major problems. They are partitioning, placement, assignment and floorplanning, routing, symbolic layout and compaction, and verification.

Traditional solution of most of the VLSI physical design problems is carried out by iterative methods [2,3]. These methods assume successive improvement of an initial variant, which is obtained by one of the constructive algorithms through local replacement of elements. However, these methods have a serious fault -- their use of a single variant of the initial solution.

Besides, when a satisfactory approximate solution is obtained by the constructive algorithms, the iterative algorithms stop at a local optimal solutions which could not be improved by further iterative steps of the same process. One way to improve the quality of solution is to incorporate new methodologies into CAD systems. In this work, we will develop and apply genetic algorithms (GA’s), which have recently received widespread attention.

In 1975, J. Holland [4] described a methodology for studying natural adaptive systems and designing artificial adaptive systems. It is now frequently used as an optimization method, based on analogy to the process of natural selection in biology. The biological basis for the adaptation process is evolution from one generation to the next, based on elimination of weak elements and retention of stronger elements ("survival the fittest" -- those with the best performance in the current environment). Of course, over the longer term, it is not the strong individuals themselves which ultimately survive, but rather offspring related to them genetically in proportion to their reproductive fitness or success at reproduction. The searching of this representation space is performed using so-called "genetic algorithms" [4-6].

GAs are now widely recognized as an effective search paradigm in artificial intelligence, image processing, job scheduling, pattern recognition and many other areas [4-6], particularly as a method for gaining relatively good solutions to NP-hard optimization problems of high dimensionality. A GA maintains a population of strings (chromosomes) that encode candidate solutions to a problem. These strings are the analog of chromosomes in natural evolution. A fitness function defines the quality of each solution. The GA chooses parent organisms from the population in such a way that the more fit organisms are more likely to be chosen. It applies operators to generate offspring from the parents. The operators are often loosely modeled on biological genetic processes, however they are only very crude abstractions of the processes known and understood to be significant in natural evolution. Most commonly used operators are mutation, which randomly makes a local modification in a chromosome, and crossover, which combines genetic material from two parents. There are many other operators such as inversion, translocation, segregation, duplication, etc, which are sometimes, but not usually, used in GA’s applied to optimization tasks. After performing these operations on individuals selected for reproduction, the GA selects current population members, often those with lower fitness values, to be replaced by the new offspring. The more fit members of the population thus propagate and combine to generate a population with generally increased fitness.

There are many design choices in the construction of a genetic algorithm for a particular problem. On the basis of our previous experience [7-19] and the results of many other investigations, we have found that GA’s can evolve good designs and produce good solutions to many combinatorial problems. In this work, we are going to develop a new construction that is appropriate and effective for solving of the compaction problem in VLSI CAD systems, and bin

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packing and nesting problems which are similar in many respects to compaction. Compaction is the translation of a layout designed from a generic technology (such as CMOS) to a particular fabrication technology’s design rules. It translates the output of the detailed-routing phase into

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mask data and has to convert the circuit elements into the appropriate mask elements and minimize the chip area. The goal is to minimize the area of the layout, while preserving the design rules and not altering the function of the circuit. This goal gives this process the name compaction. Compaction changes the geometry of the topological design to produce as small a layout as possible while enforcing the design rules. In this work, we are going to develop a new design methodology which incorporates some new genetic algorithm ideas that have been developed recently for other problems, plus efficient encoding/decoding methods and useful heuristic layout strategies. This new methodology will contain significant developments in the genetic algorithm approach and provide the basis for efficient suboptimal solution of compaction problems and the related bin packing and nesting problems. Our approach is to develop a hierarchical chromosome representation (HCR) and appropriate genetic operators incorporating various heuristics, and combine them with our "injection island" GA architecture (iiGA).

In this work we investigate the HCR for the layout compaction and bin packing problems. This representation will be designed to preserve building blocks in chromosomes, and the encoding scheme will make genes represent groups. The rationale is that in the problem being considered, "it is the groups of elements and their location which are the meaningful building blocks, i.e. the smallest piece of a solution which can convey information on the expected quality of the solution they are part of. This is crucial; indeed, the very idea behind the GA paradigm is to perform an exploration of the search space, so that promising regions are identified, together with an exploitation of the information thus gathered, by an increased search effort in those regions. If, on the contrary, the encoding scheme does not allow the building blocks to be exploited (i.e. transmitted from parents to offspring, thus allowing a continuous search in their surroundings) and simultaneously to serve as estimators of quality of the regions of the search space they occupy, then the GA strategy inevitably fails and the algorithm performs in fact little more than a random search or naive evolution" [20].

Each group of elements (subgroups) is a piece of a layout -- elements and connections in some area (or bin, for the bin packing problem). At the beginning, when we are given with some initial layout to be compact, each group contains only one element. During the GA process some groups are merged in a new more large group (of a more higher hierarchical level). It is important that all the GA operations now should work not with elements but rather with groups. For the proposed representation, we can use as the decoding mechanism one of the existing silicon compilers [2], or at least the philosophy of this approach. The silicon compiler uses a similar representation of the circuit and finds coordinates for each element (group) and each connection between elements (groups). During this compilation, at each step, two or more groups are merged into one new group, with simultaneous determination of relative coordinates of elements and connections within the group formed. Finally, all groups are merged into one, which represents the whole layout.

The formulation of the compaction problem to be solved is also to be refined, to take into account an additional very important criterion -- circuit performance. The standard compaction problems are one-dimensional (1-D) and two-dimensional (2-D) compaction. The bin packing problems include one-dimensional (1-D), two-dimensional (2-D), and three-dimensional (3-D) bin

packing. Nesting problems are usually 2-D (blank nesting, optimal nesting, or optimal cutting problems).

In the 1-D bin packing problem, the goal is to minimize the number of bins that contain a given set of weights, subject to a limitation of the total weight each bin can contain [21-24]. In the 2-D bin packing problem, the goal is to minimize the area of a single orthogonal bin by packing arbitrary-dimensional rectangular boxes into it [25]. Overlapping of features is not allowed, but there are no constraints on diversity or grouping. In the 3-D bin packing problem, the goal is to minimize the volume of a single orthogonal 3-D bin containing arbitrary dimensional 3-D boxes into it [22,26]. In the 2-D nesting problem, the goal is to maximize the

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number of arbitrary-shaped elements embedded into a single orthogonal bin [27-30]. It is often allowed to turn the elements during the process.

Our methodology is expected to produce good solutions more efficiently than other techniques. This is very important, because the problems are NP-hard. For example, reasonable approximation algorithms for the bin packing problem can only guarantee to be within 22% of optimal [25]. Our algorithm will first initialize a population of chromosomes in which each chromosome represents the layout (compaction, bin packing, or nesting) as a HCR. For this representation, it is possible to develop a modified form of crossover, inversion, translocation, and some other operators not previously applied to this class of problems. The decoding algorithm, based on a silicon compiler, takes any chromosome and forms a legal layout (packing). We expect that our algorithm will advance the state of the art in making genetic operators robust with regard to quantity of data, variation in dimensions of boxes, and variation in the aspect ratio of the bin.

In the 2- and 3-D problems, we initialize a population of chromosomes (solutions) that can be induced by the initial symbolic layout and in this way decrease incredibly the number of possible initial chromosomes. Our algorithm evolves these populations of individuals. Each individual is a string of genes representing some group of elements or subgroups and the corresponding layout that can be obtained after the decoding procedure. New individuals are produced by a stochastic mix of the modification of classic genetic operators: crossover and mutation, specialized for solving hierarchical problems, and some other genetic operations (inversion, translocation, etc.). We propose to explore several alternative heuristic operator/selection strategies, including ones we call "random with pressure" and "random-direct" selection. This will introduce less selection-induced variability. These algorithms will be run using the parallel architectures described below, as already developed by our group.

1.2. Research Tools and Validation

These ideas and objectives will be investigated in the framework of existing commercially available and public domain tools, specifically, Mentor Graphics tools for design, and the GALOPPS ("Genetic ALgorithm Optimized for Portability and Parallelism" System) (a highly

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a very flexible and portable GA system with roots in Goldberg’s SGA, but totally rewritten) already developed by one of the authors and distributed to collaborators in GA research in 10 universities around the world. The use of the Mentor Graphics package will be a useful tie into current CAD technology and is viewed as an essential tool to study the compaction.

Benchmark problems will be assembled for validation of the methodology developed. This set of benchmark problems will come from the literature, from random generation according to realistic characteristics, and from real chips, and will be used for comparison of our methods with existing compaction techniques. Several possible validation paradigms are referenced in Section 2. Specific details of the tasks and methodology which will be used to achieve the goals of this research are provided in Sections 2 and 3 of this proposal.

2. BACKGROUND

2.1. Introduction to Layout Compaction

The layout designer is driven by two conflicting demands. The first is to find the layout with an area as small as possible, in order to minimize manufacturing cost and maximize circuit performance. The second is to create the layout quickly in order to minimize design time and cost. The designer usually develops the layout during two major layout phases [2,31,32]:

1. Topological design, after which the relative placement of components and wires are defined.

2. Geometrical design, after which the geometrical (physical) positions of all the layout elements are defined.

The designer uses different design methodologies to solve the problems of these two phases. Symbolic layout and compaction are two closely related design methodologies that encourage the separation of topological design and geometrical design and help to automate geometrical design [2].

Symbolic layout allows the topological designer to work with the transistors, wires, and cells as primitives, rather than manipulating the individual polygons used in fabrication. A symbolic layout can be drawn as a stick diagram, which uses line segments and components as symbols, or as a layout display with wires and devices drawn as rectangles similar or identical to those used in the layout. The stick diagram may clarify the cell topology, while the layout display gives the designer a feel for the relative sizes of layout elements.

The translation of the output of the detailed-routing phase into mask data must convert the circuit elements into the appropriate mask elements . It should ensure that all design rules are met, while simultaneously minimizing the layout area. This last goal gives this process the name compaction [2,3]. Compaction changes the geometry of the topological design to produce a small layout while enforcing the design rules.

Compactors speed layout design by automating geometric design. The designer gives the compactor a preliminary layout. The compactor moves components and wires in the plane to optimize the layout (the first goal) and to correct it in accordance with the design rules (the second goal). The compactor usually moves subcells only in the plane, preserving the designer’s topology for the cell. The designer can therefore have a great deal of control over the layout without performing the work required to turn a sketch of a layout into a correct, space-optimized design [33].

Compaction performs a translation from the graph domain into mask geometry. Compaction is more than just an optimization problem. Compaction is quite a difficult problem not only from a combinatorial, but also from a systems point of view. Advanced compactors aim at separating combinatorial and technological issues as much as possible. Compaction algorithms use the information from the design-rule database to compute the mask features. The structure of information that the compaction algorithm has to extract from the design-rule database can be quite complicated. It involves not only simple numerical parameters, such as minimum distances between features on different masks, but also connectivity information and electrical information.

Most of the steps in the compaction process are made much simpler by working with a symbolic description of the layout. Combining compaction with symbolic layout creates advantages for the computer-aided design developer as well.

2.2. Basic Definitions and Taxonomy of Compaction

Compaction algorithms may be classified along two basic axes, A and B [3,31,32]:

A describes how components move during compaction;

B covers the algorithms used to position the components.

Algorithms from A can be divided into the following groups.

A.1. One-dimensional (1-D) compaction. In 1-D compaction, only the, say, x coordinates of the mask features are changed. This kind of compaction is also called x compaction (y compaction is defined analogously). The goal is to minimize the width of the layout, while preserving the design rules and not altering the function of the circuit.

So, in 1-D compaction, components are moved only in the x direction or only in the y direction. Most steps of 1-D compaction can be done efficiently. In fact, they can be done with almost linear-time algorithms [3,34]. A few versions of 1-D compaction are NP-hard [2,31,35].

A.2. Two-dimensional (2-D) compaction. In 2-D compaction, both x and y coordinates can be changed simultaneously in order to minimize area, i.e. in 2-D compaction, a single step can move a component in both x and y. In 1-D compaction, the cell is alternately compacted in x any y, while in 2-D compaction components are selected to move as required to improve the layout.

Most versions of 2-D compaction are NP-hard [34,36]. The difficulty of 2-D compaction lies in determining how the two dimensions of the layout must interact to minimize the area. To circumvent the intrinsic complexity of this question, some heuristic are used to decide locally how the interaction is to take place [31-33]. These heuristics are sometimes referred to as 1.5-dimensional compaction [3,35].

Algorithms from B can be divided into the following two major types (groups) [2,3,31,32].

B.1.Constraint-graph algorithms. The constraint graph algorithm describes the required connections and separation rules as linear inequalities, which can in turn be modeled as a weighted, directed graph [36]. The constraint graph is used to find new positions for the components, and the result is applied back to the layout.

B.2. Virtual grid algorithms. The virtual grid algorithm finds the subcell positions by considering the layout to be drawn on a grid; it moves all components on a grid line together so that adjacent virtual grid lines are as close as possible while satisfying all required separations between the symbols on the grid.

Modern designs are modularized hierarchically. An example is the bottom level of the hierarchy. Optimizing leaf cell layout requires awareness of many interacting constraints and complex cost functions. Traditionally, this area of design has been left to human experts. Hierarchical compaction works on cells that are constructed from other cells as well as primitive layout symbols [37,38]. Any of these techniques can be made hierarchical by applying the compaction algorithm to a leaf cell and then using the compacted cell in larger cell. Hierarchical compaction is also called cell assembly. A variety of hierarchical compaction algorithms have been developed for both constraint-graph algorithm and virtual grid algorithm compaction [39-41].

2.3. Algorithms for Compaction.

The general procedure in compacting a cell is shown in Fig. 1 [2,3,31-35]. Each iteration through the loop is a compaction step. First, the layout is analyzed to determine the spacing rules that must be obeyed. Then the layout is compacted to satisfy those constraints. Finally, a wire length minimization algorithm is applied to the compactor’s solution to adjust the positions of non-critical wires in the layout.

Compaction step

Fig. 1. The compaction process.

2.3.1. Constraint-graph 1-D Compaction Algorithms

There are two basic approaches to the constraint-graph 1-D compaction algorithms: compression ridges and graph-based compaction.

Compression-ridge method. This method was pioneered by Akers [42]. In this

approach, a region of empty space is identified in the geometric layout, which separates the layout into a left and a right part. Such a region is subsequently removed by translation of the right part of the layout to the left by as much as the spacing constraints will allow. This step is repeated until no more compression ridges are found.

Disadvantages: This method progresses from the top to the bottom of the layout. This progression amounts to a search through the layout with backtracking (if the compression-ridge method cannot progress further) and thus is computationally complex. Furthermore, it finds only horizontally convex compression ridges.

The key to finding compression ridges is the representation of the empty space in the layout by a directed edge-weighted graph, the tile graph [3,42]. The tile graph is constructed as follows. First the horizontal segments of the contours of the features are extended through the adjacent regions of empty space. This process divides the empty space between the features into rectangular tiles. The tile graph G=(V,E) has a vertex for each tile. Special vertices s and t represent the top and bottom sides of the layout. Vertices representing vertically adjacent tiles are connected with anti-paralleled edges. Thus each anti-paralleled edge pair corresponds to a horizontal segment separating two tiles. The edges are weighted as follows: An edge e pointing downward receives the weight c(e), which is the width of the corresponding tile. An edge pointing upward receives the weight c(e)=inf.

The ordered 1-D compaction can be solved as follows [3,32]:

Step 1: Find a maximum flow from s to t in G.

Step 2: For all edges e from E that point downward, compress the tile corresponding

to e by the amount indicated by the flow along e.

It was shown [3] that the preceding algorithm solves the ordered 1-D compaction with

d(1,1)=0, and p=id and without grouping constraints, as long as the initial layout is legal. In [3] they restrict their attention to compression ridges that correspond to paths in the tile graph. They give an O(n log n) time algorithm for finding such a ridge that allows for the largest decrease in layout width. However, before compaction is complete, many compression ridge may have to be found. The advantages of the compression-ridge method are that the compaction can be broken up into small steps and that it is possible to interleave compaction in both dimensions. This feature is especially important in an environment in which compaction is done interactively, step by step. The Akers compression-ridge method can be applied in a virtual grid setting.

Graph-based compaction. This method turns compaction into a system of linear inequalities that is subsequently solved using shortest-path methods [31,32,43,44]. The compactor’s job is to recognize and enforce spacing rules while minimizing area. Spacing rules can be written as constraints (the Constraint-Graph Model).

The positions of the components, represented as variables in the inequalities, are represented by vertices in the graph. Negative weights on the graph edges indicate that a component is allowed to be to the left of another: C can be at least -d units to the right of W (or d units to the left), and vice versa. The edges representing these constraints form a cycle in which the sum of the weights around the cycle is non-positive.

The graph represents a 1-D compaction because all the variables in the constraints represent positions in the same dimension. The graph includes two artificial vertices, L and U, which represent the lowest and highest positions in the cell, respectively. L is a source of the constraint graph, and U is a sink of the graph. Values assigned to the vertices represent positions of the cells in the dimension of compaction. The minimum L>U distance is determined by the longest path of constraints from L to U. One can translate the longest path problem into a shortest path problem by negating the weights of the edges. One can view

1-D compaction as a linear programming problem:

MINIMIZE U - L

subject to - L + A > 0

- L + B > 0

- A + B > 4

etc.

The objective function of the linear program is U-L, the distance between the lower and upper edges of the graph. The simplex algorithm can perform such a search. The average number of iterations required for the simplex method is very nearly linear in the number of constraints.

Constraint-graph leaf cell compaction

THE SHADOWING ALGORITHM [2,31-33,44,45]. The shadowing algorithm examines the positions of cells to determine what constraints are redundant. As shown in Fig.7, one can imagine a region that contains cells B,C,D,... that must be constrained against cell A in x as falling under a shadow cast from A.

The shadow’s maximum height is the height of A extended by the distance in each direction. If the shadow falls on a cell, that cell must be constrained against A; thus, we must generate a constraint from B, C and D to A.

The shadowing algorithm describes how to generate the constraints on a cell from all the cells below it or to its left. The algorithm keeps the bounds of the shadow’s left edge in a shadow "front". The shadow is a list of edges, each of which has a position in the constraint generation dimension and an upper and lower bound in the opposite dimension. The shadowing algorithm starts with the shadow extending from A to the cell’s left edge, then searches from right to left cells that block portions of the shadow. The function IN SHADOW returns true if a cell’s right edge is in the shadow, which implies that it must both overlap at least one edge in shadow-front in y and also be above that edge in x. If the cell is in the shadow, the algorithm adds a constraint from it to the sink and calls the update shadow procedure to modify the shadow front so that one edge of the shadow coincides with the left edge of the cell that required it. The shadowing algorithm moves from left to right.

There are some difficulties in creating a robust implementation of shadowing. Some components may move through each other during compaction, and the shadow must not be

blocked until all cells that may enter the shadow have been considered.

THE INTERVENING GROUP METHOD [45-47]. This method uses a simple heuristic to eliminate many, but not all, redundant constraints, by remembering a path through the constraint graph that provides a lower bound on the size of relevant constraints.

The first function in intervening group method, CONSTRAINED, returns TRUE if the constraint graph includes a path of constraints between two cells that satisfies the spacing rule between them. The second procedure in the method, GENERATE CONSTRAINT GRAPH, considers each cell from left to right, generating constraints to the i cell from all previously considered cells 1,...,i-1. The speed with which the set of all constraint paths to a cell can be tested and updated allows the algorithm to eliminate redundant constraints very quickly.

PERPENDICULAR-PLANE-SWEEP ALGORITHM (PP shadowing algorithm) [35,37,48-53]. The PP shadowing algorithm uses a scan line to perform a shadowing analysis. X-dimension constraints are generated by a vertical line that is swept from left to right across the layout. In design rule checking, because polygons do not move, only polygons within a fixed distance of the scan line need be checked, but for compaction the scan line must collect arbitrary distance elements. Constraints are generated from one element’s right edge to another’s left edge. A right edge is added to the edge data structure and is checked to find left edges in the data structure against which it must be constrained. A left edge, because it blocks the shadow cast by a right edge, causes right edges to be removed from the data structure. The one-layer version of the PP shadowing algorithm has a time complexity of 0(nlog(n)), where n is the number of rectangles in the layout.

Once physical connectivity and separation constraints have been generated, the constraint set must be solved to find the longest path from L to U. An iterative algorithm is usually used on a constraint graph with cycles. An edge can be used to define an ordering on the vertices it connects. All positive-weight edges are forward, as are any negative-weight edges that satisfy the partial ordering defined by the positive-weight edges; any other edges are backward. In an iteration, the method first applies acyclic-longest-path to find vertex positions that satisfy the forward edges, then it updates that solution to also satisfy the backward edges. The algorithm stops when a forward update/backward update iteration produces no change in the solution. This algorithm is of complexity 0(ve), but because constraint graphs have relatively few large strong components, its average behavior is better.

Virtual grid algorithms

VIRTUAL GRID LEAF CELL COMPACTION [34,39,40,54]. The model simplifies both constraint generation and solution. The virtual grid compaction system determines spacing rules and assign coordinates simultaneously, avoiding the need for an intermediate data structure to describe the constraints.

Compaction starts by assigning the left-most virtual grid the mask position 0. The other virtual grid lines are assigned mask positions in order by looking at the components that have

already been placed. The most commonly used method to find all the constraints that must be satisfied is the most recent layers algorithm.

After both x and y compaction, virtual grid compactors use an xy compaction step to reduce cell size. The 1-D compaction model produces a rectangular barrier around a component. The xy compaction step looks for adjacent components that can be moved closer together and adjusts the positions of their virtual grid lines. The xy compaction step is usually performed simultaneously with the second x or y compaction, since it must look at the same constraints. Because the virtual grid lines determine how components move, only one x and one y compaction step are necessary. Further x or y compaction will not reduce the cell size.

SPLIT-GRID COMPACTION [39,41]. This method allows objects on a virtual grid line to move independently, but does not allow connections with steps. Split-grid compaction produces a layout closer in quality to a constraint-graph algorithm compaction, at the cost of more CPU time than required for simple virtual grid algorithms.

2.3.2. Two-dimensional compaction (2-D compaction)

2-D compaction is an extension of 1-D constraint-graph compaction. As shown in Fig. 2, two cells A and B can have 4 relative positions: B can be above, below, left of, or right of A [36,55].

B(x)>(A(x)+c) (right),

B A(x)>(B(x)+c) (left),

B A B B(y)>(A(y)+c) (above),

B A(y)>(B(y)+c) (below).

(a) Layout. (b) Constraints.

Fig. 2. 2-D Compaction constraints.

In each case, some spacing rule determines the minimum distance required between them. The minimum distance is expressed as a linear inequality. Left-of/right-of placement constraints are expressed as functions of x-dimension variables, and above-below constraints are written in terms of y-dimension variables.

This formulation is a special case of mixed integer linear programming, which works on linear constraints and 0/1 decision variables. A simple insight helps us to discover algorithms for solving these problems -- for any particular setting of decision variables, the selected constraints form two 1-D constraint graphs, one for x and one for y. Solution algorithms choose settings for the decision variables (in effect selecting the relative locations of cells), solve the

resulting 1-D compaction to get the cell positions, and evaluate the quality of the resulting layout.

Kedem and Watanabe [55] used branch-and-bound search to solve a 2-D constraint set. Schlag et al. [36] allow all four possible placements of component pairs. Their algorithm not only searches through all possible compactions of a given planar topology, but also changes the planar topology -- by moving a component from one side of a wire to the other, for instance. One simple way to use this algorithm is to assemble 2-D compacted leaf cells using the 1-D hierarchical compaction algorithms. The limitation of the algorithm is its high computational complexity.

2.3.3. Constraint-graph hierarchical compaction

There are two approaches to constraint-graph hierarchical compaction [15,32,36,55-62]. The first treats subcells as fixed, whereas the second allows subcells to stretch during compaction.

FIXED-CELL HIERARCHICAL COMPACTION. This compaction is used in SPARCS [2,37]. These programs’ model of subcell is the position of its ports and a protection frame used to determine cell-to-cell spacing. The protection frame includes material within the maximum design rule distance on each layer; this material determines the subcell’s separation requirements.

PITCHMATCHING [63-65]. Pitchmatching---stretching cells so they can be connected by abutment---is simply recompacting the cells with additional ports to be at the same positions. Hierarchical compaction with stretchable cells required the compactor to build a more complex model of a subcell than that required for fixed-cell assembly. The ideal model would contain information about how the cell’s contents stretch during compaction -- how the ports can move during compaction -- and information to determine the spacing required between the cell and other cells.

The port abstraction model fully characterizes the stretching behavior of the cell with a much smaller constraint graph that includes only the ports as vertices and flexible protection frame that describes the cells boundary. A port abstraction consists of two constraint graphs, one for x and one for y. The vertices in each graph represent the ports. The edges describe how the ports can move during compaction. The motion of the ports is determined by the components and wires in the cell’s interior. Because cells contain many fewer ports than components and wires, the port abstraction is a greatly simplified model of the cell.

The abstraction’s constraints are determined by computing a subset of the transitive closure of the constraint graph. Because the abstraction contains only port vertices, only the longest path between ports need to be computed. The simplest algorithm for calculating

3

transitive closure is Floyd’s algorithm [66], which takes O(v) steps irrespective the graph’s sparseness. The Eic method [67] insures that each pair of components is constrained by either an x or a y constraint. The longest paths between all pairs of components and wires in the cell are computed; if their ranges conflict in one dimension, then a constraint in the other dimension

is introduced. This method is robust, but costs much more to compute.

Finding the spacing required between two subcells during hierarchical compaction is much more complicated than finding the spacing required between primitive symbols, because components in the subcell can move during compaction. The port abstraction does not contain enough information to determine how cell-to-cell spacing changes as cells stretch, so most systems use worst-case spacing between subcells.

VIRTUAL GRID HIERARCHICAL COMPACTION [68,69]. Most virtual grid systems perform a simple two-level hierarchical compaction. First, all leaf cells are compacted, then all cells are assembled into the final design by a pitchmatching algorithm. During pitchmatching, the mask positions of virtual grid lines in the cells are adjusted to stretch the cells for abutment. Stretching subcells during virtual grid hierarchical compaction is best formulated as a simple constraint problem. The virtual grid compaction of the subcells determines the minimum positions of their pins. The minimum distance of each pin from the base of its subcell can be written as a separation constraint, and a connection between pins can be written as an equality constraint. The resulting graph, after merging nodes connected by equality constraints, is acyclic and can be solved with breadth-first search.

Once the port positions have been found, it can update the positions of the other virtual grid lines for the subcells to maintain the required spacings. The virtual grid model simplifies the determination of cell-to-cell spacing -- the virtual grid allows the compactor to predict how components along the boundary will move. The CAD system PANDA [2,68] performs cell-to-cell spacing in two passes: first, using worst-case spacing, then pushing cells closer together based on a design rule analysis near the boundaries of abutted cells. CAD COORDINATOR [2,69] uses constraint-generation algorithms for leaf cell compaction, which make feasible the compaction very large (10,000) cells.

2.3.4. Wire length minimization [40,41]

The simplest algorithm for wire length minimization works directly on the compaction constraint graph. First the compaction constraints are augmented with constraints that maintain the order of wire endpoints. The augmented graph is solved by repeatedly applying the minimization step. A vertex is chosen that, when moved, will reduce the weighted sum of wire lengths in the cell. The wire length minimization algorithm is described as a linear programming formulation of the problem, and solves it using network programming techniques. Because the optimum solution to a linear program occurs at the simultaneous solution of two or more constraints, the wire length need be checked only at the ends of the vertex’s range. When no vertex can be moved to reduce total weighted wire length, the cell’s wire length is minimal. An algorithm that performs grouping and shearing operations to minimize total wire length has been developed.

INCREMENTAL CELL OPTIMIZATION [32,54,61]. The most incremental cell

optimization methods are jog introduction -- adding a degree of freedom to a connection by changing a wire segment to a z-shaped wire. Let us consider two typical situations for adding a jog. In both cases, allowing the ends of the wire to move separately allows the components to move closer together in y. Automatic jog introduction occurs at the start of a compaction step -- wires are selected for jogging and jogs are added, then constraint generation and solving proceeds normally [70].

Super-compaction [2,31-33] introduced methods for analyzing the critical path to find a small set of jogs sufficient to reduce the cell size. Finding a set of jogs that breaks all critical paths is equivalent finding a cut-set of the critical path graph. Critical path analysis also allows us to consider geometric reorganizations that break the critical path by moving cells to eliminate separation constraints.

2.4. Layout Approaches Based on Genetic Algorithms

In this proposal, we describe various approaches to physical design of VLSI systems based on genetic algorithm methodology, in order to show the utility of the GA approach to layout design.

Partitioning Problem

Let us define the VLSI partitioning problem as follows. We can represent a VLSI system as a hypergraph H=(X,E), where X represents the set of nodes and E represents the set of hyperedges. Let P={P(1),P(2),...,P(l)} be the set of partitions of the H. Let each partition P(i) contain the elements x(i); that is, P(i)={x(1),x(2),...,x(k)} and each x(i) belongs to X. The cost function is the number of hyperedges (connections) between different partitions P(i). Our task is to find a partitioning that minimizes the cost function. Genetic algorithms start with an initial population of partitions (randomly generated or generated by some constructive method). They evaluate this population based on the cost function. Then they select some members of the population and perform genetic operators (crossover, mutation, inversion, translocation and/or others). Applying GA’s allows one to find better solutions for partitioning problems [71,72] than those typically found by other methods.

Placement Problem

The placement problem of standard cells on the VLSI chip is to arrange a given set of standard cells of common or variable height and width on the chip surface. The placement must satisfy criteria of routability of the design. This is usually an objective function which minimizes a function of the wire lengths. Genetic algorithms for placement usually use the following steps: initialization of the population, evaluation, selection, and allocation. Some algorithms use so-called "pressure" techniques. After formation of each generation, they perform local optimization to find the best solutions. Such a procedure helps in finding many local optima, and perhaps also

the global optimum [73,74].

Floorplanning

The floorplan design problem is to arrange a given set of "flexible" modules (with undefined shape and pin assignment) in the plane to minimize the chip area and some function of the wire lengths. In [75], the theory of punctuated equilibria and genetic algorithms are used. They propose a new structure and new model for coding of VLSI systems, as well as a novel genetic strategy and some new genetic operators combining local and random search, by means of which they state that "better" results may be obtained.

Routing

Let us consider two optimization problems, the channel routing problem (CRP) and detailed router problem (DRP) [2,3,76,77]. The CRP is specified by a given rectangular channel with two rows of terminals along its top and bottom sides. The objective of the channel router is to assign each net to a horizontal track (or tracks) in order to minimize the number of such horizontal tracks. Construction of a genetic algorithm for the CRP includes five major steps [76].

1. Select a representation to encode the search space.

2. Determine an appropriate evaluation function and scaling scheme.

3. Determine a selection algorithm.

4. Choose genetic operators.

5. Set control parameters.

A new scheme for selection and some heuristic knowledge-oriented genetic operators combining local and random search improve the performance of the GA in this application. After each generation, the algorithm keeps the best of the previous generation and the newly generated offspring. This process improves chances of finding the optimum routing. Some new results for the DRP are also developed in [77].

Symbolic Layout and Compaction

Symbolic layout and compaction are two closely related design methodologies that encourage the separation of topological design and geometrical design and help to automate geometrical design [2,3]. The translation of the output of the detailed-routing phase into mask data must convert the circuit elements into the appropriate mask features. At the same time, it should ensure that all design rules are met, while minimizing the layout area. In [78], a genetic algorithm for performing the compaction is described. A population consisting of lists of constraints is used with chromosomes differing with respect to the order in which these constraints are applied. We will describe this problem and GA’s for it in more details in the next section.

The GA strategy is a powerful methodology for avoiding premature convergence at local optima.

It can be efficiently used for design of VLSI systems. GA’s are easily parallelized, for increasing speed in massively parallel or distributed computing environments, including low-bandwidth networks of high-performance computing elements. Parallel GA’s hold the promise nearly linear speedup of calculation with the number of processors.

2.5. Bin Packing, Nesting and Compaction Using Genetic Algorithms

2.5.1. 1-D Bin Packing

Problem formulation. Given a finite set of elements E={e,...,e} with associated weights

1n

W={w,...w} such that 0

each partition is at most w* and that N is the minimum.

Let us first consider the classic traditional methods. In [79] they call an algorithm on-line if the numbers in list L are available one at a time and the algorithm has to assign each number before the next one becomes available. Let L = (x(1), ... , x(n)) be a given list of real numbers in (0, 1), and let BIN(1), BIN(2), ... be an infinite sequence of bins, each of unit capacity. The BPP is to assign each x(i) to a unique bin, with the sum of numbers in each bin not exceeding one, such that the total number of bins used is minimum. It is shown that any on-line algorithm S must have r(S) > 3/2, where r(S) = S(L)/L*, S(L) is the number of bins used by S, and L* denotes the minimum number of bins needed.

Commonly Used Heuristics

FIRST-FIT (FF) algorithm (an on-line algorithm).

Given a list L = (x(1), ... , x(n)), the FF assigns x(j) sequentially, for j = 1, 2, ... , n to BIN(i) with the smallest i whose current content does not exceed (1-x(j)). The measure r(FF) = 17/10. The FF algorithm is an O(n log n)-time algorithm. It is shown in [79] that in generalized, d-dimensional bin packing, any O(n log n)-time algorithm S must have r(s) > d.

FIRST-FIT-DECREASING (FFD) algorithm (NOT on-line).

Given a list L = (x(1), ... , x(n)), the FFD first sorts the x(j)’s into decreasing order, and then performs FF. FFD has a running time O(n log n). r(FFD) = 11/9.

REFINED-FIRST-FIT (RFF) algorithm.

Any element x(j) in a list L will be called an A-piece, B(1)-piece, B(2)-piece, or X-piece if x(j) is in the interval (1/2, 1]-A, (2/5, 1/2]-B(1), (1/3, 2/5]-B(2), or (0, 1/3]-X, respectively. Before packing, they [79] divide the set of all bins into 4 infinite classes. Let m from {6, 7, 8, 9} be a fixed integer. Suppose the first j-1 numbers in list L have been assigned: they process the next number x(j) according to the rules:

Director 疑难解答

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件制作案例教程/刘庆全，时道波编.-北京：清华大学出版社，2012.1

二、课程教学目标与基本要求 本课程的核心目标是： 1.Photoshop软件基本功能，使用Photoshop制作课件母版、背景 以及处理幻灯片中所用图片的方法与技巧。 2.商务运营、教学课件、生活娱乐三大类课件制作方法与技巧。 3.不同风格课件的版式布局与整体配色的方法。 4.幻灯片中酷炫动画演绎以演示文稿交互效果的实现。 本课程的基本要求是让学生掌握PowerPoint这一教学工具软件 平台的使用，通过本门课程的教学使学生能熟练掌握PowerPoint软 件各项功能、了解Photoshop图像处理的基本功能以及课件制作的各 种方法与技巧，通过本门课的学习和训练，学生能够熟练运用计算机 制作多媒体课件，为以后从事小学教育工作、结合小学教学实际利用 计算机辅助教学做准备。 三、课程教学条件 机房 四、课程教学内容与学时安排 第一部分平面设计理念 本部分主要简单介绍平面设计的概念、术语以及平面设计的方法、技巧,包括以下内容: 1.1平面设计的概念、术语 1.2平面设计的方法、技巧 通过这一部分的学习，学生对平面设计有一个初步的理解，因为课件制作的版式布局、色彩搭配等很多内容与平面设计是相通的，这样可为进一步学习课件制作后续内容打好基础。

c语言循环语句和循环控制例题解析

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interview常见问题

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“Developer Settings(开发人员设置)”复选框已被选中。 单击侧边栏中的“Reset(重置)”。 仔细检查连接盒的USB线是否已经从PC上拔下。单击“Remove all SteamVR Devices(删除所有SteamVR设备)”，然后在弹出窗口中单击“Yes(是)”。 退出SteamVR，将连接盒插回PC，然后重启SteamVR。 如果你尝试了上述每个修复步骤，但问题尚未修复，原因可能是你的USB芯片组出现了问题。请查阅Steam支持页面，了解关于兼容USB芯片组的进一步说明。 2、(Error 113) Path registry not writable/(错误 113)路径注册表无法写入 这通常是由于缺乏正确的安装权限。你需要在Windows中更改权限。 可能的解决方案： 右键单击Windows资源管理器，然后选择要编辑权限的文件夹。 单击“Properties(属性)”。 单击“Security(安全)”选项卡。 检查“Group of usernames(用户名组)”复选框中列出的名称。如果你使用的帐户未显示，请单击“Add(添加)”并键入需要添加的用户名称。如果用户名已经显示，请跳过此步骤。 请在“Permissions for User of Group(用户组权限)”中点击“Allow or Deny (允许或拒绝)”。如果想解决Vive中的错误 113，你需要选择允许。(Error 200) Driver failed/(错误 200)驱动程序失败 此错误消息表示OpenVR驱动程序失败。 可能的修复方案： 果你将文件或文件夹添加到SteamVR的drivers director，这时将其删除应该可以解决问题。 如果没有，你可能没有在用户目录中写入适当的权限。这时你需要在Windows 中更改权限： 右键单击Windows资源管理器，然后选择要编辑权限的文件夹。 单击“Properties(属性)”。 单击“Security(安全)”选项卡。 检查“Group of usernames(用户名组)”复选框中列出的名称。如果你使用的帐户未显示，请单击“Add(添加)”并键入需要添加的用户名称。如果用户名已经显示，请跳过此步骤。 请在“Permissions for User of Group(用户组权限)”中点击“Allow or Deny (允许或拒绝)”。如果想解决Vive中的错误 200，你需要选择允许。3、(Error 206) Driver not calibrated/(错误 206)驱动程序未校准 错误 206表示SteamVR无法加载头显的校准。要解决此问题，你需要重置头显，强制驱动程序重新安装。 可能的修复方案： 拔下头显插头。 打开SteamVR，依次选择“Settings(设置)” > “Reset(重设)” ，然后单击“Remove all SteamVR devices(删除所有SteamVR设备)。稍等片刻。 重新插入头显，等待驱动程序安装。

C语言 个关键字九种控制语句 种运算符

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Linux常见问题及解决错误

1.locate无法查询文件，提示locate:can no stat () `/var/lib/mlocate/mlocate.db':no such file or director 解决方法： 使用updatedb命令更新一下数据库即可 2.修改httpd.conf中的监听端口为8081，然后重启httpd服务，提示错误 解决办法： 1.设置色Linux的模式为宽容模式(permissive) 1）查看selinux的模式：getenforce 2）查看selinux的政策（Policy）：sestatus 3）修改selinux的模式：setenforce a)0：转成permissive宽容模式； b)1：转成enforcing强制模式； 4）重启httpd服务 5）如果防火墙没有开放TCP8081端口，需要使用iptables添加端口准入 6）重启失效，需要重新设置，或者将SELinux设置为永久宽容模式，但是不建议这样设置，于系统造成不安全

2.设置SELinux中允许http的服务的允许端口为需要的端口---待完善 3.重启http的服务提示Starting httpd: httpd: Could not reliably determine the server's fully qualified domain name, using localhost.localdomain for ServerName 解决办法：----截图另做 2）重启httpd服务 #service httpd restart 解决办法： 由于SELinux上下文设置出错，不允许共享文件 1）关闭selinux 2）修改上下文 5.FTP下载失败文件失败 1）从windows上的cmd中使用ftp连接到linux服务器中，然后可以正常下载所需文件；2）从linux上使用ftp命令连接到linux服务器中，可以正常切换目录，但是使用ls命令时不能正常显示该目录下所有文件，提示错误信息是“ftp: connect: No route to host”； 3）检查ftp服务状态，两部linux服务器的ftp服务都已开启，且端口21都是出于listen状态； 4）检查防火墙状态，ftp客户端一方的服务器防火墙关闭，目标服务器防火墙打开； 5）把防火墙关闭后，linux ftp客户端可以正常从目标服务器中下载所需文件

c语言：流程控制语句

流程控制 ======= 知识点： if-else语句使用 switch语句使用 break使用 正常情况下，程序从main函数开始，一句一句，自上而下执行每一条语句。 一些语句可以控制，修改程序的运行流程，称为流程控制语句。 一、条件判断语句if if(表达式){ 语句 } 如果……就…… 【逻辑】当程序执行到if语句，首先计算表达式的值，如果为真，执行语句。如果为假，不执行、跳过语句。 【逻辑假设】 if（表达式）{ 语句1 }else{ 语句2 } 如果……就……否则…… 【逻辑】当程序执行到if else语句，首先计算表达式的值，如果为真，执行语句1，不执行语句2。 如果为假，执行语句2，不执行语句1。 【逻辑二择】 例，明天考试，80分以下把代码抄写五遍，80分以上奖励棒棒糖一枚。 if(表达式1){ 语句1 }else if（表达式2）{ 语句2 }else if（表达式3）{ 语句3 } else{ 语句4 } 如果（表达式1成立），那么执行语句1 否则如果（表达式2成立），那么执行语句2 …… 否则，执行语句4。

【逻辑】当程序执行到该结构，计算机表达式1，如果成立，执行语句1，跳出整个结构。如果表达式2为假，计算表达式2，如果为真，执行语句2，跳出结构体。直到表达式2为假，计算表达式3，依次类推，如果表达式都不成立，执行else下的语句。 如果不需要（即所有表达式都不成立，什么都不做），可以不写else。else if的数量根据需求，任意增减，没有限制。 【注】在if else if结构中，每个else都是对前面每个表达式的否定。 【逻辑多择】 嵌套的if-else语句 我们可以在if语句内嵌套if语句，同样，我们也可以在if语句内嵌套if-else语句，在if-else 语句内嵌套if语句，以及在if-else语句内嵌套if-else语句。 int x; scanf(“%d”,&x); if(x<0){ printf(“error!\n”); }else{ if(x%2) printf(“jishu\n”); else printf(“oushu\n”); } 练习 1、使用if else if，模拟下述分段函数。 x^2+1(x<0) y= 2*x+6 (0<=x<=5) 3*x-1 (x>5) 2、输入一个字符，如果是大写字母，转成小写字母。如果是小写字母，转成大写字母，如果不是字母，不变输出。 3、输入一个字符，判断这个字符是表示大写字母，小写字母，数字字符，还是其他。A a 9 % 二、逻辑跳转语句goto switch 1、goto语句 无条件跳转到指定标号的位置，向下执行。 goto 语句标号 printf(“————————1\n”); printf(“————————2\n”); goto A; //跳转到标号的位置 printf(“————————3\n”); printf(“————————4\n”); //标号的名字是标识符，这里使用大写是为了和变量相回避。 A: //这是一个标号，是一个位置的标记，本身是什么都不做。 printf(“————————5\n”); B:

ODS_ETL常见问题分析及解决方法

ODS_ETL常见问题分析及解决方法1II常见抽取错误及处理方法

1.1 SQL3015N 问题描述： 问题分析：源系统删除提供给II抽取用的授权用户问题解决：联系源系统人员，增加指定授权用户1.2 SQL3015N 问题描述：

问题分析：源系统表结构发生变更，导致NICKNAME不可用 问题解决：通知ODS相关人员，重建NICKNAME 1.3 SQL1822N 问题描述： SQL1822N Unexpected error code "-805" received from data source "BANKA". Associated test and tokens are "SQL0805N Package "NULLID .SYSSN200" was not found .SQ".SQLSTATE=560BD 问题分析：II在连接400前需要进行绑定 问题解决： db2 bind @db2ubind.lst blocking all grant public db2 bind @db2cli.lst blocking all grant public db2 bind db2schema.bnd blocking all grant public

1.4 SQL3022N 问题描述： db2 "EXPORT TO /gpfs/file/output/20081121/CP/NICK_N_CP_APEDU.tmp OF DEL LOBS TO /gpfs/file/output/20081121/CP/LOBFILE a_cp_apedu_20081121 MODIFIED BY coldel0x03 nochardel datesiso LOBSINFILE MESSAGES /gpfs/file/output/20081121/CP/NICK_N_CP_APEDU.msg SELECT * FROM NICK_N_CP_APEDU where 1=1 WITH UR" SQL3022N An SQL error "-204" occurred while processing the SELECT string in the Action String parameter.1024 export NICK_N_CP_APEDU 出错 问题解决： 1）复制日志中的SELECT语句直接在IIDB上执行，即可看见详细的错误信息，一般为配置表中的筛选条件出错。 2）编辑抽取配置表中相应信息 3）重新调度作业，启动作业。 2数据已抽取，但对应作业未运行 问题现象：作业流未运行完，同时既没有作业在Running没有作业Failed，这时就要查看该作业流下哪个表还未运行，通过作业流总体监控可以看到数据日期下哪些作业还未运行，如下图所示，点击作业流名称即可

课件制作课程标准定稿版

课件制作课程标准精编 W O R D版 IBM system office room 【A0816H-A0912AAAHH-GX8Q8-GNTHHJ8】

《课件制作》课程标准 一、课程基本信息 课程代码 06660213035 课程类别必修课 适应专业初等教育专业 先修与后续课程先修课是计算机应用基础无后续课程 课程简介多媒体教学课件制作技能是初等教育学生必须掌握的基本技能之一，因而在专业课程体系中占有较为重要的位置，是具有专业特色、理论与实 践结合较为紧密的课程之一，通过该课程的学习学生既能掌握制作多媒 体课件的技术与技能，又能提高教学能力。PowerPoint功能强大，使用 非常简单，是教师首选的多媒体课件制作软件，因此本课程中以 PowerPoint为软件平台进行教学。 课程总学时 64学时 课程总学分 2学分 授课教材（教材名称、教材着<编>者，出版社，出版日期，教材获奖或推荐情况简介） PowerPoint从入门到精通/刘海燕，施教芳编着.-北京:中国铁道出版社，2011.4 参考书目（书目名称、着<编>者，出版社，出版日期）多媒体课件制作案例教程/刘庆全，时道波编.-北京：清华大学出版社，2012.1 二、课程教学目标与基本要求 本课程的核心目标是：

1.Photoshop软件基本功能，使用Photoshop制作课件母版、背景以及处理幻灯片中 所用图片的方法与技巧。 2.商务运营、教学课件、生活娱乐三大类课件制作方法与技巧。 3.不同风格课件的版式布局与整体配色的方法。 4.幻灯片中酷炫动画演绎以演示文稿交互效果的实现。 本课程的基本要求是让学生掌握PowerPoint这一教学工具软件平台的使用，通过本 门课程的教学使学生能熟练掌握PowerPoint软件各项功能、了解Photoshop图像处理的 基本功能以及课件制作的各种方法与技巧，通过本门课的学习和训练，学生能够熟练运用 计算机制作多媒体课件，为以后从事小学教育工作、结合小学教学实际利用计算机辅助教 学做准备。 三、课程教学条件 机房 四、课程教学内容与学时安排 第一部分?平面设计理念 本部分主要简单介绍平面设计的概念、术语以及平面设计的方法、技巧,包括以下内容: 1.1平面设计的概念、术语 1.2平面设计的方法、技巧 通过这一部分的学习，学生对平面设计有一个初步的理解，因为课件制作的版式布局、色彩搭配等很多内容与平面设计是相通的，这样可为进一步学习课件制作后续内容打好基础。 本部分的主要教学内容（教学时数安排：4学时）： 第二部分 PowerPoint软件讲解

PPT多媒体课件制作图文教程

PPT多媒体课件制作图文教程PowerPoint是Microsoft公司Office系列办公组件中的幻灯片制作软件，由于它和其它Office软件一件，容易使用，界面友好，因此在设计制作多媒体课件中，应用也很广泛。 1.1 PowerPoint的主要特点 （1）"幻灯片"式的演示效果 PowerPoint制作的多媒体课件可以用幻灯片的形式进行演示，非常适用于学术交流、演讲、工件汇报、辅助教学和产品展示等需要多媒体演示的场合。因此PowerPoint文件又常被称为"演示文稿"或"电子简报"。 （2）强大的多媒体功能 PowerPoint能很简便地将各种图形图像、音频和视频素材插入到课件中，使课件具有强大的多媒体功能。 1.2 操作界面

1.3 视图 PowerPoint共有五种视图： （1）幻灯片视图即当前课件页的编辑状态，视图的大小可以通过"常用"工具栏上的比例栏进行调整； （2）大纲视图主要用于输入和修改大纲文字，当课件的文字输入量较大时用这种方法进行编辑较为方便； （3）幻灯片浏览视图是一种可以看到课件中所有幻灯片的视图，用这种方式，可以很方便地进行幻灯片的次序调整及其他编辑工作； （4）备注页视图主要用于作者编写注释与参考信息； （5）幻灯片放映视图即当前幻灯片的满屏放映状态。

2 基本操作 2.1 创建课件页 （1）新建文稿 启动PowerPoint，在"新建演示文稿"对话框中选择"空演示文稿"。 （2）选择版式 在选取版式对话框中选择"空白版式"。

（3）输入文本 选择"插入"菜单中"文本框"中"文本框"命令后，在编辑区拖动鼠标，绘出文本框，然后输入相应文字。 （4）格式化文本 与其它字处理软件（如WORD）相似。 （5）调整文本位置 通过调整文本框的位置来调整文本的位置。先选中要调整的文本框，使其边框上出现8个控制点，然后根据需要拖动控制点，文本框随之改变大小。当鼠标指针放在文本框边上的任何不是控制点的位置时，鼠标指针附带十字箭头，这时拖动鼠标可调整文本框的位置。

面试中的常见英文问题

Q：Can you sell yourself in two minutes？Go for it. 你能在两分钟內自我推荐吗？大胆试试吧！ A：With my qualifications and experience, I feel I am hardworking, responsible and diligent in any project I undertake. Your organization could benefit from my analytical and interpersonal skills. 依我的资格和经验，我觉得我对所从事的每一个项目都很努力、负责、勤勉。我的分析能力和与人相处的技巧，对贵单位必有价值。 Q：Give me a summary of your current job deion. 对你目前的工作，能否做个概括的说明。 A：I have been working as a computer programmer for five years. To be specific, I do system analysis, trouble shooting and provide software support. 我干了五年的电脑程序员。具体地说，我做系统分析，解决问题以及软件供应方面的支持。 Q：Why did you leave your last job？ 你为什么离职呢？ A：Well, I am hoping to get an offer of a better position. If opportunity knocks, I will take it. 我希望能获得一份更好的工作，如果机会来临，我会抓住。 A：I feel I have reached the "glass ceiling" in my current job. I feel there is no opportunity for advancement. 我觉得目前的工作，已经达到顶峰，即沒有升迁机会。 Q：How do you rate yourself as a professional？ 你如何评估自己是位专业人员呢？ A：With my strong academic background, I am capable and competent. 凭借我良好的学术背景，我可以胜任自己的工作，而且我认为自己很有竞争力。 A：With my teaching experience, I am confident that I can relate to students very well. 依我的教学经验，我相信能与学生相处的很好。 Q：What contribution did you make to your current (previous) organization？ 你对目前/从前的工作单位有何贡献？

多媒体课件制作课程教案

梧州学院教师教案 （2017～2018学年第1学期） 课程名称：多媒体课件制作 英文名称： Design and production of courseware 课程类别：专业限定选修学分： 2 课程编号： (2017-2018-1)-XZ 94 总学时：34 理论学时：24 实验学时：12 授课班级：15英语1班,15英语2班 使用教材：让课堂更精彩：精通PPT课件设计与制作任课教师：韦德华职称: 实验师 所在单位：梧州学院院系(部处) 师范学院 教务处制

教案填写说明 教案按每一大节课进行编写，其进度应与授课计划相同。教案可以是打印稿也可以是手写稿。有关部分填写要求如下： 1、课程类别（封面）：包括公共课、学科基础课、专业基础课、专业方向课、实践性教学环节、实验课、专业任选课、公选课。 2、课堂教学目的及要求：本大节课（本次课）的教学目的及要求。 3、课堂教学重点及难点：指根据教学大纲要求，确定课堂教学知识信息的重点、难点。 4、教学过程：这是整个教案的主体部分，既体现出教学活动的逻辑程序，又要划分出若干环节或步骤，并考虑到它们的时间分配、具体方法的应用，相互间的衔接、过渡，以及教学过程与板书的协调等等，充分反映教师教学设计思想，体现教师的教学经验和风格。 5、教学方法及手段：指举例讲解、多媒体讲解、模型讲解、实物讲解、挂图讲解、音像讲解等。 6、课后作业与思考题：指本大节课（本次课）结束后需要布置的作业与思考题。 7、课后小结：课后自我总结分析是对课程教学中教学环节的设计、教学重点难点的把握、教学方法的应用、师生双边活动的设计及教学效果等情况的总结与分析，为以后的教学提供经验与参考。

c语言中常见的7种条件编译语句

C语言中常见7中条件编译语句 网址出处：https://www.doczj.com/doc/d72085843.html,/huangyiyun/article/details/4364964； https://www.doczj.com/doc/d72085843.html,/language/20090806/66164.html

预处理过程扫描源代码，对其进行初步的转换，产生新的源代码提供给编译器。可见预处理过程先于编译器对源代码进行处理。 在C语言中，并没有任何内在的机制来完成如下一些功能：在编译时包含其他源文件、定义宏、根据条件决定编译时是否包含某些代码。要完成这些工作，就需要使用预处理程序。尽管在目前绝大多数编译器都包含了预处理程序，但通常认为它们是独立于编译器的。预处理过程读入源代码，检查包含预处理指令的语句和宏定义，并对源代码进行响应的转换。预处理过程还会删除程序中的注释和多余的空白字符。 预处理指令是以#号开头的代码行。#号必须是该行除了任何空白字符外的第一个字符。#后是指令关键字，在关键字和#号之间允许存在任意个数的空白字符。整行语句构成了一条预处理指令，该指令将在编译器进行编译之前对源代码做某些转换。下面是部分预处理指令： 指令用途 #空指令，无任何效果 #include包含一个源代码文件 #define定义宏 #undef取消已定义的宏 #if如果给定条件为真，则编译下面代码 #ifdef如果宏已经定义，则编译下面代码 #ifndef如果宏没有定义，则编译下面代码 #elif如果前面的#i f给定条件不为真，当前条件为真，则编译下面代码 #endif结束一个#if……#else条件编译块 #error停止编译并显示错误信息 一、文件包含 #include预处理指令的作用是在指令处展开被包含的文件。包含可以是多重的，也就是说一个被包含的文件中还可以包含其他文件。标准C编译器至少支持八重嵌套包含。 预处理过程不检查在转换单元中是否已经包含了某个文件并阻止对它的多次包含。这样就可以在多次包含同一个头文件时，通过给定编译时的条件来达到不同的效果。例如： #defineAAA #include"t.c" #undefAAA #include"t.c" 为了避免那些只能包含一次的头文件被多次包含，可以在头文件中用编译时条件来进行控制。例如： /*my.h*/ #ifndefMY_H #defineMY_H …… #endif 在程序中包含头文件有两种格式：

director 常见问题解答

director常见问题整理 Q: 为什么用MX2004打包后会显示标题栏？ A：把display template中的titlebat options里的选项都取消就可以了。 Q：如何在DR中打开word文件 A：1，在d内打开须使用activex 2，在d外打开调用word程序打开即可 Q：怎样实现让用户选择不同的背景音乐？ A：on mouseUp me,7v@ fileobj=new(xtra "fileio")~M+Hhf fileobj.setFilterMask("all file, *.*,mp3,*.mp3,wave, *.wav")i filename=displayOpen(fileobj)^|kHUb if filename="" or filename=void then exitU9 closefile(fileobj) jhI sound playFile 2, string(filename) end Q：请问怎么给mpg视频加遮照？ A：1，利用open widndow 做视频遮照 2，用MPEG advance xtra 插件，在属性窗口中把 playback opitions 下的DTS取消了，就可以了，然后就在视频之上的通道里放你遮的图片即可 Q：怎么检测本机是否连接到intel网上？ A：WinSocket Xtra Ad可以实现，说明： WinSocket Xtra 是一套Sprite Xtra，一共有三个，分别为 TCPServer.X32,TCPClient.X32和UDPSocket.X32。TCPServer.X32是服务器端xtra，TCPClient.X32是客户端xtra，采用 Tcp/ip协议。互相配套用于网络信息传递，可以构建类似聊天室，多人连线游戏。UDPSocket.X32采用 UDP 协议。独立用于网络信息传递，也可以构建类似聊天室，多人连线游戏。 Q：flash动画导到dr后声音和动画不同步怎么解决？ A：使用线索点，最好调好以后把它锁定。 Q：如何检测用户是否安装quicktime，若无就提示安装？ A：on exitframe me if quicktimeversion()<5.0 then open the moviepath@"quicktime\fullinstallercn.exe“ halt() else go "start" end if end Q：为什么发布成exe文件后视频不能正常播放？

多媒体课件制作课程教案

梧州学院 教师教案 （2017～2018学年第1学期） 课程名称：多媒体课件制作 英文名称： Design and production of courseware 课程编号：(2017-201 8-1)-XZ94 11007-030 04-1课程类别：专业限定 选修 学分：2 总学时：34理论学时：24实验学时：12授课班级：15英语1班,15英语2班 使用教材：让课堂更精彩：精通PPT课件设计与制作 AHA12GAGGAGAGGAFFFFAFAF

任课教师：韦德华职称:实验师所在单位：梧州学院院系(部处)师范学院 教务处制 AHA12GAGGAGAGGAFFFFAFAF

教案填写说明 教案按每一大节课进行编写，其进度应与授课计划相同。教案可以是打印稿也可以是手写稿。有关部分填写要求如下： 1、课程类别（封面）：包括公共课、学科基础课、专业基础课、专业方向课、实践性教学环节、实验课、专业任选课、公选课。 2、课堂教学目的及要求：本大节课（本次课）的教学目的及要求。 3、课堂教学重点及难点：指根据教学大纲要求，确定课堂教学知识信息的重点、难点。 4、教学过程：这是整个教案的主体部分，既体现出教学活动的逻辑程序，又要划分出若干环节或步骤，并考虑到它们的时间分配、具体方法的应用，相互间的衔接、过渡，以及教学过程与板书的协调等等，充分反映教师教学设计思想，体现教师的教学经验和风格。 5、教学方法及手段：指举例讲解、多媒体讲解、模型讲解、实物讲解、挂图讲解、音像讲解等。 6、课后作业与思考题：指本大节课（本次课）结束后需要布置的作业与思考题。 7、课后小结：课后自我总结分析是对课程教学中教学环节的设计、教学重点难点的把握、教学方法的应用、师生双边 AHA12GAGGAGAGGAFFFFAFAF