f IN ? Input Frequency ? MHz
60
70
80
90
100
050100150200250300
S
F
D
R
?
d
B
c
G001
f IN ? Input Frequency ? MHz
70
71
72
73
74
75
76
77
78
050100150200250300
S
N
R
?
d
B
F
S
G002
ADS5484
ADS5485
https://www.doczj.com/doc/c610157299.html,...............................................................................................................................................SLAS610C–AUGUST2008–REVISED OCTOBER2009 16-Bit,170/200-MSPS Analog-to-Digital Converters
Check for Samples:ADS5484ADS5485
FEATURES APPLICATIONS
?Wireless Infrastructure
?170/200-MSPS Sample Rates
?Test and Measurement Instrumentation
?16-Bit Resolution,78dBFS Noise Floor
?Software-Defined Radio
?SFDR=95dBc
?Data Acquisition
?On-Chip High Impedance Analog Buffer
?Power Amplifier Linearization
?Efficient DDR LVDS-Compatible Outputs
?Radar
?Power-Down Mode:70mW
?Medical Imaging
?Pin-for-Pin with ADS5483/5482/5481,
135/105/80-MSPS ADCs
?QFN-64PowerPAD?Package
(9mm×9mm footprint)
?Industrial Temperature Range:
–40°C to85°C
DESCRIPTION
The ADS5484/ADS5485(ADS548x)is a16-bit family of analog-to-digital converters(ADCs)that operate from both a5-V supply and3.3-V supply while providing LVDS-compatible digital outputs.The ADS548x integrated analog input buffer isolates the internal switching of the onboard track and hold(T&H)from disturbing the signal source while providing a high-impedance input.An internal reference generator is provided to simplify the system design.Internal dither is available to improve SFDR.These devices are drop-in compatible to the ADS5483/5482/5481,creating a pin-compatible family from80–200MSPS.Designed for highest total ENOB, the ADS548x family has outstanding low noise performance and spurious-free dynamic range.
The ADS548x family is available in a QFN-64PowerPAD package.The devices are built on Texas Instruments complementary bipolar process(BiCom3)and are specified over the full industrial temperature range(–40°C to 85°C).
SFDR SNR
vs vs
INPUT FREQUENCY INPUT FREQUENCY
Please be aware that an important notice concerning availability,standard warranty,and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.Copyright?2008–2009,Texas Instruments Incorporated Products conform to specifications per the terms of the Texas
ADS5485 is Not Recommended for New Designs
ADS5484ADS5485
SLAS610C –AUGUST 2008–REVISED OCTOBER https://www.doczj.com/doc/c610157299.html,
This integrated circuit can be damaged by ESD.Texas Instruments recommends that all integrated circuits be handled with appropriate precautions.Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure.Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
Table 1.PACKAGE/ORDERING INFORMATION (1)
SPECIFIED PACKAGE PACKAGE ORDERING TRANSPORT PRODUCT
PACKAGE-LEAD
TEMPERATURE
DESIGNATOR
MARKING NUMBER MEDIA,QUANTITY RANGE ADS5484IRGCT Tape and reel,250ADS5484QFN-64RGC –40°C to 85°C AZ5484ADS5484IRGCR Tape and reel,2000ADS5485IRGCT Tape and reel,250ADS5485QFN-64
RGC
–40°C to 85°C
AZ5485
ADS5485IRGCR
Tape and reel,2000
(1)
For the most current product and ordering information see the Package Option Addendum located at the end of this document,or see the TI website at https://www.doczj.com/doc/c610157299.html,..
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ADS5485 is Not Recommended for New Designs
ADS5484 ADS5485 is Not Recommended for New Designs
ADS5485 https://www.doczj.com/doc/c610157299.html,...............................................................................................................................................SLAS610C–AUGUST2008–REVISED OCTOBER2009
ABSOLUTE MAXIMUM RATINGS(1)
Over operating free-air temperature range,unless otherwise noted.
ADS5484,ADS5485UNIT AVDD5to GND6V Supply voltage AVDD3to GND5V DVDD3to GND5V
AC signal.Valid when AVDD5is within normal operating range.When
AVDD5is off,analog inputs should be<0.5V.If not,the protection
Analog input to GND diode between the inputs and AVDD5becomes forward-biased and–0.3to(AVDD5+0.3)V could be damaged or shorten device lifetime(see Figure30).Short
transient conditions during power on/off are not a concern.
Analog INP to INM DC signal±4V Valid when AVDD3is within normal operating range.When AVDD3is
off,clock inputs should be<0.5V.If not,the protection diode between
Clock input to GND the inputs and AVDD3becomes forward-biased and could be–0.3to(AVDD3+0.3)V damaged or shorten device lifetime(see Figure37).Short transient
conditions during power on/off are not a concern.
CLKP to CLKM±2.5V Digital data output to GND–0.3to(DVDD3+0.3)V Digital data output plus-to-minus±1V Operating temperature range–40to85°C Maximum junction temperature150°C Storage temperature range–65to150°C ESD,human-body model(HBM)2kV (1)Stresses above these ratings may cause permanent damage.Exposure to absolute maximum conditions for extended periods may
degrade device reliability.These are stress ratings only,and functional operation of the device at these or any other conditions beyond those specified is not implied.Kirkendall voidings and current density information for calculation of expected lifetime are available upon request.
THERMAL CHARACTERISTICS(1)
PARAMETER TEST CONDITIONS TYP UNIT Soldered thermal pad,no airflow20 RθJA
Soldered thermal pad,150-LFM airflow16
°C/W RθJC Thermal resistance from the junction to the package case(top)7
RθJP Thermal resistance from the junction to the thermal pad(bottom)0.2
(1)Using49thermal vias(7×7array).See PowerPAD Package in the Application Information section.
Copyright?2008–2009,Texas Instruments Incorporated Submit Documentation Feedback3
ADS5484
ADS5485 is Not Recommended for New Designs
ADS5485
SLAS610C–AUGUST2008–REVISED https://www.doczj.com/doc/c610157299.html, RECOMMENDED OPERATING CONDITIONS
ADS5484,ADS5485
UNIT
MIN NOM MAX
SUPPLIES
AVDD5Analog supply voltage 4.755 5.25V AVDD3Analog supply voltage 3.15 3.3 3.45V DVDD3Output driver supply voltage3 3.3 3.6V ANALOG INPUT
Differential input voltage range3V PP VCM Input common-mode voltage 3.1V DIGITAL OUTPUT(DRY,DATA)
Maximum differential output load(parasitic or intentional)5pF
Differential output resistance100?CLOCK INPUT(CLK)
Max CLK input sample rate(sine wave)10Rated MSPS
Clock Clock amplitude,differential sine wave(see Figure39) 1.55V PP
Clock duty cycle(see Figure44)45%50%55%
T A Operating free-air temperature–40+85°C ELECTRICAL CHARACTERISTICS(ADS5484,ADS5485)
Typical values at T A=25°C:minimum and maximum values over full temperature range T MIN=–40°C to T MAX=85°C, sampling rate=max rated,50%clock duty cycle,AVDD5=5V,AVDD3=3.3V,DVDD3=3.3V,–1dBFS differential input, and3-V PP differential clock,unless otherwise noted.
ADS5484ADS5485
PARAMETER TEST CONDITIONS UNIT
MIN TYP MAX MIN TYP MAX Clock rate170200MSPS
Resolution1616Bits ANALOG INPUTS
Differential input voltage range33V PP
Self-biased;see VCM
Analog input common-mode voltage 3.1 3.1V
specification below
Input resistance(dc)Each input to VCM10001000?
Each input to GND(unsoldered
Input capacitance 3.5 3.5pF
package)
Analog input bandwidth(–3dB)730730MHz
Common-mode signal
CMRR Common-mode rejection ratio6565dB
70MHz(see Figure26)
INTERNAL REFERENCE VOLTAGE
VREF Reference voltage 1.2 1.2V
Analog input common-mode voltage
VCM With internal voltage reference 2.9 3.1 3.3 2.9 3.1 3.3V reference output
VCM temperature coefficient-1-1mV/°C
4Submit Documentation Feedback Copyright?2008–2009,Texas Instruments Incorporated
ADS5484 ADS5485 is Not Recommended for New Designs
ADS5485 https://www.doczj.com/doc/c610157299.html,...............................................................................................................................................SLAS610C–AUGUST2008–REVISED OCTOBER2009 ELECTRICAL CHARACTERISTICS(ADS5484,ADS5485)(continued)
Typical values at T A=25°C:minimum and maximum values over full temperature range T MIN=–40°C to T MAX=85°C, sampling rate=max rated,50%clock duty cycle,AVDD5=5V,AVDD3=3.3V,DVDD3=3.3V,–1dBFS differential input, and3-V PP differential clock,unless otherwise noted.
ADS5484ADS5485
PARAMETER TEST CONDITIONS UNIT
MIN TYP MAX MIN TYP MAX
DYNAMIC ACCURACY
No missing codes,
DNL Differential nonlinearity error-0.99±0.5 1.0-0.99±0.5 1.0LSB
f IN=30MHz
INL Integral nonlinearity error f IN=30MHz-10±3+10-10±3+10LSB Offset error-1515-1515mV
Offset temperature coefficient-0.02-0.02mV/°C
Gain error-6±26-6±26%FS
Gain temperature coefficient-0.01-0.01mV/°C POWER SUPPLY
I AVDD55-V analog current310330310330mA
I AVDD3 3.3-V analog current126150126150mA
V IN=Full-scale,f IN=30MHz,
f S=Max rated,Normal operation
I DVDD3 3.3-V digital/LVDS current60656065mA
Total power dissipation 2.16 2.35 2.16 2.35W
I AVDD55-V analog current9898mA
I AVDD3 3.3-V analog current3535mA
Light sleep mode(PDWNF=H,
PDWNS=L)
I DVDD3 3.3-V digital/LVDS current0.070.07mA
Total power dissipation600680600680mW
I AVDD55-V analog current1313mA
I AVDD3 3.3-V analog current11mA
Deep sleep mode(PDWNF=L,
PDWNS=H)
I DVDD3 3.3-V digital/LVDS current0.070.07mA
Total power dissipation7010070100mW
Fast wake-up time(light sleep)From PDWNF disabled600600μS
Slow wake-up time(deep sleep)From PDWNS disabled66mS
AVDD5supply6060dB
Power-supply rejection ratio,
Without0.1-μF board supply
PSRR AVDD3supply8080dB
capacitors,with1-MHz supply
noise(see Figure46)
DVDD3supply9595dB DYNAMIC AC CHARACTERISTICS
f IN=10MHz7576.873.575.8
f IN=30MHz74.575.97375
f IN=70MHz75.775
SNR Signal-to-noise ratio,dither disabled dBFS
f IN=130MHz73.575.77274.8
f IN=170MHz75.674.8
f IN=230MHz74.974.4
f IN=10MHz84958493
f IN=30MHz84918290
f IN=70MHz8787
Spurious-free dynamic range,dither
SFDR dBc disabled f
=130MHz78867885
IN
f IN=170MHz8178
f IN=230MHz7373
f IN=10MHz8410084100
f IN=30MHz84958295
f IN=70MHz9595
HD2Second-harmonic,dither disabled dBc
f IN=130MHz78877885
f IN=170MHz8178
f IN=230MHz7373
Copyright?2008–2009,Texas Instruments Incorporated Submit Documentation Feedback5
ADS5484ADS5485
SLAS610C –AUGUST 2008–REVISED OCTOBER https://www.doczj.com/doc/c610157299.html,
ELECTRICAL CHARACTERISTICS (ADS5484,ADS5485)(continued)
Typical values at T A =25°C:minimum and maximum values over full temperature range T MIN =–40°C to T MAX =85°C,
sampling rate =max rated,50%clock duty cycle,AVDD5=5V,AVDD3=3.3V,DVDD3=3.3V,–1dBFS differential input,and 3-V PP differential clock,unless otherwise noted.
ADS5484ADS5485
PARAMETER
TEST CONDITIONS UNIT
MIN TYP MAX
MIN TYP MAX
f IN =10MHz 84978499f IN =30MHz
84
9182
87f IN =70MHz 8787HD3
Third-harmonic,dither disabled
dBc
f IN =130MHz 78
8678
85f IN =170MHz 8281f IN =230MHz 7373f IN =10MHz 84968493f IN =30MHz
84918290Worst harmonic/spur
f IN =70MHz 9090(other than HD2and HD3),dither dBc f IN =130MHz 78917890disabled
f IN =170MHz 9090f IN =230MHz 8787f IN =10MHz 81928192f IN =30MHz
81867985f IN =70MHz 8685Total harmonic distortion,dither THD
dBc disabled
f IN =130MHz 75847581f IN =170MHz 7876f IN =230MHz 7070f IN =10MHz 73.575.871.574.6f IN =30MHz
73757173.8f IN =70MHz 74.373.7Signal-to-noise and distortion,dither SINAD
dBc disabled
f IN =130MHz 71.573.87072.9f IN =170MHz 72.971.7f IN =230MHz
68.768.4f IN1=29.5MHz,f IN2=30.5MHz,99.195.9
Each at –7dBFS
Two-tone SFDR (worst spurious or IMD
dBFS
IMD)
f IN1=69.5MHz,f IN2=70.5MHz,95.395.2Each at –10dBFS
Effective number of bits
f IN =10MHz (from SINAD in dBc 11.9212.311.5812.1ENOB Bits at -1dBFS)
2.9 2.9LSB rms Noise
RMS idle-channel noise
Analog inputs shorted together
78
78
dBFS LVDS DIGITAL OUTPUTS Assumes a 100-?differential V OD Differential output voltage (±)load on each LVDS pair and 247350454247350454mV LVDS bias =3.5mA
V OC Common-mode output voltage 1.125
1.25
1.375
1.125
1.25
1.375
V DIGITAL INPUTS
V IH High-level input voltage 2
2
V V IL Low-level input voltage 0.80.8V I IH High-level input current PDWNF,PDWNS,DITHER
1
1
μA I IL
Low-level input current -1
-1
μA Input capacitance
2
2
pF
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ADS5485 is Not Recommended for New Designs
T0158-02
Sampling Clock Input
Data Clock
Output
Output Data
N
N –1E = Even Bits = B0, B2, B4, B6, B8, B10, B12, B14O = Odd Bits = B1, B3, B5, B7, B9, B11, B13, B15
Dx_y_P/M are LVDS outputs that have two bits per pair (EVEN and ODD).The values for x and y are 0_1, 2_3, 4_5, ... 14_15.
ADS5484ADS5485
https://www.doczj.com/doc/c610157299.html, ...............................................................................................................................................SLAS610C –AUGUST 2008–REVISED OCTOBER 2009
TIMING INFORMATION
Figure 1.Timing Diagram
TIMING CHARACTERISTICS (1)
Typical values at T A =25°C:minimum and maximum values over full temperature range T MIN =–40°C to T MAX =85°C,
sampling rate =max rated,50%clock duty cycle,AVDD5=5V,AVDD3=3.3V,DVDD3=3.3V,and 3-V PP differential clock,unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT t a
Aperture delay 200ps Aperture jitter,rms Internal jitter of the ADC
80fs Latency
5
cycles t CLK Clock period
1e9/CLK 100ns CLK =max rated clock for that part t CLKH Clock pulse duration,high 0.5e9/CLK 50ns number
t CLKL Clock pulse duration,low 0.5e9/CLK
50ns t DRY CLK to DRY delay time (2)150019002300ps Zero crossing,5-pF parasitic to GND t DATA CLK to DATA delay time (2)14001900
2400ps t SKEW DATA to DRY skew t DATA –t DRY ,5-pF parasitic to GND –500
0500ps t RISE DRY/DATA rise time 500ps 5-pF parasitic to GND
t FALL DRY/DATA fall time
500
ps
(1)Timing parameters are assured by design or characterization,but not production tested.
(2)
DRY and DATA are updated on the rising edge of CLK input.The latency must be added to t DATA to determine the overall propagation delay.
Copyright ?2008–2009,Texas Instruments Incorporated Submit Documentation Feedback 7
ADS5485 is Not Recommended for New Designs
AGND
48474645444342
4140393837363534
33ADS548x RGC Package (Top View)
123456789
10111213141516AVDD5AVDD5AGND REF NC NC AGND AVDD5AVDD3AGND INP INM AGND AVDD5AVDD3VCM
A G N D
A V D D 5
A V D D 3
A G N D
C L K M
C L K P
A G N D
A V D D 5
A V D D 3
A G N D
A V D D 5
A V D D 3
A G N D
A V D D 5
A V D D 3
A G N D
17
6418
6319
6220
61216022
5923
5824
5725
5626
5527
5428
5329
5230
513150
32
49D4_5_P D4_5_M D2_3_P D2_3_M D0_1_P D0_1_M DVDD3DGND NC NC NC NC DITHER PDWNS PDWNF LVDSB
D G N D
D V D D 3
D 14_15_P
D 14_15_M
D 12_13_P
D 12_13_M
D 10_11_P
D 10_11_M
D 8_9_P
D 8_9_M
D R Y _P
D R Y _M
D V D D 3
D G N D
D 6_7_P
D 6_7_M P0056-08
ADS5484ADS5485
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PIN CONFIGURATION
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ADS5484 ADS5485 is Not Recommended for New Designs
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Table2.PIN FUNCTIONS
PIN
DESCRIPTION
NAME NO.
1,2,8,14,18,
AVDD55-V analog supply
24,27,30
9,15,19,25,
AVDD3 3.3-V analog supply
28,31
3,7,10,13,17,
AGND20,23,26,29,Analog ground
32
DVDD342,52,63 3.3-V digital supply
DGND41,51,64Digital ground
NC5,6,37-40No connect-leave floating
INP,INM11,12Differential analog inputs(P=plus=true,M=minus=complement)
CLKM,CLKP21,22Differential clock inputs(P=plus=true,M=minus=complement)
Reference voltage input/output(1.2V nominal).To use an external reference and to turn the internal REF4reference off,pull both PDWNF and PDWNS to logic high(DVDD3).A0.1-μF capacitor to ground on
REF is recommended but not required.
Analog input common mode,output(3.1V),for use in applications that require use of the internally
VCM16generated common-mode.See the Applications section for more information on using VCM.A0.1-μF
capacitor to ground on VCM is recommended but not required.
External bias resistor for LVDS bias current,normally10k?to GND to provide nominal3.5-mA LVDS LVDSB33
current.
Light sleep power down,fast wake-up,logic high(DVDD3)=light sleep enabled(bandgap reference PDWNF34
remains on)
Deep sleep power down,slow wake-up,logic high(DVDD3)=deep sleep enabled(bandgap reference PDWNS35
is off)
DITHER36Dither enable,logic high(DVDD3)=dither enabled
DRY_P,
54,53Data ready signal(LVDS clock out)(P=plus=true,M=minus=complement)
DRY_M
D14_15_P,
62,61DDR LVDS output bits14then15(15is MSB)(P=plus=true,M=minus=complement)
D14_15_M
DE_O_P,
43-50,55-62DDR LVDS output bits E(even)then O(odd)(P=plus=true,M=minus=complement)
DE_O_M
D0_1_P,
44,43DDR LVDS output bits0then1(0is LSB)(P=plus=true,M=minus=complement)
D0_1_M
PowerPAD65Analog ground(exposed pad on bottom of package)
Copyright?2008–2009,Texas Instruments Incorporated Submit Documentation Feedback9
?120
?110?100?90?80?70?60?50?40?30?20?100A m p l i t u d e ? d B
?120
?110?100?90?80?70?60?50?40?30?20?100A m p l i t u d e ? d B
?120
?110?100?90?80?70?60?50?40?30?20?100A m p l i t u d e ? d B
?120
?110?100?90?80?70?60?50?40?30?20?100A m p l i t u d e ? d B
ADS5484ADS5485
SLAS610C –AUGUST 2008–REVISED OCTOBER https://www.doczj.com/doc/c610157299.html,
TYPICAL CHARACTERISTICS
At T A =25°C,sampling rate =max rated,50%clock duty cycle,3-V PP differential sinusoidal clock,analog input amplitude =
–1dBFS,AVDD5=5V,AVDD3=3.3V,and DVDD3=3.3V,unless otherwise noted.
ADS5484-170-MSPS Typical Data
Plots in this section are with a clock of 170MSPS,unless otherwise specified.
ADS5484SPECTRAL PERFORMANCE
ADS5484SPECTRAL PERFORMANCE
vs
vs
FFT for 10-MHz INPUT SIGNAL
FFT for 70-MHz INPUT SIGNAL
ADS5484SPECTRAL PERFORMANCE
ADS5484SPECTRAL PERFORMANCE
vs
vs
FFT for 130-MHz INPUT SIGNAL
FFT for 230-MHz INPUT SIGNAL
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ADS5485 is Not Recommended for New Designs
分销商库存信息:
TI
ADS5484IRGCT ADS5484IRGCR ADS5484IRGCRG4 ADS5484IRGCTG4ADS5485IRGCR ADS5485IRGCRG4 ADS5485IRGCTG4