The General Situation of AT89C51
The AT89C51 is a low-power, high-performance CMOS 8-bit microcomputer with 4K bytes of Flash Programmable and Erasable Read Only Memory (PEROM) and 128 bytes RAM. The device is manufactured using Atmel’s high density nonvolatile memory technology and is compatible with the industry standard MCS-51? instruction set and pin out. The chip combines a versatile 8-bit CPU with Flash on a monolithic chip; the Atmel AT89C51 is a powerful microcomputer which provides a highly flexible and cost effective solution to many embedded control applications.
Features:
? Compatible with MCS-51? Products
? 4K Bytes of In-System Reprogrammable Flash Memory
? Endurance: 1,000 Write/Erase Cycles
? Fully Static Operation: 0 Hz to 24 MHz
? Three-Level Program Memory Lock
? 128 x 8-Bit Internal RAM
? 32 Programmable I/O Lines
? Two 16-Bit Timer/Counters
? Six Interrupt Sources
? Programmable Serial Channel
? Low Power Idle and Power Down Modes
The AT89C51 provides the following standard features: 4K bytes of Flash, 128 bytes of RAM, 32 I/O lines, two 16-bit timer/counters, a five vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator and clock circuitry. In addition, the AT89C51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes.
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The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port and interrupt system to continue functioning. The Power Down Mode saves the RAM contents but freezes the oscillator disabling all other chip functions until the next hardware reset.
Block Diagram
Pin Description:
VCC Supply voltage.
GND Ground.
Port 0：Port 0 is an 8-bit open drain bidirectional I/O port. As an output port each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high impedance inputs. (Sink/flow)
Port 0 may also be configured to be the multiplexed low order address/data bus during accesses to external program and data memory. In this mode P0 has
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internal pull-ups.
Port 0 also receives the code bytes during Flash programming, and outputs the code bytes during program verification. External pull-ups are required during program verification.
Port 1：Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pull-ups.
Port 1 also receives the low-order address bytes during Flash programming and verification.
Port 2：Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pull-ups.
Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that uses 16-bit addresses (MOVX @ DPTR). In this application it uses strong internal p ull-ups when emitting 1s. During accesses to external data memories that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register.
Port 2 also receives the high-order address bits and some control signals during Flash programming and verification.
Port 3：Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (IIL) because of the pull-ups.
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Port 3 also serves the functions of various special features of the AT89C51 as listed below:
Port 3 also receives some control signals for Flash programming and verification.
RST：Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device.
ALE/PROG：Address Latch Enable output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming.
In normal operation ALE is emitted at a constant rate of 1/6 the oscillator frequency, and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external Data Memory.
If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode.
PSEN：Program Store Enable is the read strobe to external program memory.
When the AT89C51 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory.
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EA/VPP：External Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1(LB1) is programmed, EA will be internally latched (fasten with a latch) on reset.
EA should be strapped to VCC for internal program executions.
This pin also receives the 12-volt programming enable voltage（VPP) during Flash programming, for parts that require 12-volt VPP.
XTAL1：Input to the inverting oscillator amplifier and input to the internal clock operating circuit.
XTAL2：Output from the inverting oscillator amplifier.
Oscillator Characteristics：XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier which can be configured for use as an on-chip oscillator, as shown in Figure 1. Either a quartz crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 2. There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum voltage high and low times specifications must be observed.
Idle Mode：In idle mode, the CPU puts itself to sleep while all the on chip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the special functions registers remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset.
It should be noted that when idle is terminated by a hard ware reset, the device normally resumes program execution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when Idle is terminated by reset, the instruction following the one that invokes Idle
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should not be one that writes to a port pin or to external memory.
Power Down Mode
In the power down mode the oscillator is stopped, and the instruction that invokes power down is
the last instruction executed. The on-chip RAM and Special Function Registers retain their values until the power down mode is terminated. The only exit from power down is a hardware reset. Reset redefines the SFRs but does not change the on-chip RAM. The reset should not be activated before VCC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize.
Program Memory Lock Bits
On the chip are three lock bits which can be left unprogrammed (U) or can be programmed (P) to obtain the additional features listed in the table below:
When lock bit 1 is programmed, the logic level at the EA pin is sampled and latched during reset. If the device is powered up without a reset, the latch initializes to a random value, and holds that value until reset is activated. It is
necessary that the latched value of EA be in agreement with the current logic level at that pin in order for the device to function properly.
Programming the Flash：The AT89C51 is normally shipped with the on-chip Flash memory array in the erased state (that is, contents = FFH) and ready to be programmed.The programming interface accepts either a high-voltage (12-volt) or a low-voltage (VCC) program enable signal.The low voltage programming mode provides a convenient way to program the AT89C51 inside the user’s system, while the high-voltage programming mode is compatible with conventional third party Flash or EPROM programmers.
The AT89C51 is shipped with either the high-voltage or low-voltage programming mode enabled. The respective top-side marking and device signature
The AT89C51 code memory array is programmed byte-bybyte in either programming mode. To program any nonblank byte in the on-chip Flash Programmable and Erasable Read Only Memory, the entire memory must be erased using the Chip Erase Mode.
Programming Algorithm: Before programming the AT89C51, the address, data and control signals should be set up according to the Flash programming mode table and Figures 3 and 4. To program the AT89C51, take the following steps.
1. Input the desired memory location on the address lines.
2. Input the appropriate data byte on the data lines.
3. Activate the correct combination of control signals.
4. Raise EA/VPP to 12V for the high-voltage programming mode.
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5. Pulse ALE/PROG once to program a byte in the Flash array or the lock bits. The byte-write cycle is self-timed and typically takes no more than 1.5 ms. Repeat steps 1 through 5, changing the address and data for the entire array or until the end of the object file is reached.
Data Polling: The AT89C51 features Data Polling to indicate the end of a write cycle. During a write cycle, an attempted read of the last byte written will result in the complement of the written datum on PO.7. Once the write cycle has been completed, true data are valid on all outputs, and the next cycle may begin. Data Polling may begin any time after a write cycle has been initiated.
Ready/Busy:The progress of byte programming can also be monitored by the RDY/BSY output signal. P3.4 is pulled low after ALE goes high during programming to indicate BUSY. P3.4 is pulled high again when programming is done to indicate READY.
Program Verify: If lock bits LB1 and LB2 have not been programmed, the programmed code data can be read back via the address and data lines for verification. The lock bits cannot be verified directly. Verification of the lock bits is achieved by observing that their features are enabled.
Chip Erase: The entire Flash Programmable and Erasable Read Only Memory array is erased electrically by using the proper combination of control signals and by holding ALE/PROG low for 10 ms. The code array is written with all “1”s. The chip erase operation must be executed before the code memory can be re-programmed.
Reading the Signature Bytes: The signature bytes are read by the same procedure as a normal verification of locations 030H, 031H, and 032H, except that P3.6 and P3.7 must be pulled to a logic low. The values returned are as follows.
(030H) = 1EH indicates manufactured by Atmel
(031H) = 51H indicates 89C51
(032H) = FFH indicates 12V programming
(032H) = 05H indicates 5V programming
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Programming Interface
Every code byte in the Flash array can be written and the entire array can be erased by using the appropriate combination of control signals. The write operation cycle is selftimed and once initiated, will automatically time itself to completion.
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AT89C51的概况
AT89C51是美国ATMEL公司生产的低电压，高性能CMOS8位单片机，
片内含4Kbytes的快速可擦写的只读程序存储器（PEROM）和128 bytes 的随机存取数据存储器（RAM），器件采用ATMEL公司的高密度、非易失性存储技术生产，兼容标准MCS-51产品指令系统，片内置通用8位中央处理器（CPU）和flish存储单元，功能强大AT89C51单片机可为您提供许多高性价比的应用场合，可灵活应用于各种控制领域。
主要性能参数：
与MCS-51产品指令系统完全兼容
4K字节可重复写flash闪速存储器
1000次擦写周期
全静态操作：0HZ－24MHZ
三级加密程序存储器
128*8字节内部RAM
32个可编程I/O口
2个16位定时／计数器
6个中断源
可编程串行UART通道
低功耗空闲和掉电模式
功能特性概述
AT89C51提供以下标准功能：4K 字节flish闪速存储器，128字节内部RAM，32个I/O口线，两个16位定时／计数器，一个5向量两级中断结构，一个全双工串行通信口，片内振荡器及时钟电路。同时，AT89C51可降至0HZ的静态逻辑操作，并支持两种软件可选的节电工作模式。空闲方式停止CPU的工作，但允许RAM，定时／计数器，串行通信口及中断系统继续工作。掉电方式保存RAM中的内容，但振荡器停止
工作并禁止其它所有部件工作直到下一个硬件复位。
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引脚功能说明
Vcc：电源电压
GND：地
P0口：P0口是一组8位漏极开路型双向I/O口，也即地址/数据总线复位口。作为输出口用时，每位能吸收电流的方式驱动8个逻辑门电路，对端口写“1”可作为高阻抗输入端用。
在访问外部数据存储器或程序存储器时，这组口线分时转换地址（低8位）和数据总线复用，在访问期间激活内部上拉电阻。
P1口：P1是一个带内部上拉电阻的8位双向I/O口，P1的输出缓冲级可驱动（吸收或输出电流）4个TTL逻辑门电路。对端口写“1”，通过内部的上拉电阻把端口拉到高电平，此时可做熟出口。做输出口使
用时，因为内部存在上拉电阻，某个引脚被外部信号拉低时会输出一个
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电流（Iil）.
Flash编程和程序校验期间，P1接受低8位地址。
P2口：P2是一个带有内部上拉电阻的8位双向I/O口，P2的输出缓冲级可驱动（吸收或输出电流）4个TTL逻辑门电路。对端口写“1”，通过内部地山拉电阻把端口拉到高电平，此时可作为输出口，作输出口使用时，因为内部存在上拉电阻，某个引脚被外部信号拉低时会输出一个电流（Iil）。
在访问外部程序存储器获16位地址的外部数据存储器（例如执行MOVX @DPTR指令）时，P2口送出高8位地址数据。在访问8位地址的外部数据存储器（如执行 MOVX @RI指令）时，P2口线上的内容（也即特殊功能寄存器（SFR）区中R2寄存器的内容），在整个访问期间不改变。
Flash编程或校验时，P2亦接受高地址和其它控制信号。
P3口：P3口是一组带有内部上拉电阻的8位双向I/O口。P3口输出缓冲级可驱动（吸收或输出电流）4个TTL逻辑门电路。对P3口写入“1”时，他们被内部上拉电阻拉高并可作为输出口。做输出端时，被外部拉低的P3口将用上拉电阻输出电流（Iil）。P3口除了作为一般的I/O口线外，更重要的用途是它的第二功能，如下表所示：
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P3口还接收一些用于flash闪速存储器编程和程序校验的控制信号。
RST：复位输入。当振荡器工作时，RST引脚出现两个机器周期以上高电平将使单片机复位。
ALE/PROG：当访问外部程序存储器或数据存储器时，ALE（地址所存允许）输出脉冲用于所存地址的低8位字节。即使不访问外部存储器，ALE仍以时钟振荡频率的1/6输出固定的正脉冲信号，因此它可对外输出时钟或用于定时目的。要注意的是：每当访问外部数据存储器时将跳过一个ALE脉冲。
对flash存储器编程期间，该引脚还用于输入编程脉冲（^PROG）。
如有不要，可通过对特殊功能寄存器（SFR）区中的8EH单元的D0位置位，可禁止ALE操作。该外置位后，只要一条MOVX和MOVC指令ALE才会被激活。此外，该引脚会被微弱拉高，单片机执行外部程序时，应设置ALE无效。
PSEN：程序存储允许（^PSEN）输出是外部程序存储器的读选通信号，当AT89C51由外部程序存储器取指令（或数据）时，每个机器周期两个^PSEN有效，即输出两个脉冲。在此期间，当访问外部数据存储器，这两次有效的^PSEN信号不出现。
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EA/VPP:外部访问允许。欲使CPU仅访问外部程序存储器（地址为0000H---FFFFH），EA端必须保持低电平（接地）。需注意的是; 如果加密位LB1被编程，复位时内部会锁存EA端状态。
如 EA端为高电平（接VCC端），CPU则执行内部程序存储器中的指令。
Flash存储器编程时，该引脚加上+12V的编程允许电源VPP，当然这必须是该器件是使用12V编程电压VPP.
XTAL1: 振荡器反相放大器的及内部时钟发生器的输出端。
XTAL2: 振荡器反相放大器的输出端。
时钟振荡器：AT89C51中有一个用于构成内部振荡器的高增益反相放大器，引脚XTAL1和XTAL2分别是该放大器的输入端和输出端。这个放大器与作为反馈的片外石英晶体或陶瓷谐振器一起构成自激振荡器，振荡电路参见图5。
外接石英晶体（或陶瓷谐振器）及电容C1、C2接在放大器的反馈回路中构成并联振荡电路。对外接电容C1、C2虽然没有十分严格的要求，但电容容量的大小会轻微影响振荡频率的高低、振荡器的稳定性、起振的难易程度及温度稳定性，如果使用石英晶体，我们推荐电容使用30PF+10PF，而如使用陶瓷谐振器建议选择40PF+10PF。
用户也可以采用外部时钟。采用外部时钟的电路如图5右所示。这种情况下，外部时钟脉冲接到XTAL1端，即内部时钟发生器的输入端，XTAL2则悬空
由于外部时钟信号是通过一个2分频触发器后作为内部时钟信号的，所以对外部时钟信号的占空比没有特殊要求，但最小高电平持续时间和最大的低电平持续时间应符合产品技术要求。
空闲模式：在空闲工作模式状态，CPU保持睡眠状态而所有片内的外设仍保持激活状态，这种方式由软件产生。此时，片内RAM和所有特殊功能寄存器的内容保持不变。空闲模式可由任何允许的中断请求或硬件复位终止。
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终止空闲工作模式的方法有两种，其一是任何一条被允许中断的事件被激活，即可终止空闲工作模式。程序会首先响应中断，进入中断服务程序，执行完中断服务程序并仅随终端返回指令，下一条要执行的指令就是使单片机进入空闲模式那条指令后面的一条指令。其二是通过硬件复位也可将空闲工作模式终止，需要注意的是，当由硬件复位来终止空闲模式时，CPU通常是从激活空闲模式那条指令的下一条指令开始继续执行程序的，要完成内部复位操作，硬件复位脉冲要保持两个机器周期（24个时钟周期）有效，在这种情况下，内部禁止CPU访问片内RAM，而允许访问其它端口。为了避免可能对端口产生以外写入，激活空闲模式的那条指令后一条指令不应该是一条对端口或外部存储器的写入指令。
掉电模式
在掉电模式下，震荡器停止工作，进入掉电模式的指令是最后一条被执行的指令，片内RAM和特殊功能寄存器的内容在终止掉电模式前被冻结。退出掉电模式的唯一方法是硬件复位，复位后将重新定义全部特殊功能寄存器但不改变RAM中的内容，在VCC恢复到正常工作电平前，复位应无效，且必须保持一定时间以使振荡器重启动并稳定工作。
程序存储器的加密：AT89C51可使用对芯片上的3个加密位进行编程（P）或不编程（U）来得到如下表所示的功能：
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当加密位LB1被编程时，在复位期间，EA端的逻辑电平被采样并锁存，如果单片机上电后一直没有复位，则锁存起的初始值是一个随机数，且这个随机数会一直保持到真正复位为止。为使单片机能正常工作，被锁存的EA电平值必须与该引脚当前的逻辑电平一致。此外，加密位只能通过整片擦除的方法清除。
FLASH闪速存储器的编程：AT89C51单片机内部有4K字节的FLASH PEROM,这个FLASH存储阵列出厂时已处于擦除状态（即所有存储单元的内容均为FFH），用户随时可对其进行编程。编程接口可接收高电平（+12V）或低电平（VCC）的允许编程信号，低电平编程模式适合于用户再线编程系统，而高电平编程模式可与通用EPROM编程器兼容。
AT89C51单片机中，有些属于低电压编程方式，而有些则是高电平编程方式，用户可从芯片上的型号和读取芯片内的签名字节获得该信息，见下表。
AT89C51的程序存储器阵列是采用字节写入方式编程的，每次写入一个字节，要对整个芯片内的PEROM程序存储器写入一个非空字节，必须使用片擦除的方式将整个存储器的内容清除。
编程方法：编程前，需按表1、图3和图4所示设置好地址，数据及控制信号， AT89C51编程方法如下：
1.在地址线上加上要编程单元的地址信号。
2.在数据线上加上要写入的数据字节。
3.激活相应的控制信号。
4.在高电压编程方式时，将^EA/VPP端加上+12V编程电压。
5.每对FLASH存储阵列写入一个字节或每写入一个程序加密位，加上一个ALE/^PROG编程脉冲，改变编程单元的地址和写入的数据，重复1—5步骤，直到全部文件编程结束。每个字节写入周期是自身定时地，通常约为1.5ms。
数据查询：AT89C51单片机用数据查询方式来检测一个写周期是否结束，在一个写周期中，如需要读取最后写入的那个字节，则读出的数据的最高位（P0.7）是原来写入字节最高位的反码。写周期完成后，有效的数据就会出现在所有输出端上，此时，可进入下一个字节的写周期，写周期开始后，可在任意时刻进行数据查询。
READY/^BUSY：字节编程的进度可通过“RDY/^BSY”输出信号监测，编程期间，ALE变为高电平“H”后P3.4(RDY/^BSY)端电平被拉低，表示正在编程状态（忙状态）。编程完成后，P3.4变为高电平表示准备就绪状态。
程序校验：如果加密位LB1、LB2没有进行编程，则代码数据可通过地址和数据线读回原编写的数据。加密位不可能直接变化。证实加密位的完成通过观察它们的特点和能力。
芯片擦除：利用控制信号的正确组合（表1）并保持ALE/^PROG引
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脚10ms的低电平脉冲宽度即可将PEROM阵列（4k字节）整片擦除，代码阵列在擦除操作中将任何非空单元写入“1”，这步骤需要再编程之前进行。
读片内签名字节：AT89C51单片机内有3个签名字节，地址为030H、031H和032H。用于声明该器件的厂商、型号和编程电压。读签名字节的过程和单元030H、031H和032H的正常校验相仿，只需将P3.6和P3.7保持低电平，返回值意义如下：
（030H）=1EH声明产品由ATMEL公司制造。
（031H）=51H声明为AT89C51单片机。
（032H）=FFH声明为12V编程电压。
（032H）=05H声明为5V编程电压。
编程接口：采用控制信号的正确组合可对FLASH闪速存储阵列中的每一代码字节进行写入和存储器的整片擦除，写操作周期是自身定时的，初始化后它将自动定时到操作完成。
英文原文
Description
The at89s52 is a low-power, high-performance CMOS 8-bit microcomputer with 4K bytes of Flash Programmable and Erasable Read Only Memory (PEROM) and 128 bytes RAM. The device is manufactured using Atmel’s high density nonvolatile memory technology and is compatible with the industry standard MCS-51? instruction set and pinout. The chip combines a versatile 8-bit CPU with Flash on a monolithic chip, the Atmel
at89s52 is a powerful microcomputer which provides a highly flexible and cost effective solution to many embedded control applications.
Features:
? Compatible with MCS-51? Products
? 4K Bytes of In-System Reprogrammable Flash Memory
? Endurance: 1,000 Write/Erase Cycles
? Fully Static Operation: 0 Hz to 24 MHz
? Three-Level Program Memory Lock
? 128 x 8-Bit Internal RAM
? 32 Programmable I/O Lines
18
? Two 16-Bit Timer/Counters
? Six Interrupt Sources
? Programmable Serial Channel
? Low Power Idle and Power Down Modes
19
The at89s52 provides the following standard features: 4K bytes of Flash, 128 bytes of RAM, 32 I/O lines, two 16-bit timer/counters, a five vector
two-level interrupt architecture, a full duplex serial port, on-chip oscillator and clock circuitry. In addition, the at89s52 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port and interrupt system to continue functioning. The Power Down Mode saves the RAM contents but freezes the oscillator disabling all other chip functions until the next hardware reset.
Pin Description:
VCC Supply voltage.
GND Ground.
Port 0
20
中国联通China Unicom 中国移动China Mobile 网络容量network capacity 交换容量exchange capacity 扩容Capacity Expansion 平滑升级smooth upgrade 射频Radio Frequencies 接收灵敏度Receive Sensitivity: 数据Data Options 传输速率Data Rate 电源部分Power supply 数据接口Data Interface 天线接口Antenna Interface 传输速率Baud Rate 用户交互界面User Interface 认证Certifications 网络数据传输数率net data transfer rate 联通无限U-Max 旗下subordinate] 品牌trademark U-Info 互动视界U-Magic 神奇宝典 U-Net 掌中宽带 U-Mail 彩e U-Map 定位之星 U-Sms 联通在信 应用服务Application Service 产业价值链industrial value chain 战略目标strategic objective 渠道channel 转型transition/Transformation 推广extension 针对aim at 电信telecommunication 整合conformity 市场渗透率market penetration factor 微观的microcosmic 科学技术science and technology 地理环境geographic environment 宏观的macroscopical 供应链supply chain 产品种类product variety
通信一班序号：28 姓名：粟清明学号：14102301239 JXTA is a crystallization by Sun company's chief scientist Bill Joy's more than twenty years of brewing."JXTA technology is a platform for Network programming and calculation.To solve the modern distribution calculation especially peer-to-peer (Peer to Peer, P2P) in the calculation of the problem". [1] JXTA research project,which will provide a new framework that make the user more convenient to access to connect on the Internet's personal computer resources, thus further expand Internet 's space. At the same time JXTA is also the Sun's "ONE Internet" strategic continuance, and will take a more positive attitude to compete with the .net strategy of Microsoft and Hailstorm plan . JXTA agreement defines a set of six agreement based on XML, the organization of node into node group, release and found some resources, communication and mutual monitoring provides standardized method. (Endpoint Routing Protocol,ERP) is used for node found routing.To send a message to other nodes, and through the potential firewall and connection. (Rendezvous Protocol,RVP) s used for the nodes in the group to spread information.(Peer Resolver Protocol,PRP) is Used to one or more points to send general inquiries, and receive the response of inquiries. (Peer Discovery Protocol, PDP) is used to release and found advertising resources. (Peer Information Protocol, PIP) used to get other nodes state Information. (Peer Binding Protocol, PBP), can let a node with another node or between more nodes to set up virtual communication channel or pipeline. Compared to the nowadays general communication mode .P2P has many advantages, but it also has a lot of problems waiting to be solved.Firstly, each Peer in P2P is an active participant,in order to make the network performance increase, they need more Peer's participation, so that will result in the network's huge, manage this network will is a complex project; Secondly, P2P agreement compares with traditional
第一课 土木工程学土木工程学作为最老的工程技术学科，是指规划，设计，施工及对建筑环境的管理。此处的环境包括建筑符合科学规范的所有结构，从灌溉和排水系统到火箭发射设施。 土木工程师建造道路，桥梁，管道，大坝，海港，发电厂，给排水系统，医院，学校，公共交通和其他现代社会和大量人口集中地区的基础公共设施。他们也建造私有设施，比如飞机场，铁路，管线，摩天大楼，以及其他设计用作工业，商业和住宅途径的大型结构。此外，土木工程师还规划设计及建造完整的城市和乡镇，并且最近一直在规划设计容纳设施齐全的社区的空间平台。 土木一词来源于拉丁文词“公民”。在1782年，英国人John Smeaton为了把他的非军事工程工作区别于当时占优势地位的军事工程师的工作而采用的名词。自从那时起，土木工程学被用于提及从事公共设施建设的工程师，尽管其包含的领域更为广阔。 领域。因为包含范围太广，土木工程学又被细分为大量的技术专业。不同类型的工程需要多种不同土木工程专业技术。一个项目开始的时候，土木工程师要对场地进行测绘，定位有用的布置，如地下水水位，下水道，和电力线。岩土工程专家则进行土力学试验以确定土壤能否承受工程荷载。环境工程专家研究工程对当地的影响，包括对空气和地下水的可能污染，对当地动植物生活的影响，以及如何让工程设计满足政府针对环境保护的需要。交通工程专家确定必需的不同种类设施以减轻由整个工程造成的对当地公路和其他交通网络的负担。同时，结构工程专家利用初步数据对工程作详细规划，设计和说明。从项目开始到结束，对这些土木工程专家的工作进行监督和调配的则是施工管理专家。根据其他专家所提供的信息，施工管理专家计算材料和人工的数量和花费，所有工作的进度表，订购工作所需要的材料和设备，雇佣承包商和分包商，还要做些额外的监督工作以确保工程能按时按质完成。 贯穿任何给定项目，土木工程师都需要大量使用计算机。计算机用于设计工程中使用的多数元件（即计算机辅助设计，或者CAD）并对其进行管理。计算机成为了现代土木工程师的必备品，因为它使得工程师能有效地掌控所需的大量数据从而确定建造一项工程的最佳方法。 结构工程学。在这一专业领域，土木工程师规划设计各种类型的结构，包括桥梁，大坝，发电厂，设备支撑，海面上的特殊结构，美国太空计划，发射塔，庞大的天文和无线电望远镜，以及许多其他种类的项目。结构工程师应用计算机确定一个结构必须承受的力：自重，风荷载和飓风荷载，建筑材料温度变化引起的胀缩，以及地震荷载。他们也需确定不同种材料如钢筋，混凝土，塑料，石头，沥青，砖，铝或其他建筑材料等的复合作用。 水利工程学。土木工程师在这一领域主要处理水的物理控制方面的种种问题。他们的项目用于帮助预防洪水灾害，提供城市用水和灌溉用水，管理控制河流和水流物，维护河滩及其他滨水设施。此外，他们设计和维护海港，运河与水闸，建造大型水利大坝与小型坝，以及各种类型的围堰，帮助设计海上结构并且确定结构的位置对航行影响。 岩土工程学。专业于这个领域的土木工程师对支撑结构并影响结构行为的土壤和岩石的特性进行分析。他们计算建筑和其他结构由于自重压力可能引起的沉降，并采取措施使之减少到最小。他们也需计算并确定如何加强斜坡和填充物的稳定性以及如何保护结构免受地震和地下水的影响。 环境工程学。在这一工程学分支中，土木工程师设计，建造并监视系统以提供安全的饮用水，同时预防和控制地表和地下水资源供给的污染。他们也设计，建造并监视工程以控制甚至消除对土地和空气的污染。他们建造供水和废水处理厂，设计空气净化器和其他设备以最小化甚至消除由工业加工、焚化及其他产烟生产活动引起的空气污染。他们也采用建造特殊倾倒地点或使用有毒有害物中和剂的措施来控制有毒有害废弃物。此外，工程师还对垃圾掩埋进行设计和管理以预防其对周围环境造成污染。
陶瓷ceramics 合成纤维synthetic fibre 电化学腐蚀electrochemical corrosion 车架automotive chassis 悬架suspension 转向器redirector 变速器speed changer 板料冲压sheet metal parts 孔加工spot facing machining 车间workshop 工程技术人员engineer 气动夹紧pneuma lock 数学模型mathematical model 画法几何descriptive geometry 机械制图Mechanical drawing 投影projection 视图view 剖视图profile chart 标准件standard component 零件图part drawing 装配图assembly drawing 尺寸标注size marking 技术要求technical requirements 刚度rigidity 内力internal force 位移displacement 截面section 疲劳极限fatigue limit 断裂fracture 塑性变形plastic distortion 脆性材料brittleness material 刚度准则rigidity criterion 垫圈washer 垫片spacer 直齿圆柱齿轮straight toothed spur gear 斜齿圆柱齿轮helical-spur gear 直齿锥齿轮straight bevel gear 运动简图kinematic sketch 齿轮齿条pinion and rack 蜗杆蜗轮worm and worm gear 虚约束passive constraint 曲柄crank 摇杆racker 凸轮cams
第一课现代数字设计及数字信号处理 课文 A: 数字信号处理简介 1.什么是数字信号处理？ 数字信号处理，或DSP，如其名称所示，是采用数字方式对信号进行处理。在这种情况下一个信号可以代表各种不同的东西。从历史的角度来讲，信号处理起源于电子工程，信号在这里意味着在电缆或电话线或者也有可能是在无线电波中传输的电子信号。然而，更通用地说，一个信号是一个可代表任何东西--从股票价格到来自于远程传感卫星的数据的信息流。术语“digital”来源于“digit”，意思是数字（代可以用你的手指计数），因此“digital”的字面意思是“数字的，用数字表示的”，其法语是“numerique”。一个数字信号由一串数字流组成，通常（但并非一定）是二进制形式。对数字信号的处理通过数字运算来完成。 数字信号处理是一个非常有用的技术，将会形成21世纪的新的科学技术。数字信号处理已在通信、医学图像、雷达和声纳、高保真音乐产生、石油开采等很广泛的领域内引起了革命性的变革。这些领域中的每一个都使得DSP技术得到深入发展，有该领域自己的算法、数学基础，以及特殊的技术。DSP发展的广度和深度的结合使得任何个人都不可能掌握已发展出的所有的DSP技术。DSP教育包括两个任务：学习应用数字信号处理的通用原则及学习你所感兴趣的特定领域的数字信号处理技术。 2.模拟和数字信号 在很多情况下，所感兴趣的信号的初始形式是模拟电压或电流，例如由麦克风或其它转换器产生的信号。在有些情况下，例如从一个CD播放机的可读系统中输出的信号，信号本身就是数字的。在应用DSP技术之前，一个模拟信号必须转换成数字信号。例如，一个模拟电压信号，可被一个称为模数转换器或ADC的电路变换成数字信号。该转换器产生一系列二进制数字作为数字输出，其值代表每个采样时刻的输入模数转换设备的电压值。 3.信号处理 通常信号需要以各种方式处理。例如，来自于传感器的信号可能被一些没用的电子“噪声”污染。测心电图时放在病人胸部的电极能测量到当心脏及其它肌肉活动时微小的电压变化。信号也常会被来自于电源的电磁干扰所影响。采用滤波电路处理信号至少可以去掉不需要的信号部分。如今，对信号滤波以增加信号的质量或抽取重要信息的任务越来越多地由DSP技术完成而不是采用模拟电路完成。 4.DSP的发展和应用 数字信号处理的发展起源于60年代大型数字计算机进行数字处理的应用，如使用快速傅立叶变换（FFT）可以快速计算信号的频谱。这些技术在当时并没有被广泛应用，因为通常只有在大学或者其它的科研机构才有合适的计算机。 由于当时计算机很贵，DSP仅仅局限于少量的非常重要的应用。先驱们的探索工作主要集中在4个关键领域：雷达和声纳，用于保卫国家安全；石油开采，可以赚大量的钱；空间探索，其中的数据是不能重复产生的；及医学图像，可以救治生命。 20世纪80年代到90年代个人电脑的普及使得DSP产生了很多新的应用。与以往由军方或政府的需求驱动不同，DSP突然间由商业市场的需求驱动了。任何认为自己能在这个飞速发展的领域赚钱的人都会立即成为DSP供应商。DSP通过在移动电话、CD播放器及语音邮件等产品中应用进入了公共应用领域。 这些技术革命是自上而下发生的。在20世纪80年代早期，DSP是电子工程专业的研究
一、二、 十一、汉译英时分多址：TDMA （Time Division Multiple Address/ Time Division Multiple Access）2、通用无线分组业务：GPRS General Packet Radio Service 3、国际电报电话咨询委员会：CCITT 4、同步数字体系：SDH Synchronous Digital Hierarchy （同步数字序列） 5、跳频扩频：FHSS frequency hopping spread spectrum 6、同步转移模块：STM synchronous transfer module 7、综合业务数字网：ISDN Integrated Services Digital Network 8、城域网：MAN Metropolitan Area Network 9、传输控制协议/互联网协议：TCP/IP Transmission Control Protocol/Internet Protocol 10、服务质量：QOS Quality of Service 11、中继线：trunk line 12、传输速率：transmission rate 13、网络管理：network management 14、帧结构：frame structure 15、移动手机：Mobile Phone 手机 Handset 16、蜂窝交换机：（Cellular switches）（电池开关cell switch）(cell 蜂房) 17、天线：Antenna 18、微处理器：microprocessor 19、国际漫游：International roaming 20、短消息：short message 21、信噪比：SNR(Signal to Noise Ratio) 22、数字通信：Digital communication 23、系统容量：system capacity 24、蜂窝网：cell network（cellular network）（Honeycomb nets） 25、越区切换：Handover 26、互联网：internet 27、调制解调器：modem 28、频谱：spectrum 29、鼠标：Mouse 30、电子邮件：electronic mail E-mail 31、子网：subnet 32、软件无线电：software defined radios 33、网络资源：network resources 十二、英译汉 1、mobile communication：移动通信 2、Computer user：计算机用户 3、Frame format：帧格式 4、WLAN：wireless local area network 无线局域网络 5、Communication protocol：通信协议 6、Transmission quality：传输质量 7、Remote terminal：远程终端 8、International standard：国际标准 9、GSM：全球移动通信系统 Global System for Mobile Communications 10、CDMA：码分多址Code Division Multiple Access 11、ITU：国际电信联盟 International Telecommunication Union 12、PCM：pulse code modulation 脉冲编码调制 13、WDM：波分复用Wavelength Division Multiplex 14、FCC：联邦通信委员会 Federal communications commission 15、PSTN：公用电话交换网 Public Switched Telephone Network 16、NNI：网络节点借口Network Node Interface 17、WWW：万维网World Wide Web 18、VOD：视频点播Video-On-Demand 19、VLR：访问位置寄存器 Visitor Location Register 20、MSC：移动交换中心Mobile Switching Centre 21、HLR：原籍位置寄存器Home Location Register 22、VLSI：超大规模集成电路 Very Large Scale Integrated Circuits 23、Bluetooth technology：蓝牙技术 24、Matched filter：匹配滤波器 25、ADSL：非对称数字用户环路Asymmetrical Digital Subscriber Loop非对称数字用户线路(Asymmetric Digital Subscriber Line) 26、GPS：全球定位系统Global Position System 27、ATM：异步传输模式Asynchronous Transfer Mode
Building construction concrete crack of prevention and processing Abstract The crack problem of concrete is a widespread existence but again difficult in solve of engineering actual problem, this text carried on a study analysis to a little bit familiar crack problem in the concrete engineering, and aim at concrete the circumstance put forward some prevention, processing measure. Keyword: Concrete crack prevention processing Foreword Concrete's ising 1 kind is anticipate by the freestone bone, cement, water and other mixture but formation of the in addition material of quality brittleness not and all material.Because the concrete construction transform with oneself, control etc. a series problem, harden model of in the concrete existence numerous tiny hole, spirit cave and tiny crack, is exactly because these beginning start blemish of existence just make the concrete present one some not and all the characteristic of quality.The tiny crack is a kind of harmless crack and accept concrete heavy, defend Shen and
机械英语词汇大全2 金属切削 metal cutting 机床 machine tool 金属工艺学 technology of metals 刀具 cutter 摩擦 friction 联结 link 传动 drive/transmission 轴 shaft 弹性 elasticity 频率特性 frequency characteristic 误差 error 响应 response 定位 allocation 拉孔 broaching 装配 assembling 铸造 found 流体动力学 fluid dynamics 流体力学 fluid mechanics 加工 machining 液压 hydraulic pressure 切线 tangent 机电一体化 mechanotronics mechanical-electrical integration 气压 air pressure pneumatic pressure 稳定性 stability 介质 medium 数学模型 mathematical model 画法几何 descriptive geometry 机械制图 Mechanical drawing 投影 projection 视图 view 剖视图 profile chart 标准件 standard component 零件图 part drawing 装配图 assembly drawing 尺寸标注 size marking 技术要求 technical
机床夹具 jig 动力学 dynamic 运动学 kinematic 静力学 static 分析力学 analyse mechanics 拉伸 pulling 压缩 hitting 剪切 shear 扭转 twist 弯曲应力 bending stress 强度 intensity 三相交流电 three-phase AC 磁路 magnetic circles 变压器 transformer 异步电动机 asynchronous motor 液压驱动泵 fluid clutch 液压泵 hydraulic pump 阀门 valve 失效 invalidation 强度 intensity 载荷 load 应力 stress 安全系数 safty factor 可靠性 reliability 螺纹 thread 螺旋 helix 键 spline 销 pin 滚动轴承 rolling bearing 滑动轴承 sliding bearing requirements 刚度 rigidity 内力 internal force 位移 displacement 截面 section 疲劳极限 fatigue limit 断裂 fracture 塑性变形 plastic distortion 脆性材料 brittleness material 刚度准则 rigidity criterion 垫圈 washer 垫片 spacer 直齿圆柱齿轮
Unit 13 Comparison between GSM and CDMA GSM与CDMA之比较 Using CDMA/FDD technology, subscribers of CDMA cellular mobile communication system can transmit their information simultaneously through the same channel. On the other hand, the GSM system adopts TDMA/FDD method to transmit and distinguish information from different GSM mobile stations. In addition, in favor of QCELP arithmetic, RAKE receiver, power control and soft switching etc., CDMA shows more advantages in its system performance than the GSM, such as greater anti-interference capability, bigger system capacity, higher successful connection ratio, fewer off-line chances, low probability of intercept(LPI), and so on. 使用码分多址/频分双工技术，用户的蜂窝移动通信系统的传输信息的同时，通过同样的渠道。另一方面，该系统采用时分多址/频分双工传输的方法和识别信息从不同的移动台。此外，有利于中国电信集团广州研发中心算术，耙式接收器，功率控制和软开关等，显示出更多的优势在码分多址系统性能比，如更高的抗干扰能力，更大的系统容量，连接成功率较高，离线的机会少，低截获概率（低截获概率），等。 1, Power Control and RAKE Receiver功率控制和瑞克接收机 When different subscribers send their information to the same BS(base station), different signal power caused by different transmitting distances will consequentially cause interference with each other, especially for those MSs(mobile station) being far away from BS will be seriously disturbed because of their almost submerged signals by signals of the close-to-BS MSs.[2] p110 In order to solve this problem and keep high system performance, power control technique is introduced in CDMA communication system, which can effectively overcome this cross-disturbance. As one of the core techniques in CDMA cellular mobile communication system, power control can make the signal power from all subscribers to the BS equivalent through adjusting the transmitting power from each subscriber. 为解决这一问题，保持较高的系统性能，功率控制技术介绍了码分多址通信系统，它可以有效地克服这cross-disturbance。作为一个核心技术在蜂窝移动通信系统的功率控制，可以使信号功率从所有用户的学士学位相当于通过调整发射功率，从每个用户。 Power control can be not only divided to open-loop control and closed-loop control, but also to forward (down) power control and backward (up) power control. For open-loop control method, subscriber adjusts emitting power according to the measured frame error probability, while for the closed-loop power control, base station measures the signal-to-noise ratio of received signals and then adjust the transmitting power of corresponding MS. 功率控制不仅可以分为开环控制和闭环控制，而且还提出了（下）功率控制和反向功率控制（上）。开环控制方法，用户调整发射功率根据测量帧错误概率，同时为闭环功率控制，基站测量接收信号的信噪比，然后调整发射功率相应的女士 The backward power control in CDMA system can be divided into two kinds of control technique, the open-loop backward power control only used by mobile station, and the closed-loop
通信工程专业英语翻译 JXTA is a crystallization by Sun company's chief scientist Bill Joy's more than twenty years of brewing."JXTA technology is a platform for Network programming and calculation.To solve the modern distribution calculation especially peer-to-peer (Peer to Peer, P2P) in the calculation of the problem".[1] JXTA research project,which will provide a new framework that make the user more convenient to access to connect on the Internet's personal computer resources, thus further expand Internet 's space. At the same time JXTA is also the Sun's "ONE Internet" strategic continuance, and will take a more positive attitude to compete with the .net strategy of Microsoft and Hailstorm plan . JXTA agreement defines a set of six agreement based on XML, the organization of node into node group, release and found some resources, communication and mutual monitoring provides standardized method.(Endpoint Routing Protocol,ERP) is used for node found routing.To send a message to other nodes, and through the potential firewall and connection.(Rendezvous Protocol,RVP) s used for the nodes in the group to spread information.(Peer Resolver Protocol,PRP) is Used to one or more points to send general inquiries, and receive the response of inquiries.
2012级土木工程（本）专业《土木工程英语》课程论文 论文题目：高层建筑防火的研究 Research of high-rise building fire prevention 专业班级： 学生姓名： 学号： 论文成绩： 评阅教师： 2015年11 月14 日
（一） 基于性能化防火设计方法的商业综合体典型空间防火优化设计研究 正文：改革开放以来，我国市场经济蓬勃发展，各种类型的商业建筑如雨后春笋般涌现。然而人们在享受高效便捷的购物消费和休闲娱乐的同时，商业综合体及其建筑群的巨大规模、多样功能、众多人数、复杂流线、与城市多层面多点衔接等特点，极大程度地增大了灾害风险，特别是城市和建筑中最易发生的灾种——火灾的风险。传统的建筑防火设计以“条文式”的防火规范为依据，无法满足部分现代商业综合体迅速发展的设计需要，当因结构、功能、造型等方面的特殊要求，出现现行国家消防技术规范中未明确规定的、现行国家消防技术规范规定的条件不适用的、依照国家消防技术规范进行设计确有困难的情况时，将采取针对性更强、更加先进、经济、合理、有效的性能化防火措施进行建筑和规划设计。与此同时，性能化防火设计方法以其在火灾场景和人员疏散模拟等方面的突出优势，也将被更多地运用于优化“条文式”防火设计规范框架内的规划与建筑方案设计。可见研究大型商业综合体的性能化防火设计措施，并利用性能化防火设计的方法调整优化规划与建筑设计以避免和减轻火灾危害是亟待解决的重要课题。本论文共分为十章，分别介绍了课题的研究背景与意义，国内外商业综合体性能化防火的研究现状，要素构成及火灾危险性，建筑的火灾机理与性能化防火设计参数，五大类商业综合体典型空间的防火优化措施，最后提出结论与展望。本文的核心研究内容是结合商业综合体空间要素构成特征的火灾特点以及建筑防火设计中的三个重要指标（防火分区、疏散距离、疏散宽度），提炼五大类商业综合体的典型空间，即密集空间、竖向贯通空间、超大水平开敞空间、狭长通道空间和地下空间，以建筑学和城市规划学的视角，一方面运用计算机技术，对“超规范”的设计方案进行性能化防火设计安全评价，另一方面对条文式规范框架内的设计方法进行优化。性能化防火策略作为消防设计乃至贯穿整个建筑、规划设计全过程的设计思路，已初步为我们展现出应用领域的美好前景，本文旨在进一步完善和发展以数字技术为基础的性能化防火设计方法，为建筑和城市减灾防灾目标的实现提供更有力的保障。
Unit 22 3D Printing I. lead-in Information related to the text Do you know what additive Manufacturing is? It is an appropriate name to describe the technologies that build 3D objects by adding layer-upon-layer of material, whether the material is plastic, metal, concrete or one day…human tissue. Common to AM technologies is the use of a computer, 3D modelling software (Computer Aided Design or CAD), machine equipment and layering material. Now, let’s study key words and phrases of the text together. II. Word Study 1. additive ['?d?t?v] adj. 附加的；[数] 加法的n. 添加剂，添加物 1) Strict safety tests are carried out on food additives. 对食品添加剂进行了严格的安全检测。 2) The process of cultural development is additive. 文化发展是一个累积的过程。 3) But the additive's effects on humans are dire. 但此添加剂对人体的影响是可怕的。 4) We can use the additive property of the integral. 我们可利用积分的可加性。 2. fabricate ['f?br?ke?t] vt. 制造；伪造；装配 1) All four claim that officers fabricated evidence against them 四人全都声称警察捏造证据陷害他们。 2) All the tools are fabricated from high quality steel. 所有工具均由精钢制成。 3) You will work in groups to fabricate devices and collect data. 你将在一个小组中工作，一起制作器件和收集数据。 3. encompass [?n'k?mp?s; en-] vt. 包含；包围，环绕；完成 1)The map shows the rest of the western region, encompassing nine states. 地图上显示了西部地区的其他部分，包括9个州。 2)Your launch philosophy should encompass plans for both the long and sh ort terms. 你的发行理念应该包括长期和短期的计划。 3) His repertoire encompassed everything from Bach to Schoenberg. 他能演奏从巴赫到勋伯格的所有作品。 4. envision [?n'v??n] vt. 想象；预想 1) In the future we envision a federation of companies 我们设想将来会成立一个公司联盟。
4B/3D(code)--4 Binary/3 ternary (code)4二进制/3三电平（码） A A/D --Analog/Digital数/模 AAL--ATM adaptation layer ATM适配层 AC. ac.--Alternating Current 交流 ACK --ACKnowledge确认 ADC--Application data center集中托管式数据应用中心 --Analog-to-Digital Converter模拟/数字转换器(模数变换器) ADPCM--Adaptive DPCM自适应差分脉（冲编）码调制 ADPCM--Adaptive DPCM自适应差分脉冲编码调制 ADSL--Asymmetric Digital Subscriber Line非对称数字用户环路 ADSL--Asymmetric Digital Subscribers Loop非对称数字用户环路 AM--Amplitude Modulation 幅度调制、调幅 AM--Amplitude Modulation振幅调制（调幅） AMI--Alternate Mark Inverse传号交替反转 ANSI--American National Standards Institute美国国家标准学会 APK --Amplitude Phase Keying幅相键控 APT--the Advanced Packaging Tool Ubuntu软件包管理系统的高级界面ARQ--Automatic Repeat reQuest自动要求重发 ASCII--American Standard Code for Information Interchange美国标准信息交换码ASIC--Application Specific Integrated Circuit专用集成电路 ASK--Amplitude Shift Keying振幅键控 AT&T--American Telephone & Telegraph美国电话电报公司 ATM--Automated Tellermachine自动取款机 --Asynchronous Transfer Mode 异步转移（传递）模式 AU--Administration Unit管理单元 AUG--Administration Unit Group管理单元群 B BCD--Binary Coded Decimal二十进制