高速MOS驱动电路设计和应用指南

浅析MOSFET 高速驱动器电路设计赵云（船舶重工集团公司723所，扬州225 l ）摘要通过对M O SFET 转换过程的分析，得出高速转换过程对驱动电路的要求。

通过对转换过程中功率损耗的计算和驱动电流计算的注意事项，得出了在设计高速驱动M O SFET 电路过程中的要点。

这对用开关电源设计M O SFET 的高速驱动电路有参考价值。

关键词M O SFET驱动电路功率损耗引言开关电源的发展趋势是工作频率越来越高。

国外发达国家的实用频率已接近或超过l MH Z ，我国目前实用频率为5 !l k H Z 。

要提高工作频率，驱动电路的设计选型尤为重要，因此在MH Z 范围工作的高速MO SFET 的过渡过程就成为整个开关过程的重要部分。

过渡过程太慢不仅影响工作频率的提高，而且对开关电源的效率、寿命等产生严重影响。

本文就工程研制中高速驱动电路的设计考虑加以分析。

l高速转换过程分析MO SFET l 个周期的高速转换过程有2个：一为导通转换过程，二为关断转换过程。

（l ）导通转换过程的漏源电压与漏极电流，栅源电压与电荷关系分别如图l 所示。

（a ）m !m l 区间：栅极电压从 上升到门限电压V g s ，称作延迟时间。

在这一区间MO SFET 上的电压、电流都不变化。

（b ）m l !m 2区间：栅极电压达到V g s 的m l 时刻开始，漏极电流开始增长，至m 2时刻I d 达到最大值。

在这一过程中，栅源电压也在上升，而漏源电压将保持截止时的高水平不变。

在这一过程中，由于电压与电流重叠，MO SFET 功耗最大。

图l截止导通转换过程波形（c ）m 2!m 3区间：从m 2时刻开始，MO SFET 漏源电压开始下降，引起从漏极到栅极的密勒电容效应，使得栅极电压不能上升而出现平台，在m 3时刻源漏电压下降到最小值。

（d ）m 3!m 4区间：在这一区间栅极电压从平台上升到最后的驱动电压。

上升的栅压使漏源电阻R ds （On ）减小，m 4以后MOSFET 进入导通状态。

MOSFET高速驱动设计英飞凌MOSFET驱动MOSFET并联摘要：本文阐述了MOSFET驱动的基本要求以及在各种应用中如何优化驱动电路的设计关键词： MOSFET 驱动， MOSFET 并联1．引言随着电源高效，高功率密度的要求，电源的频率由原来的工频，到几十千赫兹，再到如今几百千赫兹甚至兆赫兹。

电源频率的要求越来越高。

如何选择合适的MOSFET, 如何有效的驱动高速的MOSFET，提升电源效率是广大工程师面临的问题。

本文将探讨MOSFET的选型以及高速驱动线路的设计的注意事项。

2．MOSFET结构以及影响驱动的相关参数图1图1是MOSFET的电容等效图。

MOSFET包含3个等效结电容Cgd, Cgs和 Cds.通常在MOSFET的规格书中我们可以看到以下参数其中Ciss=Cgs+CgdCoss=Cgd+CdsCrss=Cgd这些结电容影响着MOSFET开通和关闭速度。

结电容小的MOSFET具有快速的开关速度，可以降低MOSFET开通和关闭时所产生的损耗。

同时对驱动线路需求更低。

但是值得注意的是这些电容跟普通的电容并不完全相同，普通电容的容值并不会有太大的改变，而MOSFET等效电容容值会随着MOSFET Vds的变化而变化。

图2描述了MOSFET 结电容随电压的变化状况。

图2由于Q=C*U*t为了方便计算MOSFET所需的驱动功率以及开关损耗，规格书中通常会给出MOSFET 的Q值。

图3中描述了MOSFET开通的过程以及不同的Qg值对MOSFET开通过程中的影响。

Qgs 是Cgs的电荷量，Qgd是Cgd的电荷量，而整个开通过程中电荷量的总和我们称之为Qg.图3 2.1 MOSFET导通时序介绍t1阶段此阶段处于MOSFET死区时间。

MOSFET电压电流并无变化t2阶段t2阶段MOSFET Vgs电压达到阀值并继续上升。

此时MOSFET开始导通，电流从MOSFET 漏极流向源极并在t2结束时到达最大值，而Vds此时保持不变。

MOS管工作原理及其驱动电路MOS管（金属-氧化物-半导体场效应管）是一种广泛应用于电子电路中的半导体器件。

它的工作原理基于PN结和增强型场效应晶体管（JFET）的特性，但却具有更高的输入阻抗、更低的功耗和更好的高频特性。

MOS管由三个主要组成部分构成：栅极（G），漏极（D）和源极（S）。

在工作原理方面，MOS管的栅极主要用于控制漏极和源极之间的电流流动，而这个控制过程在固有电荷的作用下进行。

MOS管具有两种不同的工作方式：增强型和耗尽型。

增强型MOS管是最常用的类型，在没有栅极电压的情况下，其通道是关闭的。

通过施加正向栅极电压，源极到漏极之间的电流流动开始增加。

电流的增加程度取决于施加的栅极电压。

耗尽型MOS管则是通过施加负向栅极电压来控制电流的，其工作原理与增强型相似，只是电压的极性相反。

为了对MOS管进行驱动，需要合适的驱动电路。

驱动电路主要包括电源、信号发生器、输入阻抗匹配电路和输出驱动电路。

在驱动电路中，其中最重要的是输入信号的幅度和频率与MOS管的特性进行匹配。

在MOS管的驱动电路中，输入信号通常通过信号发生器提供。

信号发生器的输出通常是一个方波或脉冲信号，其幅度和频率需要与MOS管的特性相匹配。

信号发生器的输出通过输入阻抗匹配电路来匹配MOS管的输入阻抗，以确保输入信号的准确传递。

输入阻抗匹配电路通常包括电阻、电容和电感等元件，用于提供合适的输入阻抗。

电阻和电容用于匹配信号发生器和MOS管之间的阻抗，而电感则用于提供必要的补偿和滤波。

输出驱动电路用于提供足够的功率和电流来驱动MOS管的栅极。

输出驱动电路通常包括驱动晶体管和功率放大器等元件。

驱动晶体管用于放大输入信号，并通过功率放大器将信号放大成足够的功率和电流来驱动MOS 管的栅极。

总之，MOS管是一种重要的半导体器件，其工作原理基于PN结和增强型场效应晶体管。

为了驱动MOS管，需要合适的驱动电路来匹配输入信号和MOS管的特性。

输入信号通过信号发生器和输入阻抗匹配电路进行匹配，而输出驱动电路则提供足够的功率和电流来驱动MOS管的栅极。

mos运算放大器——原理、设计与应用摩斯运算放大器是一种专门用于摩斯信号放大的电子设备。

它的原理是通过对输入的摩斯代码进行放大和驱动，从而实现信号的放大和扩展。

在摩斯电码通信中，摩斯代码是由短信和长信组成的，需要通过摩斯运算放大器来将其转化为可以听到或观察到的信号。

摩斯运算放大器的设计基于放大器、驱动电路以及相应的控制电路。

放大器主要负责放大输入的摩斯代码信号，驱动电路负责将放大后的信号驱动到输出设备上，控制电路负责监听输入信号并根据其转化为相应的驱动信号控制器件的工作状态。

在摩斯运算放大器的设计中，放大器的设计是一个关键环节。

放大器需要具备较高的增益和带宽，以确保输入的摩斯代码能够准确地被放大。

一般情况下，放大器可以采用晶体管或集成电路等元件组成。

为了保证放大器的稳定性和可靠性，在设计中需要考虑放大器的输入和输出阻抗匹配、温度漂移等因素。

摩斯运算放大器的应用主要集中在无线通信、航空航天等领域。

在无线通信中，摩斯运算放大器可以用于摩斯电码信号的放大和扩展，使得信号能够在较远距离传输。

在航空航天中，摩斯运算放大器可以用于对摩斯代码信号进行放大和处理，以便在航空器、卫星等场景中进行通信和指令的传递。

摩斯运算放大器的设计和应用也有很多挑战和优化的空间。

在设计上，需要考虑信号的失真、噪声干扰等因素，以提高放大器的性能。

在应用中，需要考虑信号的传输距离、抗干扰能力等因素，以确保摩斯代码信号能够准确地被接收和识别。

此外，随着数字通信技术的发展，摩斯运算放大器也面临着与数字信号处理、调制解调等技术的结合，以适应现代通信的需求。

总之，摩斯运算放大器是一种专门用于摩斯信号放大的电子设备。

它的设计和应用是一个综合考虑放大器、驱动电路和控制电路等因素的过程。

摩斯运算放大器在无线通信、航空航天等领域具有重要的应用价值，同时也面临着技术的挑战和发展的机遇。

高速MOSFET门极驱动电路的设计应用指南author Laszlo Baloghtranslator Justin Hu摘要本文主要演示了一种系统化的方法来设计高速开关装置的高性能门极驱动电路。

文章收集了大量one-stop-shopping 主题的信息来解决最普通的设计挑战。

因此它应当对各种水平的电力电子工程师都适用。

最常用的电路方案和它们的性能都经过了分析，包括寄生参数、瞬时和极端运行条件的影响。

文章首先回顾了MOSFET技术和开关运行模式，然后由简入繁地讨论问题。

详细的描述了参考地和高端门极驱动电路的设计程序、交流耦合和变压器隔离方案。

专门的一章用来介绍同步整流装置中MOSFET的门极驱动要求。

文章另举出了几个设计的实例，一步一步进行了说明。

Ⅰ.引言MOSTET是金属氧化物半导体场效应晶体管(Metal Oxide Semiconductor Field Effect Transistor)的缩写，是电子工业中高频、高效率开关装置的关键器件。

令人惊叹的是，场效应晶体管技术发明于1930年，比双极性晶体管早了大约20年。

第一个信号级别的场效应晶体管20世纪50年代末期被制造出来，功率级别的MOSFET在20世纪70年代中期出现。

而今天无数的MOSFET被集成到现代电子器件中，无论是微处理器还是分立的功率晶体管。

本文所关注的是功率MOSFET在各种各样的开关模式功率变换器装置中门极驱动的要求。

Ⅱ.MOSFET技术双极型和MOSFET晶体管都使用了同样的工作原理。

从根本上讲，这两种晶体管都是电荷控制的器件，这就意味着它们的输出电流和控制电极在半导体中建立的电荷成比例。

当这些器件用作开关时，它们都必须被一个低阻抗的电源驱动，电源要能提供足够的充放电电流来使它们快速建立或释放控制电荷。

从这一点来看，MOSFET在开关过程中必须和双极性晶体管一样通过“硬”驱动才能获得类似的开关速度。

理论上，双极型和MOSFET器件的开关速度几乎一样，由载流子运动经过半导体区域所需要的时间决定。

重点讲解MOS管驱动电路详解一、MOS管驱动电路综述在使用MOS管设计开关电源或者马达驱动电路的时候，大部分人都会考虑MOS的导通电阻，最大电压等，最大电流等，也有很多人仅仅考虑这些因素。

这样的电路也许是可以工作的，但并不是优秀的，作为正式的产品设计也是不允许的。

1、MOS管种类和结构MOSFET管是FET的一种(另一种是JFET)，可以被制造成增强型或耗尽型，P沟道或N沟道共4种类型，但实际应用的只有增强型的N沟道MOS管和增强型的P沟道MOS管，所以通常提到NMOS，或者PMOS指的就是这两种。

至于为什么不使用耗尽型的MOS管，不建议刨根问底。

对于这两种增强型MOS管，比较常用的是NMOS。

原因是导通电阻小，且容易制造。

所以开关电源和马达驱动的应用中，一般都用NMOS。

下面的介绍中，也多以NMOS为主。

MOS管的三个管脚之间有寄生电容存在，这不是我们需要的，而是由于制造工艺限制产生的。

寄生电容的存在使得在设计或选择驱动电路的时候要麻烦一些，但没有办法避免，后边再详细介绍。

在MOS管原理图上可以看到，漏极和源极之间有一个寄生二极管。

这个叫体二极管，在驱动感性负载(如马达)，这个二极管很重要。

顺便说一句，体二极管只在单个的MOS管中存在，在集成电路芯片内部通常是没有的。

2、MOS管导通特性导通的意思是作为开关，相当于开关闭合。

NMOS的特性，Vgs大于一定的值就会导通，适合用于源极接地时的情况(低端驱动)，只要栅极电压达到4V或10V就可以了。

PMOS的特性，Vgs小于一定的值就会导通，适合用于源极接VCC时的情况(高端驱动)。

但是，虽然PMOS可以很方便地用作高端驱动，但由于导通电阻大，价格贵，替换种类少等原因，在高端驱动中，通常还是使用NMOS。

3、MOS开关管损失不管是NMOS还是PMOS，导通后都有导通电阻存在，这样电流就会在这个电阻上消耗能量，这部分消耗的能量叫做导通损耗。

选择导通电阻小的MOS管会减小导通损耗。

高速MOS驱动电路设计和应用指南摘要本篇论文的主要目的是来论证一种为高速开关应用而设计高性能栅极驱动电路的系统研究方法。

它是对“一站买齐”主题信息的收集，用来解决设计中最常见的挑战。

因此，各级的电力电子工程师对它都应该感兴趣。

对最流行电路解决方案和他们的性能进行了分析，这包括寄生部分的影响、瞬态的和极限的工作情况。

整篇文章开始于对MOSFET技术和开关工作的概述，随后进行简单的讨论然后再到复杂问题的分析。

仔细描述了设计过程中关于接地和高边栅极驱动电路、AC耦合和变压器隔离的解决方案。

其中一个章节专门来解决同步整流器应用中栅极驱动对MOSFET的要求。

另外，文章中还有一些一步一步的参数分析设计实例。

简介MOSFET是Metal Oxide Semiconductor Field Effect Transistor的首字母缩写，它在电子工业高频、高效率开关应用中是一种重要的元件。

或许人们会感到不可思议，但是FET是在1930年，大约比双极晶体管早20年被发明出来。

第一个信号电平FET晶体管制成于二十世纪60年代末期，而功率MOSFET是在二十世纪80年代开始被运用的。

如今,成千上万的MOSFET晶体管集成在现代电子元件,从微型的到“离散”功率晶体管。

本课题的研究重点是在各种开关模型功率转换应用中栅极驱动对功率MOSFET 的要求。

场效应晶体管技术双极晶体管和场效应晶体管有着相同的工作原理。

从根本上说,，两种类型晶体管均是电荷控制元件，即它们的输出电流和控制极半导体内的电荷量成比例。

当这些器件被用作开关时，两者必须和低阻抗源极的拉电流和灌电流分开，用以为控制极电荷提供快速的注入和释放。

从这点看，MOS-FET在不断的开关，当速度可以和双极晶体管相比拟时，它被驱动的将十分的‘激烈’。

理论上讲，双极晶体管和MOSFET的开关速度是基本相同的，这取决与载流子穿过半导体所需的时间。

在功率器件的典型值为20 ~ 200皮秒，但这个时间和器件的尺寸大小有关。

高速MOSFET门极驱动电路的设计应用指南author Laszlo Balogh translator Justin Hu摘要本文主要演示了一种系统化的方法来设计高速开关装置的高性能门极驱动电路。

文章收集了大量one-stop-shopping 主题的信息来解决最普通的设计挑战。

因此它应当对各种水平的电力电子工程师都适用。

最常用的电路方案和它们的性能都经过了分析，包括寄生参数、瞬时和极端运行条件的影响。

文章首先回顾了MOSFET技术和开关运行模式，然后由简入繁地讨论问题。

详细的描述了参考地和高端门极驱动电路的设计程序、交流耦合和变压器隔离方案。

专门的一章用来介绍同步整流装置中MOSFET的门极驱动要求。

文章另举出了几个设计的实例，一步一步进行了说明。

Ⅰ.引言MOSTET是金属氧化物半导体场效应晶体管(Metal Oxide Semiconductor Field Effect Transistor)的缩写，是电子工业中高频、高效率开关装置的关键器件。

令人惊叹的是，场效应晶体管技术发明于1930年，比双极性晶体管早了大约20年。

第一个信号级别的场效应晶体管20世纪50年代末期被制造出来，功率级别的MOSFET在20世纪70年代中期出现。

而今天无数的MOSFET被集成到现代电子器件中，无论是微处理器还是分立的功率晶体管。

本文所关注的是功率MOSFET在各种各样的开关模式功率变换器装置中门极驱动的要求。

Ⅱ.MOSFET技术双极性和MOSFET晶体管都使用了同样的工作原理。

从根本上讲，这两种晶体管都是电荷控制的器件，这就意味着它们的输出电流和控制电极在半导体中建立的电荷成比例。

当这些器件用作开关时，它们都必须被一个低阻抗的电源驱动，电源要能提供足够的充放电电流来使它们快速建立或释放控制电荷。

从这一点来看，MOSFET在开关过程中必须和双极性晶体管一样通过“硬”驱动才能获得类似的开关速度。

理论上，双极性和MOSFET器件的开关速度几乎一样，由载流子运动经过半导体区域所需要的时间决定。

高速MOSFEMOSFET T栅极驱动电路的设计与应用指南摘要本文将展示一个用来设计高速开关应用所需的高性能栅极驱动电路的系统性方案。

它综合了各方面的信息，可一次性解决一些最常见的设计问题。

因此，各个层面的电力电子工程师都值得一读。

文中分析了一些最流行的电路方案及其性能，包括寄生元件、瞬间和极端工作条件的影响。

首先，文章对MOSFET技术和开关操作进行了大致讨论，从简单问题逐渐转向复杂问题，并详细讲述了低端和高端栅极驱动电路以及交流耦合和变压器隔离式方案的设计程序。

另外，文章还专门用一个章节的内容来讨论同步整流器应用中MOSFET的栅极驱动要求。

最后，本文还提供了多个分步骤的设计案例。

简介MOSFET，全称为金属氧化物半导体场效应晶体管，是电子产品领域各种高频高效开关应用的关键元器件。

FET技术发明于1930年，比双极晶体管还要早大约20年，这一点令人感到意外。

最早的信号级FET晶体管出现在20世纪50年代末，而功率MOSFET则是在70年代中期问世的。

如今，数百万的MOSFET 晶体管被集成到了各种电子元器件中，从微控制器到“离散式”功率晶体管。

本话题的重点在于各种开关模式电源转换应用中功率MOSFET的栅极驱动要求。

Design And Application GuideFor High Speed MOSFET Gate Drive CircuitsBy Laszlo BaloghABSTRACTThe main purpose of this paper is to demonstrate a systematic approach to design high performance gate drive circuits for high speed switching applications. It is an informative collection of topics offering a “one-stop-shopping” to solve the most common design challenges. Thus it should be of interest to power electronics engineers at all levels of experience.The most popular circuit solutions and their performance are analyzed, including the effect of parasitic components, transient and extreme operating conditions. The discussion builds from simple to more complex problems starting with an overview of MOSFET technology and switching operation. Design procedure for ground referenced and high side gate drive circuits, AC coupled and transformer isolated solutions are described in great details. A special chapter deals with the gate drive requirements of the MOSFETs in synchronous rectifier applications.Several, step-by-step numerical design examples complement the paper.INTRODUCTIONMOSFET – is an acronym for Metal Oxide Semiconductor Field Effect Transistor and it is the key component in high frequency, high efficiency switching applications across the electronics industry. It might be surprising, but FET technology was invented in 1930, some 20 years before the bipolar transistor. The first signal level FET transistors were built in the late 1950’s while power MOSFETs have been available from the mid 70’s. Today, millions of MOSFET transistors are integrated in modern electronic components, from microprocessors, through “discrete” power transistors.The focus of this topic is the gate drive requirements of the power MOSFET in various switch mode power conversion applications. MOSFET TECHNOLOGYThe bipolar and the MOSFET transistors exploit the same operating principle. Fundamentally, both type of transistors are charge controlled devices which means that their output current is proportional to the charge established in the semiconductor by the control electrode. When these devices are used as switches, both must be driven from a low impedance source capable of sourcing and sinking sufficient current to provide for fast insertion and extraction of the controlling charge. From this point of view, the MOSFETs have to be driven just as “hard” during turn-on and turn-off as a bipolar transistor to achieve comparable switching speeds. Theoretically, the switching speeds of the bipolar and MOSFET devices are close to identical, determined by the time required for the charge carriers to travel across the semiconductor region. Typical values in power devices are approximately 20 to 200 picoseconds depending on the size of the device. The popularity and proliferation of MOSFET technology for digital and power applications is driven by two of their major advantages over the bipolar junction transistors. One of these benefits is the ease of use of the MOSFET devices in high frequency switching applications. The MOSFET transistors are simpler to drive because their control electrode is isolated from the current conducting silicon, therefore a continuous ON current is not required. Once the MOSFET transistors are turned-on, their drive current is practically zero. Also, the controlling charge and accordingly the storage time in the MOSFET transistors is greatly reduced. This basically1eliminates the design trade-off between on state voltage drop – which is inversely proportional to excess control charge – and turn-off time. As a result, MOSFET technology promises to use much simpler and more efficient drive circuits with significant economic benefits compared to bipolar devices.Furthermore, it is important to highlight especially for power applications, that MOSFETs have a resistive nature. The voltage drop across the drain source terminals of a MOSFET is a linear function of the current flowing in the semiconductor. This linear relationship is characterized by the R DS(on) of the MOSFET and known as the on-resistance. On-resistance is constant for a given gate-to-source voltage and temperature of the device. As opposed to the -2.2mV/°C temperature coefficient of a p-n junction, the MOSFETs exhibit a positive temperature coefficient of approximately 0.7%/°C to 1%/°C. This positive temperature coefficient of the MOSFET makes it an ideal candidate for parallel operation in higher power applications where using a single device would not be practical or possible. Due to the positive TC of the channel resistance, parallel connected MOSFETs tend to share the current evenly among themselves. This current sharing works automatically in MOSFETs since the positive TC acts as a slow negative feedback system. The device carrying a higher current will heat up more – don’t forget that the drain to source voltages are equal – and the higher temperature will increase its R DS(on) value. The increasing resistance will cause the current to decrease, therefore the temperature to drop. Eventually, an equilibrium is reached where the parallel connected devices carry similar current levels. Initial tolerance in R DS(on) values and different junction to ambient thermal resistances can cause significant – up to 30% – error in current distribution.Device typesAlmost all manufacturers have got their unique twist on how to manufacture the best power MOSFETs, but all of these devices on the market can be categorized into three basic device types. These are illustrated in Figure 1.Figure 1. Power MOSFET device types Double-diffused MOS transistors were introduced in the 1970’s for power applications and evolved continuously during the years. Using polycrystalline silicon gate structures and self-aligning processes, higher density integration and rapid reduction in capacitances became possible. The next significant advancement was offered by the V-groove or trench technology to further increase cell density in power MOSFET devices. The better performance and denser integration don’t come free however, as trench MOS devices are more difficult to manufacture.The third device type to be mentioned here is the lateral power MOSFETs. This device type is constrained in voltage and current rating due to its inefficient utilization of the chip geometry. Nevertheless, they can provide significant benefits in low voltage applications, like in microprocessor power supplies or as synchronous rectifiers in isolated converters.2The lateral power MOSFETs have significantly lower capacitances, therefore they can switch much faster and they require much less gate drive power.MOSFET ModelsThere are numerous models available to illustrate how the MOSFET works, nevertheless finding the right representation might be difficult. Mostof the MOSFET manufacturers provide Spice and/or Saber models for their devices, but these models say very little about the application traps designers have to face in practice. They provide even fewer clues how to solve the most common design challenges.A really useful MOSFET model which would describe all important properties of the device from an application point of view would be very complicated. On the other hand, very simple and meaningful models can be derived of the MOSFET transistor if we limit the applicabilityof the model to certain problem areas.The first model in Figure 2 is based on the actual structure of the MOSFET device and can be used mainly for DC analysis. The MOSFET symbol in Figure 2a represents the channel resistance and the JFET corresponds to the resistance of the epitaxial layer. The length, thus the resistance of the epi layer is a function of the voltage rating of the device as high voltage MOSFETs require thicker epitaxial layer.Figure 2b can be used very effectively to model the dv/dt induced breakdown characteristic of a MOSFET. It shows both main breakdown mechanisms, namely the dv/dt induced turn-on of the parasitic bipolar transistor - present in all power MOSFETs - and the dv/dt induced turn-onof the channel as a function of the gate terminating impedance. Modern power MOSFETs are practically immune to dv/dt triggering of the parasitic npn transistor due to manufacturing improvements to reduce the resistance between the base and emitter regions.It must be mentioned also that the parasitic bipolar transistor plays another important role. Its base – collector junction is the famous body diode of the MOSFET.Figure 2. Power MOSFET models34Figure 2c is the switching model of the MOSFET. The most important parasitic components influencing switching performance are shown in this model. Their respective roles will be discussed in the next chapter which is dedicated to the switching procedure of the device.MOSFET Critical ParametersWhen switch mode operation of the MOSFET is considered, the goal is to switch between the lowest and highest resistance states of the device in the shortest possible time. Since the practical switching times of the MOSFETs (~10ns to 60ns) is at least two to three orders of magnitude longer than the theoretical switching time (~50ps to 200ps), it seems important to understand the discrepancy. Referring back to the MOSFET models in Figure 2, note that all models include three capacitors connected between the three terminals of the device. Ultimately, the switching performance of the MOSFET transistor is determined by how quickly the voltages can be changed across these capacitors.Therefore, in high speed switching applications, the most important parameters are the parasitic capacitances of the device. Two of these capacitors, the C GS and C GD capacitors correspond to the actual geometry of the device while the C DS capacitor is the capacitance of the base collector diode of the parasitic bipolar transistor (body diode).The C GS capacitor is formed by the overlap of the source and channel region by the gate electrode. Its value is defined by the actual geometry of the regions and stays constant (linear) under different operating conditions.The C GD capacitor is the result of two effects. Part of it is the overlap of the JFET region and the gate electrode in addition to the capacitance of the depletion region which is non-linear. The equivalent C GD capacitance is a function of the drain source voltage of the device approximated by the following formula:DS1GD,0GD V K 1C C ⋅+≈The C DS capacitor is also non-linear since it is the junction capacitance of the body diode. Its voltage dependence can be described as:DS 2DS,0DS V K C C ⋅≈Unfortunately, non of the above mentioned capacitance values are defined directly in the transistor data sheets. Their values are given indirectly by the C ISS , C RSS , and C OSS capacitor values and must be calculated as: RSSOSS DS RSS ISS GS RSSGD C C C C C C C C −=−== Further complication is caused by the C GD capacitor in switching applications because it is placed in the feedback path between the input and output of the device. Accordingly, its effective value in switching applications can be much larger depending on the drain source voltage of the MOSFET. This phenomenon is called the “Miller” effect and it can be expressed as:()GD L fs eqv GD,C R g 1C ⋅⋅+=Since the C GD and C DS capacitors are voltage dependent, the data sheet numbers are valid only at the test conditions listed. The relevant average capacitances for a certain application have to be calculated based on the required charge to establish the actual voltage change across the capacitors. For most power MOSFETs the following approximations can be useful: offDS,spec DS,spec OSS,ave OSS,off DS,spec DS,spec RSS,ave GD,V V C 2C V V C 2C ⋅⋅=⋅⋅=The next important parameter to mention is the gate mesh resistance, R G,I . This parasitic resistance describes the resistance associated by the gate signal distribution within the device. Its importance is very significant in high speed switching applications because it is in between the driver and the input capacitor of the device, directly impeding the switching times and the5dv/dt immunity of the MOSFET. This effect is recognized in the industry, where real high speed devices like RF MOSFET transistors use metal gate electrodes instead of the higher resistance polysilicon gate mesh for gate signal distribution. The R G,I resistance is not specified in the data sheets, but in certain applications it can be a very important characteristic of the device. In the back of this paper, Appendix A4 shows a typical measurement setup to determine the internal gate resistor value with an impedance bridge.Obviously, the gate threshold voltage is also a critical characteristic. It is important to note that the data sheet V TH value is defined at 25°C and at a very low current, typically at 250μA. Therefore, it is not equal to the Miller plateau region of the commonly known gate switching waveform. Another rarely mentioned fact about V TH is its approximately –7mV/°C temperature coefficient. It has particular significance in gate drive circuits designed for logic level MOSFET where V TH is already low under the usual test conditions. Since MOSFETs usually operate at elevated temperatures, proper gate drive design must account for the lower V TH when turn-off time, and dv/dt immunity is calculated as shown in Appendix A and F.The transconductance of the MOSFET is its small signal gain in the linear region of its operation. It is important to point out that every time the MOSFET is turned-on or turned-off, it must go through its linear operating mode where the current is determined by the gate-to-source voltage. The transconductance, g fs , is the small signal relationship between drain current and gate-to-source voltage:GSD fs dV dI g =Accordingly, the maximum current of the MOSFET in the linear region is given by: ()fs th GS D g V V I ⋅−=Rearranging this equation for V GS yields the approximate value of the Miller plateau as a function of the drain current.fs D th Miller GS,g IV V +=Other important parameters like the source inductance (L S ) and drain inductance (L D ) exhibit significant restrictions in switching performance. Typical L S and L D values are listed in the data sheets, and they are mainly dependant on the package type of the transistor. Their effects can be investigated together with the external parasitic components usually associated with layout and with accompanying external circuit elements like leakage inductance, a current sense resistor, etc.For completeness, the external series gate resistor and the MOSFET driver’s output impedance must be mentioned as determining factors in high performance gate drive designs as they have a profound effect on switching speeds and consequently on switching losses.SWITCHING APPLICATIONSNow, that all the players are identified, let’s investigate the actual switching behavior of the MOSFET transistors. To gain a better understanding of the fundamental procedure, the parasitic inductances of the circuit will be neglected. Later their respective effects on the basic operation will be analyzed individually. Furthermore, the following descriptions relate to clamped inductive switching because most MOSFET transistors and high speed gate drive circuits used in switch mode power supplies work in that operating mode.Figure 3. Simplified clamped inductive switchingmodelThe simplest model of clamped inductive switching is shown in Figure 3, where the DC current source represents the inductor. Its current can be considered constant during the short switching interval. The diode provides a path for the current during the off time of the MOSFET and clamps the drain terminal of the device to the output voltage symbolized by the battery.Turn-On procedureThe turn-on event of the MOSFET transistor can be divided into four intervals as depicted in Figure 4.Figure 4. MOSFET turn-on time intervalsIn the first step the input capacitance of the device is charged from 0V to V TH. During this interval most of the gate current is charging the C GS capacitor. A small current is flowing through the C GD capacitor too. As the voltage increases at the gate terminal and the C GD capacitor’s voltage has to be slightly reduced. This period is called the turn-on delay, because both the drain current and the drain voltage of the device remain unchanged.Once the gate is charged to the threshold level, the MOSFET is ready to carry current. In the second interval the gate is rising from V TH to the Miller plateau level, V GS,Miller. This is the linear operation of the device when current is proportional to the gate voltage. On the gate side, current is flowing into the C GS and C GD capacitors just like in the first time interval and the V GS voltage is increasing. On the output side of the device, the drain current is increasing, while the drain-to-source voltage stays at the previous level (V DS,OFF). This can be understood looking at the schematic in Figure 3. Until all the current is transferred into the MOSFET and the diode is turned-off completely to be able to block reverse voltage across its pn junction, the drain voltage must stay at the output voltage level. Entering into the third period of the turn-on procedure the gate is already charged to the sufficient voltage (V GS,Miller) to carry the entire load current and the rectifier diode is turned off. That now allows the drain voltage to fall. While the drain voltage falls across the device, the gate-to-source voltage stays steady. This is the Miller plateau region in the gate voltage waveform. All the gate current available from the driver is diverted to discharge the C GD capacitor to facilitate the rapid voltage change across the drain-to-source terminals. The drain current of the device stays constant since it is now limited by the external circuitry, i.e. the DC current source.The last step of the turn-on is to fully enhance the conducting channel of the MOSFET by applying a higher gate drive voltage. The final amplitude of V GS determines the ultimate on-resistance of the device during its on-time. Therefore, in this fourth interval, V GS is increased from V GS,Miller to its final value, V DRV. This is accomplished by charging the C GS and C GD capacitors, thus gate current is now split between the two components. While these capacitors are being charged, the drain current is still constant, and the drain-to-source voltage is slightly decreasing as the on-resistance of the device is being reduced.6Turn-Off procedureThe description of the turn-off procedure for the MOSFET transistor is basically back tracking the turn-on steps from the previous section. Start with V GS being equal to V DRV and the current in the device is the full load current represented by I DC in Figure 3. The drain-to-source voltage is being defined by I DC and the R DS(on) of the MOSFET. The four turn-off steps are shown in Figure 5. for completeness.Figure 5. MOSFET turn-off time intervals The first time interval is the turn-off delay which is required to discharge the C ISS capacitance from its initial value to the Miller plateau level. During this time the gate current is supplied by the C ISS capacitor itself and it is flowing through the C GS and C GD capacitors of the MOSFET. The drain voltage of the device is slightly increasing as the overdrive voltage is diminishing. The current in the drain is unchanged.In the second period, the drain-to-source voltage of the MOSFET rises from I D⋅R DS(on) to the final V DS(off) level, where it is clamped to the output voltage by the rectifier diode according to the simplified schematic of Figure 3. During this time period – which corresponds to the Miller plateau in the gate voltage waveform - the gate current is strictly the charging current of the C GDcapacitor because the gate-to-source voltage is constant. This current is provided by the bypass capacitor of the power stage and it is subtracted from the drain current. The total drain current still equals the load current, i.e. the inductor current represented by the DC current source in Figure 3.The beginning of the third time interval is signified by the turn-on of the diode, thus providing an alternative route to the load current.The gate voltage resumes falling from V GS,Miller to V TH. The majority of the gate current is coming out of the C GS capacitor, because the C GDcapacitor is virtually fully charged from the previous time interval. The MOSFET is in linear operation and the declining gate-to-source voltage causes the drain current to decrease and reach near zero by the end of this interval.Meanwhile the drain voltage is steady at V DS(off)due to the forward biased rectifier diode.The last step of the turn-off procedure is to fully discharge the input capacitors of the device. V GSis further reduced until it reaches 0V. The bigger portion of the gate current, similarly to the third turn-off time interval, supplied by the C GScapacitor. The drain current and the drain voltage in the device are unchanged.Summarizing the results, it can be concluded that the MOSFET transistor can be switched between its highest and lowest impedance states (either turn-on or turn-off) in four time intervals. The lengths of all four time intervals are a function of the parasitic capacitance values, the required voltage change across them and the available gate drive current. This emphasizes the importance of the proper component selection and optimum gate drive design for high speed, high frequency switching applications.7Characteristic numbers for turn-on, turn-off delays, rise and fall times of the MOSFET switching waveforms are listed in the transistor data sheets. Unfortunately, these numbers correspond to the specific test conditions and to resistive load, making the comparison of different manufacturers’ products difficult. Also, switching performance in practical applications with clamped inductive load is significantly different from the numbers given in the data sheets.Power lossesThe switching action in the MOSFET transistorin power applications will result in some unavoidable losses, which can be divided into two categories.The simpler of the two loss mechanisms is the gate drive loss of the device. As described before, turning-on or off the MOSFET involves chargingor discharging the C ISS capacitor. When the voltage across a capacitor is changing, a certain amount of charge has to be transferred. The amount of charge required to change the gate voltage between 0V and the actual gate drive voltage V DRV, is characterized by the typical gate charge vs. gate-to-source voltage curve in the MOSFET datasheet. An example is shown in Figure 6.Figure 6. Typical gate charge vs. gate-to-sourcevoltage This graph gives a relatively accurate worst case estimate of the gate charge as a function of the gate drive voltage. The parameter used to generate the individual curves is the drain-to-source off state voltage of the device. V DS(off) influences the Miller charge – the area below the flat portion of the curves – thus also, the total gate charge required in a switching cycle. Once the total gate charge is obtained from Figure 6, the gate charge losses can be calculated as:DRVGDRVGATEfQVP⋅⋅=where V DRV is the amplitude of the gate drive waveform and f DRV is the gate drive frequency – which is in most cases equal to the switching frequency. It is interesting to notice that the Q G⋅f DRV term in the previous equation gives the average bias current required to drive the gate. The power lost to drive the gate of the MOSFET transistor is dissipated in the gate drive circuitry. Referring back to Figures 4 and 5, the dissipating components can be identified as the combination of the series ohmic impedances in the gate drive path. In every switching cycle the required gate charge has to pass through the driver output impedances, the external gate resistor, and the internal gate mesh resistance. As it turns out, the power dissipation is independent of how quickly the charge is delivered through the resistors. Using the resistor designators from Figures 4 and 5, the driver power dissipation can be expressed as:OFFDRV,ONDRV,DRVIG,GATELODRVGDRVLOOFFDRV,IG,GATEHIDRVGDRVHIONDRV,PPPRRRfQVR21PRRRfQVR21P+=++⋅⋅⋅⋅=++⋅⋅⋅⋅=In the above equations, the gate drive circuit is represented by a resistive output impedance and this assumption is valid for MOS based gate drivers. When bipolar transistors are utilized in the gate drive circuit, the output impedance becomes non-linear and the equations do not yield the correct answers. It is safe to assume that with low value gate resistors (<5Ω) most gate drive losses are dissipated in the driver. If R GATE is sufficiently large to limit I G below the output89current capability of the bipolar driver, the majority of the gate drive power loss is then dissipated in R GATE .In addition to the gate drive power loss, the transistors accrue switching losses in the traditional sense due to high current and high voltage being present in the device simultaneously for a short period. In order to ensure the least amount of switching losses, the duration of this time interval must be minimized. Looking at the turn-on and turn-off procedures of the MOSFET, this condition is limited to intervals 2 and 3 of the switching transitions in both turn-on and turn-off operation. These time intervals correspond to the linear operation of the device when the gate voltage is between V TH and V GS,Miller , causing changes in the current of the device and to the Miller plateau region when the drain voltage goes through its switching transition.This is a very important realization to properly design high speed gate drive circuits. It highlights the fact that the most important characteristic of the gate driver is its source-sink current capability around the Miller plateau voltage level. Peak current capability, which is measured at full V DRV across the driver’s output impedance, has very little relevance to the actual switching performance of the MOSFET. What really determines the switching times of the device is the gate drive current capability when the gate-to-source voltage, i.e. the output of the driver is at ~5V (~2.5V for logic level MOSFETs).A crude estimate of the MOSFET switching losses can be calculated using simplified linear approximations of the gate drive current, drain current and drain voltage waveforms during periods 2 and 3 of the switching transitions. First the gate drive currents must be determined for the second and third time intervals respectively:()G.I GATE HI MillerGS,DRV G3G.IGATE HI TH Miller GS,DRVG2R R R V V I R R R V V 0.5V I ++−=+++⋅−=Assuming that I G2 charges the input capacitor of the device from V TH to V GS,Miller and I G3 is the discharge current of the C RSS capacitor while the drain voltage changes from V DS(off) to 0V, the approximate switching times are given as:G3offDS,RSS G2THMillerGS,ISS I V C t3I V V C t2⋅=−⋅=During t2 the drain voltage is V DS(off) and the current is ramping from 0A to the load current, I L while in t3 time interval the drain voltage is falling from V DS(off) to near 0V. Again, using linear approximations of the waveforms, the power loss components for the respective time intervals can be estimated:Loff DS,Loff DS,I 2V T t3P32I V T t2P2⋅⋅=⋅⋅=where T is the switching period. The total switching loss is the sum of the two loss components, which yields the following simplifed expression:Even though the switching transitions are well understood, calculating the exact switching losses is almost impossible. The reason is the effect of the parasitic inductive components which will significantly alter the current and voltage waveforms, as well as the switching times during the switching procedures. Taking into account the effect of the different source and drain inductances of a real circuit would result in second order differential equations to describe the actual waveforms of the circuit. Since the variables, including gate threshold voltage, MOSFET capacitor values, driver output impedances, etc. have a very wide tolerance, the above described linear approximation seems to be a reasonable enough compromise to estimate switching losses in the MOSFET.Effects of parasitic componentsThe most profound effect on switching performance is exhibited by the source inductance. There are two sources for parasitic source inductance in a typical circuit, the sourceTt3t22I V P L DS(off)SW +⋅⋅=。