附录：文献翻译
TMS320LF2407, TMS320LF2406, TMS320LF2402
TMS320LC2406, TMS320LC2404, MS320LC2402
DSP CONTROLLERS
The TMS320LF240x and TMS320LC240x devices, new members of the ‘24x family of digital signal processor (DSP) controllers, are part of the C2000 platform of fixed-point DSPs. The ‘240x devices offer the enhanced TMS320 architectural design of the ‘C2xx core CPU for low-cost, low-power, high-performance processing capabilities. Several advanced peripherals, optimized for digital motor and motion control applications, have been integrated to provide a true single chip DSP controller. While code-compatible with the existing ‘24x DSP controller devices, the ‘240x offers increased processing performance (30 MIPS) and a higher level of peripheral integration. See the TMS320x240x device summary section for device-specific features.
The ‘240x family offers an array of memory sizes and different peripherals tailored to meet the specific price/performance points required by various applications. Flash-based devices of up to 32K words offer a reprogrammable solution useful for:
◆Applications requiring field programmability upgrades.
◆Development and initial prototyping of applications that migrate to
ROM-based devices.
Flash devices and corresponding ROM devices are fully pin-to-pin compatible. Note that flash-based devices contain a 256-word boot ROM to facilitate in-circuit programming.
All ‘240x devices offer at least one event manager module which has been optimized for digital motor control and power conversion applications. Capabilities of this module include centered- and/or edge-aligned PWM generation, programmable
deadband to prevent shoot-through faults, and synchronized analog-to-digital conversion. Devices with dual event managers enable multiple motor and/or converter control with a single ?240x DSP controller.
The high performance, 10-bit analog-to-digital converter (ADC) has a minimum conversion time of 500 ns and offers up to 16 channels of analog input. The auto sequencing capability of the ADC allows a maximum of 16 conversions to take place in a single conversion session without any CPU overhead.
A serial communications interface (SCI) is integrated on all devices to provide asynchronous communication to other devices in the system. For systems requiring additional communication interfaces; the ‘2407, ‘2406, and ‘2404 offer a 16-bit synchronous serial peripheral interface (SPI). The ‘2407 and ‘2406 offer a controller area network (CAN) communications module that meets 2.0
B specifications. To maximize device flexibility, functional pins are also configurable as general purpose inputs/outputs (GPIO).
To streamline development time, JTAG-compliant scan-based emulation has been integrated into all devices. This provides non-intrusive real-time capabilities required to debug digital control systems. A complete suite of code generation tools from C compilers to the industry-standard Code Composerdebugger supports this family. Numerous third party developers not only offer device-level development tools, but also system-level design and development support.
PERIPHERALS
The integrated peripherals of the TMS320x240x are described in the following subsections:
●Two event-manager modules (EV A, EVB)
●Enhanced analog-to-digital converter (ADC) module
●Controller area network (CAN) module
●Serial communications interface (SCI) module
●Serial peripheral interface (SPI) module
●PLL-based clock module
●Digital I/O and shared pin functions
●External memory interfaces (‘LF2407 only)
●Watchdog (WD) timer module
Event manager modules (EV A, EVB)
The event-manager modules include general-purpose (GP) timers, full-compare/PWM units, capture units, and quadrature-encoder pulse (QEP) circuits. EV A‘s and EVB‘s timers, compare units, and capture units function identically. However, timer/unit names differ for EV A and EVB. Table 1 shows the module and signal names used. Table 1 shows the features and functionality available for the event-manager modules and highlights EV A nomenclature.
Event managers A and B have identical peripheral register sets with EV A starting at 7400h and EVB starting at 7500h. The paragraphs in this section describe the function of GP timers, compare units, capture units, and QEPs using EV A nomenclature. These paragraphs are applicable to EVB with regard to function—however, module/signal names would differ.
Table 1. Module and Signal Names for EV A and EVB
General-purpose (GP) timers
There are two GP timers: The GP timer x (x = 1 or 2 for EV A; x = 3 or 4 for EVB) includes:
● A 16-bit timer, up-/down-counter, TxCNT, for reads or writes
● A 16-bit timer-compare register, TxCMPR (double-buffered with shadow
register), for reads or writes
● A 16-bit timer-period register, TxPR (double-buffered with shadow
register), for reads or writes
● A 16-bit timer-control register,TxCON, for reads or writes
●Selectable internal or external input clocks
● A programmable prescaler for internal or external clock inputs
●Control and interrupt logic, for four maskable interrupts: underflow,
overflow, timer compare, and period interrupts
● A selectable direction input pin (TDIR) (to count up or down when
directional up-/down-count mode is selected)
The GP timers can be operated independently or synchronized with each other. The compare register associated with each GP timer can be used for compare function and PWM-waveform generation. There are three continuous modes of operations for each GP timer in up- or up/down-counting operations. Internal or external input clocks with programmable prescaler are used for each GP timer. GP timers also provide the time base for the other event-manager submodules: GP timer 1 for all the compares and PWM circuits, GP timer 2/1 for the capture units and the quadrature-pulse counting operations. Double-buffering of the period and compare registers allows programmable change of the timer (PWM) period and the compare/PWM pulse width as needed.
Full-compare units
There are three full-compare units on each event manager. These compare units use GP timer1 as the time base and generate six outputs for compare and PWM-waveform generation using programmable deadband circuit. The state of each of the six outputs is configured independently. The compare registers of the compare units are double-buffered, allowing programmable change of the compare/PWM pulse widths as needed.
Programmable deadband generator
The deadband generator circuit includes three 8-bit counters and an 8-bit compare register. Desired deadband values (from 0 to 24 μs) can be programmed into the compare register for the outputs of the three compare units. The deadband generation can be enabled/disabled for each compare unit output individually. The deadband-generator circuit produces two outputs (with or without deadband zone) for each compare unit output signal. The output states of the deadband generator are configurable and changeable as needed by way of the double-buffered ACTR register.
PWM waveform generation
Up to eight PWM waveforms (outputs) can be generated simultaneously by each event manager: three independent pairs (six outputs) by the three full-compare units with programmable deadbands, and two independent PWMs by the GP-timer compares.
PWM characteristics
Characteristics of the PWMs are as follows:
●16-bit registers
●Programmable deadband for the PWM output pairs, from 0 to 24 μs
●Minimum deadband width of 50 ns
●Change of the PWM carrier frequency for PWM frequency wobbling as
needed
●Change of the PWM pulse widths within and after each PWM period as
needed
●External-maskable power and drive-protection interrupts
●Pulse-pattern-generator circuit, for programmable generation of asymmetric,
symmetric, and four-space vector PWM waveforms
●Minimized CPU overhead using auto-reload of the compare and period
registers
Capture unit
The capture unit provides a logging function for different events or transitions. The values of the GP timer 2 counter are captured and stored in the two-level-deep FIFO stacks when selected transitions are detected on capture input pins, CAPx (x = 1, 2, or 3 for EV A; and x = 4, 5, or 6 for EVB). The capture unit consists of three capture circuits.
Capture units include the following features:
●One 16-bit capture control register, CAPCON (R/W)
●One 16-bit capture FIFO status register, CAPFIFO (eight MSBs are
read-only, eight LSBs are write-only)
●Selection of GP timer 2 as the time base
●Three 16-bit 2-level-deep FIFO stacks, one for each capture unit
●Three Schmitt-triggered capture input pins (CAP1, CAP2, and CAP3)—one
input pin per capture unit. [All inputs are synchronized with the device (CPU)
clock. In order for a transition to be captured, the input must hold at its
current level to meet two rising edges of the device clock. The input pins
CAP1 and CAP2 can also be used as QEP inputs to the QEP circuit.]
●User-specified transition (rising edge, falling edge, or both edges) detection
●Three maskable interrupt flags, one for each capture unit
Enhanced analog-to-digital converter (ADC) module
A simplified functional block diagram of the ADC module is shown in Figure 1. The ADC module consists of a 10-bit ADC with a built-in sample-and-hold (S/H) circuit. Functions of the ADC module include:
●10-bit ADC core with built-in S/H
●Fast conversion time (S/H + Conversion) of 500 ns
●16-channel, muxed inputs
●Autosequencing capability provides up to 16 ―autoconversions‖ in a single
session. Each conversion can be programmed to select any 1 of 16 input
channels
●Sequencer can be operated as two independent 8-state sequencers or as one
large 16-state sequencer (i.e., two cascaded 8-state sequencers)
●Sixteen result registers (individually addressable) to store conversion values
●Multiple triggers as sources for the start-of-conversion (SOC) sequence
?S/W – software immediate start
?EV A – Event manager A (multiple event sources within EV A)
?EVB – Event manager B (multiple event sources within EVB)
?Ext – External pin (ADCSOC)
●Flexible interrupt control allows interrupt request on every end of sequence
(EOS) or every other EOS
●Sequencer can operate in ―start/stop‖ mode, allowing multiple
―time-sequenced triggers‖ to synchronize conversions
●EV A and EVB triggers can operate independently in dual-sequencer mode
●Sample-and-hold (S/H) acquisition time window has separate prescale
control
●Built-in calibration mode
●Built-in self-test mode
The ADC module in the ‘240x has been enhanced to provide flexible interface to event managers A and B. The ADC interface is built around a fast, 10-bit ADC module with total conversion time of 500 ns (S/H + conversion). The ADC module has 16 channels, configurable as two independent 8-channel modules to service event managers A and B. The two independent 8-channel modules can be cascaded to form a 16-channel module. Figure 2 shows the block diagram of the ‘240x ADC module.
The two 8-channel modules have the capability to autosequence a series of conversions, each module has the choice of selecting any one of the respective eight channels available through an analog mux. In the cascaded mode, the autosequencer functions as a single 16-channel sequencer. On each sequencer, once the conversion is complete, the selected channel value is stored in its respective RESULT register. Autosequencing allows the system to convert the same channel multiple times, allowing the user to perform oversampling algorithms. This gives increased resolution over traditional single-sampled conversion results.
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TMS320LF2407, TMS320LF2406, TMS320LF2402
TMS320LC2406, TMS320LC2404, MS320LC2402
数字信号处理控制器
TMS320LF240x和TMS320LC240x系列芯片作为’24x系列DSP控制器的新成员，是C2000平台下的一种定点DSP芯片。’240x芯片为以’C2xx为核心CPU 的增强型的TMS320结构设计提供了低成本、低功耗、高性能处理能力。芯片集成了用以优化电机数字控制应用的一些高级外设，以实现一个真正的单芯片DSP 控制器。与现有的’24x DSP控制芯片编码兼容的通知，’240x系列芯片具有更好的处理能力（30 MIPS）和更高级的集成外设。
’240x系列芯片提供一系列不同的存储空间和不同的外设搭配，以满足各种应用中特殊的性价比要求。高达32K的FLASH存储空间为以下应用提供了可重复编程的解决方案：
◆需要整体编程能力升级的应用
◆移植到基于ROM的设备的应用的开发和初始化
Flash芯片和对应的ROM芯片引脚是完全逐一兼容的。基于flash的芯片包含一个256字节的引导ROM，使在线编程十分便利。
所有的’240x系列芯片至少提供一个用以优化数字控制电机和电源的事件管理模块。该模块可以提供中间和/或边缘排列的PWM发生器，为防止穿透型击穿可编程死区以及同步的A/D转换器。带有双事件管理器的芯片一个DSP芯片就可控制多个电机和/或转换控制器。
高性能的十位模拟-数字转换器（ADC）最低转换时间是500ns，可以提供多达16通道的模拟输入。具有自动排序功能的ADC在一个转换周期内允许最多16次转换而不增加任何CPU开销。
芯片内集成了串行通信接口（SCI）以同系统中的其他设备进行异步通信。对于要求额外通信接口的系统，’2407, ’2406和’2404芯片提供一个16位的同步串行外设接口（SPI）。’2407 和’2406芯片提供控制器局域网通信模块，符合2.0B规范的要求。为了最大化设备的易用性，功能引脚也可配置为通用的I/O接口（GPIO）。
为了开发的流线性，每块芯片都集成了基于SCAN的JATG适配器，这为数字控制系统的调试提供了在线实时调试能力。一整套从C编辑器到工业级的代码编译调试器的工具支持这一系列的芯片。很多第三方开发软件不仅提供设备级的开
发工具，并且支持系统级的设计和开发。
外设
对TMS320x240x系列芯片的集成外设包括：
●两个事件管理模块
●增强型模拟-数字转换（ADC）模块
●控制器局域网（CAN）模块
●串行通信接口（SCI）模块
●基于锁相环的时钟模块
●数字输入/输出以及引脚复用功能
●外部存储器接口（仅’LF2407）
●看门狗（WD）时钟模块
事件管理器模块（EVA,EVB）
事件管理器模块包括通用（GP）定时器、全比较/PWM单元、捕捉单元以及正交编码脉冲（QEP）电路。EVA和EVB的定制器、比较单元以及捕捉单元的功能都是一致的。只是定时器和单元的名称不同。表1列出了所用的模块和信号的名称，列出了事件管理器模块的可用特征与功能，并着重讲解了EVA模块。
事件管理器A和B拥有相同的外围寄存器。EVA的起始地址是7400h，EVB 的起始地址是7500h。本节以EVA为例描述了通用（GP）定时器、比较单元、捕捉单元以及正交编码脉冲（QEP）的功能。EVB模块也有相同的功能，只是模块/信号的名称不同。
表1 EVA与EVB的模块与信号名称
通用定时器
每个事件管理模块包含2个通用定时器：定时器x（对EVA，x=1或2；对EVB，x=3或4）包括：
●一个16位定时器、增减计数的计数器TxCNT，可读写
●一个16位定时器比较寄存器（双缓冲，带影子寄存器）TxCMPR，可读写●一个16位定时器比较寄存器（双缓冲，带影子寄存器）TxPR，可读写
●一个16位定时器控制寄存器TxCON，可读写
●可选择的内部或外部输入时钟
●用于内部或外部时钟输入的可编程的预定标器
●控制和中断逻辑用于四个可屏蔽中断：下溢、溢出、定时器比较和周期中
断
●一个可选择方向的输入引脚(TDIR)（当用双向计数方式时用来选择向上或
向下计数）
每个GP定时器既可以相互独立运行，又可以同步工作。与GP定时器相关的比较寄存器既可用作比较功能，也可用于PWM波形的发生。每个GP定时器在加或加减计数时有三种连续工作的模式。每个GP定时器都拥有可编程预定标的内部或外部输入时钟。GP定时器还向事件管理器的子模块提供时基。GP定时器1向所有比较单元和PWM电路提供时基。GP定时器2/1还向捕捉单元以及正交脉冲计数操作提供时基。周期寄存器和比较寄存器的双缓冲允许根据需要编程修改定时器的周期以及比较/PWM的脉宽。
全比较单元
每个事件管理器模块包含三个全比较单元。这些单元以GP定时器1作为时基，可产生六路输出用于比较和可编程死区电路的PWM波形。这六个输出的状态可以独立配置。比较单元的比较寄存器是双缓冲的，允许依据需要编程控制比较/PWM的脉冲宽度。
可编程死区发生器
死区发生器电路包括三个8位计数器和一个8位比较寄存器，死区时间间隔（0~24 μs）可根据需要编程存入比较寄存器以控制三个比较单元的输出。每个比较单元的死区发生器可以独立的使能或取消。死区产生电路（不论是否有死区空间）对每一比较单元产生两路输出。通过双缓冲的ACTR寄存器，死区发生器的输出状态可根据需要配置或改变。
PWM波形发生器
每个事件管理器可以同时产生多达8路的PWM波形（输出）：有可编程死区功能的三个全比较单元产生三对（6个输出）独立的波形，GP定时器比较产生两
个独立的PWM波形。
脉宽调制电路
脉宽调制电路波形的特征如下：
●16位寄存器
●有从0到24μs的可编程死区发生器控制每一个输出对
●最小死区宽度为50ns
●依据需要可以改变PWM的载波频率
●在每个PWM周期内或之后可依据需要改变PWM的脉冲宽度
●外部可屏蔽的功率驱动保护中断
●脉冲形式发生器电路，用于可编程的对称、非对称以及4个空间矢量PWM
波形产生
●自动重装载的比较和周期寄存器使CPU的负担最小
捕捉单元
此单元可采集每个事件或跳变。当侦查到输入引脚CAPx（对EVA，x=1、2或3；对EVB，x=4、5或6）上有与设定想通的跳变时，GP定时器2的计数值会被存入一个两级的FIFO栈中。捕捉单元由三个捕捉电路构成。
捕捉单元的特征如下：
●一个16位的捕捉控制寄存器CAPCON（可读写）
●一个16位的捕捉FIFO寄存器CAPFIFO（8位MSBs只读，8位LSBs只写）
●以通用GP定时器2作为时基
●3个16位两级深的FIFO，每个捕捉单元一个
●3个施密特触发器（CAP1/2/3），每个捕捉单元一个输入引脚。【所有的
输入与内部CPU时钟同步，为了使跳变被捕获，输入必需在当前电平保
持两个CPU时钟周期。输入引脚CAP1/2和CAP4/5也可用作正交编码脉
冲电路的正交编码脉冲输入】
●用户可定义的跳变检测方式（上升沿、下降沿或任意跳变）
●三个可屏蔽中断标志位，每个捕捉单元一个
增强型模拟-数字转换（ADC）模块
图2是ADC模块的功能框图。通过一个内置抽样和保持电路，ADC模块可进行10位ADC变换。此模块的功能如下：
●带内置采样/保持（S/H）的10位模数转换模块ADC
●转换时间快（采样/保持+转换），金庸500ns
●16个可选择的模拟输入通道
●自动排序功能。一次可执行最多16个通道的“自动转换”，而且每次要
转换的通道都可通过编程选择
●排序器即可当作两个八位的排序器，也可用作一个大的16位排序器（例：
两个级联的八位排序器）
●16个结果寄存器（独立编址），用以存储转换结果
●多个触发器可以启动AD转换：
?S/W - 软件立即启动
?EVA –事件管理器A（在事件管理器A中有多个事件源可以启动AD
转换）
?EVB –事件管理器B（在事件管理器B中有多个事件源可以启动AD
转换）
?外部– ADCSOC引脚
●灵活的中断控制允许在每一个或每隔一个序列结束时产生中断请求
●排序器可以工作在启动/停止模式，允许多个按时间排序的触发源同步
转换
●EVA和EVB各自独立的触发SEQ1和SEQ2(仅在双排序模式)
●采样和保持获取时间窗口有独立的预定标机制
●内置校验模式
●内置自测试模式
’240x的ADC模块已经被加强从而为事件管理器提供了灵活的接口。ADC 接口围绕在一个快速的10位ADC模块旁，总转换时间为500ns（采样/保持+转换）。ADC模块拥有16个通道，可配置为两个独立的8通道模块以服务于事件管理器A和B。两个独立的8通道模块可级联为一个16位的模块。表2为’240x ADC 模块的功能框图。
两个8通道的模块也可将输入自动排序为一系列转换。通过模拟输入选择器，每个模块可选择各自输入的八个通道。在级联模式，可形成一个16通道的自动排序器。在每个排序其中，一旦转换结束，所选择的通道的转换值将会被存入对应的结果寄存器。自动排序功能允许系统多次转换同一通道，允许用户执行过抽样法则。这可使传统的信号抽样转换结果得以增强。
图2 ＇240x ADC模块功能框图