3. Fundmentals of VHDL (2)

VHDL operators
Attention: precedence of operators
Outline
Brief introduction Structure of VHDL Program Basic parts of VHDL program VHDL data types and operators VHDL data objects Basic VHDL statements Testbench Other parts of VHDL
VHDL data objects
Signal:
defined for holding or passing logic values pathway of information from one component to another (from one process to another) Analogous to a wire or a node in hardware (it does have corresponding hardware) All PORTS of an ENTITY are signals by default. Syntax of declaration:
‘NOT’ has the highest precedence. it is evaluated firstly.
And, or, Nand, Nor, Xor, Xnor have the same precedence. They are evaluated in the order in which they are written.
VHDL data objects
Comparison (signal v. s. variable )
Signal is an abstraction of wire in hardware, for connection between components Variable has no corresponding hardware, just for high level computation, or temporal data storage Signal is global, for multiple processes Variable is local, valid in its process only Signal assignment has delay, while variable assignment takes effect immediately. Signal can carry history information, while variable has current value only.
Real Natural /positive Bit Bit_vector character string
Floating point numbers, -1.0E+38~1.0E+38 Subset of integer Logic ‘0’ or ‘1’ Bit vector ASCII code character array
Internal Function Configuration
VHDL data types
Data types predefined by VHDL
Data types Integer Descriptions 4 byte length, from -2,147,483,647 to 2,147,483,647 Comments For representation of bus width, bit operations/logic operations are not permitted, needs range specification
VHDL data objects
Constant:
Application: (entity, architecture, process, package)
Describing constant value, as a global value Representing static data Example: For more readable program Bus width Easier to modify
VHDL data objects
Attention (to signal): Signal values can be changed by signal assignment
(operator ‘<=’) Signal assignment takes effect after a delay. (real circuit phenomena, realistic, it takes time for a signal to pass a wire) Signal assignment in process takes effect only when the process suspends (signal carries history information, and present information, signal assignment in process does not take effect in execution of the process.) operator ‘:=’ is used for initialization
VHDL data types
Data types predefined by VHDL
Data types Descriptions Comments
Boolean
time Severity level
Logic ‘true’ or ‘false’
Unit: fs, ps, ns, us, ms, sec, min, hr, NOTE，WARNING， ERROR，FAILURE
The assignment takes effect immediately
Has no direct analogue in hardware (no corresponding hardware) Valid only in the sequential areas within a process, subprogram ( not within the architecture body)
Digital system design
Lecture 3: Fundamentals of VHDL
C. QING School of EIE. SCUT
Structure of VHDL code:
Physical significance?
Name, Input and output pins
VHDL data objects
Constant:
holding a fixed value of given type. A value must be assigned when declaration. Never changes once declared Syntax:
VHDL data objects
Variable:
defined in process or sub-program (function, procedure) For saving intermediate data or for computation It is local (value hold by variable is local, valid in local process) Syntax:
VHDL data objects
VHDL data object: Holding a value of some specified type Useful to interpret a type of information
Three classes:
Constant: defined to represent a fixed value; Variable: representing the varying value in process or sub-program; Signal: analogous to wire or node
library ieee; use ieee.std_logic_1164.all; entity divider is port ( clk : in std_logic ; q : out std_logic) ; end divider; architecture var of divider is begin process(clk) variable v:integer range 0 to 6; begin if rising_edge(clk) then v:=v+1; if v=6 then q<='1'; v:=0; else q<='0'; end if; end if; end process; end var;
Voltage representation Algorithms Needs range specification Signal value, single quotes Example “1100”, double quotes Case sensitive Simulation reminding
Signal state, bus control, arbitration
Signal delay Program state reminding
VHDL data types
Synthesizable data types
VHDL operators
Operators: arithmetic, logic, relational operations, and others Attention: precedence of operations.
VHDL data objects
VHDL data objects
Signal v. s. Variable:
Example: 1/6 frequency divider design using variable ‘v’ is defined as a variable, it returns to zero immediately once it is ‘6’
Example :
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VHDL data objects
Attention (to variable):
Can be assigned new value multiple times (operator :=) Initialization is optional
What about Constant ?
VHDL operators
Assignment Operators
Logic Operators
VHDL operators
Arithmetic Operators Comparison Operators
Concatenation Operators
& (, , ,) Examples: Z <= x & ‘’1000000’’; -- If x<=‘1’, then z<=‘’11000000’’ Z <= (‘1’, ‘1’, ‘0’, ‘0’, ‘0’, ‘0’, ‘0’, ‘0’,); -- z<= ‘’11000000’’
VHDL operator overloading
Define our own operators using the same name as the pre-defined ones. Example: add an integer to a binary 1-bit number
• First ‘’+’’ is the pre-defined addition operator (add two integers); • Second ‘’+’’ is the overloaded userdefined (add integer and bit)