The Description of AT89S51
1 General Description
The AT89S51 is a low-power, high-performance CMOS 8-bit microcontroller with 4K bytes of In-System Programmable Flash memory. The device is manufactured using Atmel’s high-density nonvolatile memory technology and is compatible with the industry-standard 80C51 instruction set and pinout. The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with In-System Programmable Flash on a monolithic chip, the Atmel AT89S51 is a powerful microcontroller which provides a highly-flexible and cost-effective solution to many embedded control applications.
The AT89S51 provides the following standard features: 4K bytes of Flash, 128 bytes of RAM, 32 I/O lines, Watchdog timer, two data pointers, two 16-bit timer/counters, a five-vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator, and clock circuitry. In addition, the AT89S51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes.
The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port, and interrupt system to continue functioning. The Power-down mode saves the RAM contents but freezes the oscillator, disabling all other chip functions until the next external interrupt or hardware reset.
2 Ports
Port 0 is an 8-bit open drain bi-directional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high-impedance inputs. Port 0 can also be configured to be the multiplexed low-order address/data bus during accesses to external program and data memory. In this mode, P0 has internal pull-ups. Port 0 also receives the code bytes during Flash programming and outputs the code bytes during program verification. External pull-ups are required during program verification.
Port 1 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins, they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (I IL) because of the internal
pull-ups.
Port 1 also receives the low-order address bytes during Flash programming and verification.
Port Pin Alternate Functions
P1.5 MOSI (used for In-System Programming)
P1.6 MOSO (used for In-System Programming)
P1.7 SCK(used for In-System Programming)
Port 2 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins, they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (I IL) because of the internal pull-ups.Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @ DPTR). In this application, Port 2 uses strong internal pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives the high-order address bits and some control signals during Flash programming and verification.
Port 3 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins, they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (I IL) because of the pull-ups. Port 3 receives some control signals for Flash programming and verification. Port 3 also serves the functions of various special features of the AT89S51, as shown in the following table.
Port Pin Alternate Functions
P3.0 RXD(serial input port)
P3.1 TXD(serial output port)
P3.2 INT0(external interrupt 0)
P3.3 INT1(external interrupt 1)
P3.4 T0(timer 0 external input)
P3.5 T1(timer 1 external input)
P3.6 WR(external data memory write strobe)
P3.7 RD(external data memory read strobe)
3 Special Function Registers
A map of the on-chip memory area called the Special Function Register (SFR) space is shown in Table 3-1.
Table 3-1. AT89S51 SFR Map and Reset Values
0F8H 0FFH
0F0H
B
00000000
0F7H
0E8H 0EFH
0E0H
ACC
00000000
0E7H
0D8H 0DFH
0D0H
PSW
00000000
0D7H
0C8H 0CFH 0C0H 0C7H
0B8H
IP
XX000000
0BFH
0B0H
P3
11111111
0B7H
0A8H
IE
0X000000
0AFH
0A0H
P2
11111111
AUXR1
XXXXXXX0
WDTRST
XXXXXXXX
0A7H
98H
SCON
00000000
SBUF
XXXXXXXX
9FH
90H
P1
11111111
97H
88H
TCON
00000000
TMOD
00000000
TL0
00000000
TL1
00000000
TH0
00000000
TH1
00000000
AUXR
XXX00XX
8FH
80H
P0
11111111
SP
00000111
DP0L
00000000
DP0H
00000000
DP1L
00000000
DP1H
00000000
PCON
0XXX0000
87H
Note that not all of the addresses are occupied, and unoccupied addresses may not be implemented on the chip. Read accesses to these addresses will in general return random data, and write accesses will have an indeterminate effect.
User software should not write 1s to these unlisted locations, since they may be
used in future products to invoke new features. In that case, the reset or inactive values of the new bits will always be 0.
Interrupt Registers: The individual interrupt enable bits are in the IE register. Two priorities can be set for each of the five interrupt sources in the IP register.
Table 3-2. AUXR:Auxiliary Register
AUXR Address=8EH Reset Value=XXX00XX0b
Not Bit Addressable
–––WDIDLE DISRTO ––DISALE
Bit 7 6 5 4 3 2 1 0
–Reserved for future expansion
DISALE Disable/Enable ALE
DISALE
Operating Mode
0 ALE is emitted at a constant rate of 1/6 the oscillator frequency
1 ALE is active only during a MOVX or MOVC instruction
DISRTO Disable/Enable Reset-out
DISRTO
0 Reset pin is driven High after WDT times out
1 Reset pin is input only
WDIDLE Disable/Enable WDT in IDLE mode
WDIDLE
0 WDT continues to count in IDLE mode
1 WDT halts counting in IDLE mode
Dual Data Pointer Registers: To facilitate accessing both internal and external data memory, two banks of 16-bit Data Pointer Registers are provided: DP0 at SFR address locations 82H-83H and DP1 at 84H-85H. Bit DPS = 0 in SFR AUXR1 selects DP0 and DPS = 1 selects DP1. The user should always initialize the DPS bit to the appropriate value before accessing the respective Data Pointer Register.
Power Off Flag: The Power Off Flag (POF) is located at bit 4 (PCON.4) in the PCON SFR. POF is set to “1” during power up. It can be set and rest under software control and is not affected by reset.
Table 3-3. AUXR1:Auxiliary Register 1
AUXR1 Address = A2H Reset Value = XXXXXXX0B Not Bit Addressable
–––––––
DPS Bit 7 6 5 4 3 2 1 0
–Reserved for future expansion
DPS Data Pointer Register Select
DPS
0 Selects DPTR Registers DP0L, DP0H
1 Selects DPTR Registers DP1L, DP1H
4 Memory Organization
MCS-51 devices have a separate address space for Program and Data Memory. Up to 64K bytes each of external Program and Data Memory can be addressed.
4.1 Program Memory
If the EA pin is connected to GND, all program fetches are directed to external memory. On the AT89S51, if EA is connected to V CC, program fetches to addresses 0000H through FFFH are directed to internal memory and fetches to addresses 1000H through FFFFH are directed to external memory.
4.2 Data Memory
The AT89S51 implements 128 bytes of on-chip RAM. The 128 bytes are accessible via direct and indirect addressing modes. Stack operations are examples of indirect addressing, so the 128 bytes of data RAM are available as stack space.
5 Watchdog Timer (One-time Enabled with Reset-out)
The WDT is intended as a recovery method in situations where the CPU may be subjected to software upsets. The WDT consists of a 14-bit counter and the Watchdog Timer Reset (WDTRST) SFR. The WDT is defaulted to disable from exiting reset. To enable the WDT, a user must write 01EH and 0E1H in sequence to the WDTRST register (SFR location 0A6H). When the WDT is enabled, it will increment every machine cycle while the oscillator is running. The WDT timeout period is dependent on the external clock frequency. There is no way to disable the WDT except through
reset (either hardware reset or WDT overflow reset). When WDT overflows, it will drive an output RESET HIGH pulse at the RST pin.
5.1 Using the WDT
To enable the WDT, a user must write 01EH and 0E1H in sequence to the WDTRST register (SFR location 0A6H). When the WDT is enabled, the user needs to service it by writing 01EH and 0E1H to WDTRST to avoid a WDT overflow. The 14-bit counter overflows when it reaches 16383 (3FFFH), and this will reset the device. When the WDT is enabled, it will increment every machine cycle while the oscillator is running. This means the user must reset the WDT at least every 16383 machine cycles. To reset the WDT the user must write 01EH and 0E1H to WDTRST. WDTRST is a write-only register. The WDT counter cannot be read or written. When WDT overflows, it will generate an output RESET pulse at the RST pin. The RESET pulse duration is 98xTOSC, where TOSC = 1/FOSC. To make the best use of the WDT, it should be serviced in those sections of code that will periodically be executed within the time required to prevent a WDT reset.
5.2 WDT DURING Power-down and Idle
In Power-down mode the oscillator stops, which means the WDT also stops. While in Power-down mode, the user does not need to service the WDT. There are two methods of exiting Power-down mode: by a hardware reset or via a level-activated external interrupt, which is enabled prior to entering Power-down mode. When Power-down is exited with hardware reset, servicing the WDT should occur as it normally does whenever the AT89S51 is reset. Exiting Power-down with an interrupt is significantly different. The interrupt is held low long enough for the oscillator to stabilize. When the interrupt is brought high, the interrupt is serviced. To prevent the WDT from resetting the device while the interrupt pin is held low, the WDT is not started until the interrupt is pulled high. It is suggested that the WDT be reset during the interrupt service for the interrupt used to exit Power-down mode. To ensure that the WDT does not overflow within a few states of exiting Power-down, it is best to reset the WDT just before entering Power-down mode. Before going into the IDLE mode, the WDIDLE bit in SFR AUXR is used to determine whether the WDT continues to count if enabled. The WDT keeps counting during IDLE (WDIDLE bit = 0) as the default state. To prevent the WDT from resetting the AT89S51 while in IDLE mode, the user should always set up a timer that will periodically exit IDLE, service the WDT, and reenter IDLE mode.
With WDIDLE bit enabled, the WDT will stop to count in IDLE mode and
resumes the count upon exit from IDLE.
6.Interrupts
The AT89S51 has a total of five interrupt vectors: two external interrupts (INT0 and INT1), two timer interrupts (Timers 0 and 1), and the serial port interrupt. These interrupts are all shown in Figure 6-1. Each of these interrupt sources can be individually enabled or disabled by setting or clearing a bit in Special Function Register IE. IE also contains a global disable bit, EA, which disables all interrupts at once.
Note that Table 6-1 shows that bit positions IE.6 and IE.5 are unimplemented. User software should not write 1s to these bit positions, since they may be used in future AT89 products. The Timer 0 and Timer 1 flags, TF0 and TF1, are set at S5P2 of the cycle in which the timers overflow. The values are then polled by the circuitry in the next cycle.
Table 6-1 Interrupt Enable(IE)Register
(MSB) (LSB)
EA––ES ET1 EX1 ET0 EX0 Enable Bit = 1 enables the interrupt.
Enable Bit = 0 disables the interrupt
Symbol Position Function
EA IE.7 Disables all interrupts. If EA = 0, no interrupt is acknowledged.
If EA = 1, each interrupt source is individually enabled or disabled by setting or
clearing its enable bit.
–IE.6 Reserved
–IE.5 Reserved
ES IE.4 Serial Port interrupt enable bit
ET1 IE.3 Timer 1 interrupt enable bit
EX1 IE.2 External interrupt 1 enable bit
ET0 IE.1 Timer 0 interrupt enable bit
EX0 IE.0 External interrupt 0 enable bit
User software should never write 1s to reserved bits, because they may be used in future A T89 products
Figure 6-1 Interrupt Sources
7 Oscillator Characteristics
XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier that can be configured for use as an on-chip oscillator, as shown in Figure 7-1. Either a quartz crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven, as shown in Figure 7-2. There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum voltage high and low time specifications must be observed.
Figure 7-1 Oscillator Connections
Note: pF
2
,1±
30
=for Crystals
pF
C
C10
=for Ceramic Resonators
40±
pF
pF10
Figure 7-2 External Clock Drive Configuration
8 Idle Mode
In idle mode, the CPU puts itself to sleep while all the on-chip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the special function registers remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset.
Note that when idle mode is terminated by a hardware reset, the device normally resumes pro-gram execution from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when idle mode is terminated by a reset, the instruction following the one that invokes idle mode should not write to a port pin or to external memory.
9 Power-down Mode
In the Power-down mode, the oscillator is stopped, and the instruction that invokes Power-down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values until the Power-down mode is terminated. Exit from Power-down mode can be initiated either by a hardware reset or by activation of an enabled external interrupt (INT0 or INT1). Reset redefines the SFRs but does not change the on-chip RAM. The reset should not be activated before VCC is restored to its normal operating level and must be held active long enough to allow the oscillator
to restart and stabilize.
Table 9-1 Status of External Pins During Idle and Power-down Modes
Mode Program Memory ALE PSEN PORT0PORT1 PORT2 PORT3 Idle Internal 1 1 Data Data Data Data Idle External 1 1 Float Data Address Data Power-down Internal 0 0 Data Data Data Data Power-down External 0 0 Float Data Data Data
AT89S51概述
1 一般概述
该AT89S51是一个低功耗，高性能CMOS 8位微控制器,可在4K字节的系统内编程的闪存存储器。该设备是采用Atmel的高密度、非易失性存储器技术和符合工业标准的80C51指令集和引脚。芯片上的Flash程序存储器在系统中可重新编程或常规非易失性内存编程。通过结合通用8位中央处理器的系统内可编程闪存的单芯片， AT89S51是一个功能强大的微控制器提供了高度灵活的和具有成本效益的解决办法，可在许多嵌入式控制中应用。
在AT89S51提供以下标准功能： 4K字节的Flash闪存， 128字节的RAM ，32个 I / O线，看门狗定时器，两个数据指针，两个16位定时器/计数器， 5向量两级中断结构，全双工串行端口，片上振荡器和时钟电路。此外， AT89S51设计了可降至零频率的静态逻辑操作和支持两种软件可选的节电工作模式。
在空闲模式下停止CPU的工作，但允许RAM 、定时器/计数器、串行接口和中断系统继续运行。掉电模式保存RAM中的内容，停止振荡器工作并禁止其它所有部件工作，直到下一个外部中断或硬件复位。
2 端口
P0端口是一个8位漏极开路双向I / O端口。作为一个输出端口，每个引脚可驱动8个TTL输入。对端口写“1”可作为高阻抗输入端用。在访问外部程序和数据存储器时，P0端口也可以配置为复低阶地址/数据总线。在访问期间激活内部上拉电阻。在Flash编程时，PO端口接收指令字节，而在程序校验时，输出指令字节，同时要求外接上拉电阻。
P1端口是一个带内部上拉电阻的8位双向I /O端口。P1端口的输出缓冲级可以驱动四个TTL输入。对端口写“1”，通过内部的上拉电阻把端口拉到高电平，此时可作为输入口。作为输入口时，因为内部存在上拉电阻，某个引脚被外
），Flash编程和程序校验期间，P1接收低8部信号拉低时会输出一个电流（I
IL
位地址。
端口引脚第二功能
P1.5 MOSI(用于ISP编程)
P1.6 MISO（用于ISP编程）
P1.7 SCK(用于ISP编程)
P2端口是一个带有内部上拉电阻的8位双向I/O端口。P2端口的输出缓冲级可驱动（吸收或输出电流）4个TTL输入。对端口写“1”，通过内部的上拉电阻把端口拉到高电平，此时可作输入口。当作输入口使用时，因为内部存在上
拉电阻，某个引脚被外部信号拉低时会输出一个电流（I
IL
）。在访问外部程序存
储器或16位地址的外部数据存储器（例如执行 MOVX @ DPTR指令）时，P2端
口送出高8位地址数据。在访问8位地址的外部数据存储器（例如执行MOVX@Ri
指令）时，P2端口上的内容（即特殊功能寄存器（SFR)区中P2寄存器的内容），在整个访问期间不变。Flash编程或校验时，P2也可接收高位地址和其它控制信号。
P3端口是一组带有内部上拉电阻的8位双向I/O端口。P3端口输出缓冲级
可驱动（吸收或输出电流）4个TTL逻辑门电路。对P3端口写入“1”时，他们
被内部上拉电阻拉高并作为输入端口。当作输入端时，被外部拉低的P2端口将
用上拉电阻输出电流（I
IL
）．Ｐ３端口还接收一些用于Flash闪存编程和程序校
验的控制信号。P3端口可以采用AT89S51的
各种特殊功能，如下表所示。
端口引脚第二功能
P3.0 RXD(串行输入端口)
P3.1 TXD(串行输出端口)
P3.2 INT0(外部中断0)
P3.3 INT1（外部中断1）
P3.4 T0(定时/计数器0外部输入）
P3.5 T1（定时/计数器1外部输入）
P3.6 WR（外部数据存储器写选通）
P3.7 RD（外部数据存储器读选通）
3 特殊功能寄存器
特殊功能寄存器（SFR）的片内空间分布如表3-1所示。
表3-1 AT89S51特殊功能寄存器分布图及复位值
0F8H 0FFH
0F0H
B
00000000
0F7H
0E8H 0EFH
0E0H
ACC
00000000
0E7H
0D8H 0DFH
0D0H
PSW
00000000
0D7H
0C8H
0CFH
0C0H
0C7H
0B8H
IP
XX000000
0BFH
0B0H
P3
11111111
0B7H
0A8H
IE
0X000000
0AFH
0A0H
P2
11111111
AUXR1 XXXXXXX0
WDTRST XXXXXXXX 0A7H
98H
SCON
00000000 SBUF XXXXXXXX
9FH
90H
P1
11111111
97H
88H
TCON
00000000 TMOD 00000000 TL0 00000000 TL1
00000000 TH0
00000000 TH1
00000000 AUXR
XXX00XX
8FH
80H
P0 11111111
SP 00000111
DP0L 00000000
DP0H
00000000 DP1L
00000000 DP1H
00000000
PCON 0XXX0000
87H
值得注意的是，这些地址并没有全部占用，没有占用的地址也不可使用，读
这些地址将得到一个随意的数值。而写这些地址单元不能得到预期的结果。 不要用软件访问这些未定义的单元，这些单元是留作以后产品扩展用途的，复位后这些新的位将为0。
中断寄存器：各个中断控制位于IE 寄存器，5个中断源的中断优先级控制位于IP 寄存器。
表3-2 AUXR 辅助寄存器
AUXR 地址=8EH 复位状态=XXX00XX0B 不可寻址位
– 为将来扩展用途保留位
DISALE ALE 禁止/使能 DISALE 操作模式
– – –
WDIDLE DISRTO – –
DISABLE Bit 7
6
5
4
3
2
1
0 ALE 输出1/6振荡时钟频率脉冲
1 ALE 仅在执行MOVX或MOVC指令期间输出脉冲
DISRTO 禁止/使能复位输出
DISRTO
0 复位引脚在WDT溢出时变高
1 复位引脚仅为输入
WDIDLE 进制/使能IDLE模式的WDT
WDIDLE
0 IDLE模式WDT继续计数
1 IDLE模式WDT停止计数
双数据指针寄存器：为了便于访问内部和外部数据存储器，提供两个16位数据指针寄存器： DP0位于SFR（特殊功能寄存器）区块中的地址82H - 83H和DP1位于84H - 85H 。当SFR中的位DPS = 0选择DP0，而DPS=1则选择DP1 。用户应在访问相应的数据指针寄存器前初始化DPS位。
电源空闲标志：电源空闲标志（POF）在特殊功能寄存器SFR中PCON的第四位（PCON.4）,电源打开时POF置“1”，它可由软件设置睡眠转台并不为复位所影响。
表3-3 AUXR辅助寄存器1
AUXR1 地址=A2H 复位状态=XXXXXXX0B 不可寻址位
–––––––DPS
Bit 7 6 5 4 3 2 1 0
–为将来扩展用途保留位
DPS 数据指针选择位
DPS
0 选择DPTR寄存器DP0L,DP0H
1 选择DPTR寄存器DP1L,DP1H
4 存储器结构
MCS-51单片机内核采用程序存储器和数据存储器空间分开的结构，均具有64KB外部程序和数据的寻址空间。
4.1 程序存储器
如果的EA引脚接地（GND），全部程序都可以执行外部存储器。在AT89S51 ，如果EA连接到电源+（VCC），程序首先执行地址从0000H到FFFH内部存储器，在执行地址从1000H到FFFFH的外部程序存储器。
4.2 数据存储器
AT89S51具有128字节的内部RAM 。这128字节都可以通过直接和间接寻址方式访问，堆栈操作可利用间接寻址方式进行，因此， 128字节都可以可作为堆栈空间。
5 看门狗定时器（WDT）
看门狗定时器（WDT）是为了解决CPU程序运行时可能进入混乱或死循环而设置，它由一个14bit计数器和看门狗定时器复位SFR（WDTRST）构成。外部复位时，看门狗定时器（WDT）默认为关闭状态，要打开WDT，用户必须按顺序将01EH和0E1H写到WDTRST寄存器（SFR地址为0A6H），当启动了WDT，它会随警惕振荡器在每个机器周期计数，除了硬件复位或WDT溢出复位外没有其它方法关闭WDT，当WDT溢出，将使RST引脚输出高电平的复位脉冲。
5.1使用看门狗定时器（WDT）
用户在打开WDT时，需要按次序将01EH和0E1H写到WDTRST寄存器(SFR的地址为0A6H)，当WDT打开后，需要在一定的时候将01EH和0E1H写道WDTRST
寄存器以避免WDT计数溢出。14位WDT计数器达到16383（3FFFH），WDT将溢出并使用器件复位。WDT打开时，它会随着晶体振荡器在每个机器周期计数，这意味着用户必须在小于每个16383机器周期内复位WDT，也即写01EH和0E1H到WDTRST寄存器，WDTRST为只写寄存器。WDT计数器既不可读也不可写，当WDT
溢出时，通常将使RST引脚输出高电平的复位脉冲。复位脉冲持续时间为
98xTosc，而Tosc=1/Fosc(晶体振荡频率)。为使WDT工作最优化，必须在合适的程序代码时间段周期地复位WDT防止WDT溢出。
5.2掉电和空闲模式下的WDT
掉电时期，晶体振荡停止，看门狗定时器也停止。掉电模式下，用户不嗯那个在复位看门狗定时器。有两种方法可以推出掉电模式：硬件复位或通过激活外部中断，当硬件复位退出掉电模式时，处理看门狗定时器可像通常的上电复位一样。当由中断退出掉电模式时则有所不同，中断低电平状态持续到晶体振荡稳定，当中断电平变为高电平事即可相应中断服务。以防止中断误复位，当器件复位，中断引脚持续为低时，看门狗定时器并未开始计数，知道中断引脚被拉高时为止。
这为在掉电模式下的中断执行中断服务程序而设置。为保证看门狗定时器在退出掉电模式时极端情况下不溢出，最好在进入掉电模式前复位看门狗定时器。在进入空闲模式前，看门狗定时器打开时，WDT是否继续计数由SFR中的AUXR的WDIDLE位决定，在IDLE期间（位WDIDLE=0）默认状态是继续计数。为防止AT89S51从空闲模式中复位，用户应该周期性地设置定时器，重新进入空闲模式。
当WDIDLE位被置位，在空闲模式中看门狗定时器将停止计数，直到从空闲(IDLE)模式中退出重新开始计数。
6 中断
AT89S51共有五个中断向量：两个外部中断（ INT0和INT1 ），两个定时器中断（Timer0和Timer1)和一个串行中断。这些中断都如图6-1 。这些中断源各自的禁止和使能位参见特殊功能寄存器的IE。IE也包含总中断控制位EA，EA清0，将关闭所有中断。
值得注意的是表6-1中的IE.6和IE.5没有定义，用户不要访问这些位，它是保留为以后的AT89产品扩展用途。定时器0和定时器1的中断标志TF0和TF1，它是定时器溢出时的S5P2时序周期被置位，该标志保留至下个时序周期。
表6-1 中断控制寄存器（IE）
（MSB） (LSB)
EA ––ES ET1 EX1 ET0 EX0 当bit=1，打开中断
当bit=0，关闭中断
Symbol Position Function
EA IE.7 Ea=0,关闭所有中断
EA=1，各中断源的禁止或使能取决于个中断源控制位的设置
为1或是0
–IE.6 保留
–IE.5 保留
ES IE.4 串行中断使能控制位
ET1 IE.3 定时器1使能控制位
EX1 IE.2 外中断1使能控制位
ET0 IE.1 定时器0使能控制位
EX0 IE.0 外中断0使能控制位
用户不要访问保留位，这些可能是保留给以后的AT89系列产品扩展用途用的。
图6-1 中断源方框图
7 振荡器特性
AT89S51中有一个用于构成内部振荡器的高增益反相放大器，引脚XTAL1和XTAL2分别是该放大器的输入端和输出端。如图7-1所示。外接石英晶体或陶瓷谐振器都可以使用于反馈元件。用户也可以采用外部时钟，在这种情况下，外部时钟接到XTAL1端，即内部时钟发生器的输入端，XTAL2则悬空，如图7-2所示。由于外部时钟信号是通过一个2分频触发器后作为内部时钟信号的，所以对外部时钟信号的占空比没有特殊要求，但是最小高电平持续时间和最大的低电平时序时间应符合产品技术条件的要求。
图7-1 内部振荡电路 注意：石英晶体时，pF pF C C 10302,1±= 陶瓷滤波器，pF pF C C 10402,!±=
图7-2 外部时钟驱动电路
8 空闲模式
在空闲工作模式状态， CPU保持睡眠状态而所有片内的外设仍然保持激活状态，这种方式由软件产生。此时，片内RAM和所有特殊功能寄存器的内特那个保持不变，空闲模式可由任何语序中断的请求或硬件复位终止。
需要注意的是，当由硬件复位来终止空闲工作模式时，CPU通常是从激活空闲模式那条指令的下一条指令开始继续执行程序的，要完成内部复位操作，硬件复位脉冲要保持两个机器周期有效，在这种情况下，内部禁止CPU访问片内RAM,而允许访问其他端口。为了避免在复位结束时可能对端口产生意外写入，激活空闲模式的那条指令的后一条指令不应该是一条对端口或外部存储器的写入指令。
9 掉电模式
在掉线模式下，振荡器停止工作，进入掉电模式的指令是最后一条被执行的指令，片内RAM和特殊功能寄存器的内容在终止掉电模式前被冻结。退出掉电模式的方法是硬件复位或由处于使能状态的外中断INT0和INT1激活。复位后将重新定义全部特殊功能寄存器，但不改变原来RAM中的内容，在VCC恢复到正常工作电平前，复位应无效，且必须保持一定时间以使振荡器重启动并稳定工作。表9-1 空闲和掉电期间外部引脚状态
模式程序存储区ALE PSEN PORT0 PORT1 PORT2 PORT3 空闲模式内部 1 1 数据数据数据数据
空闲模式外部 1 1 浮空数据地址数据
掉电模式内部0 0 数据数据数据数据
掉电模式外部0 0 浮空数据数据数据
AT89C51外文翻译 Description The AT89C51 is a low-power, high-performance CMOS 8-bit microcomputer with 4K bytes of Flash Programmable and Erasable Read Only Memory (PEROM). The device is manufactured using Atmel’s high density nonvolatile memory technology and is compatible with the industry standard MCS-51? instruction-set and pinout. The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with Flash on a monolithic chip, the Atmel AT89C51 is a powerful microcomputer which provides a highly flexible and cost effective solution to many embedded control applications. Features ? Compatible with MCS-51? Products ? 4K Bytes of In-System Reprogrammable Flash Memory – Endurance: 1,000 Write/Erase Cycles ? Fully Static Operation: 0 Hz to 24 MHz ? Three-Level Program Memory Lock ? 128 x 8-Bit Internal RAM ? 32 Programmable I/O Lines ? Two 16-Bit Timer/Counters ? Six Interrupt Sources ? Programmable Serial Channel ? Low Power Idle and Power Down Modes The AT89C51 provides the following standard features: 4K bytes of Flash,128 bytes of RAM, 32 I/O lines, two 16-bit timer/counters, a five vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator and clock circuitry. In addition, the AT89C51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port and interrupt system to continue functioning. The Power-down Mode saves the RAM contents but freezes the oscillator disabling all other chip functions until the next hardware reset.
外文文献： Knowledge of the stepper motor What is a stepper motor： Stepper motor is a kind of electrical pulses into angular displacement of the implementing agency. Popular little lesson: When the driver receives a step pulse signal, it will drive a stepper motor to set the direction of rotation at a fixed angle (and the step angle). You can control the number of pulses to control the angular displacement, so as to achieve accurate positioning purposes; the same time you can control the pulse frequency to control the motor rotation speed and acceleration, to achieve speed control purposes. What kinds of stepper motor sub-： In three stepper motors: permanent magnet (PM), reactive (VR) and hybrid (HB) permanent magnet stepper usually two-phase, torque, and smaller, step angle of 7.5 degrees or the general 15 degrees; reaction step is generally three-phase, can achieve high torque output, step angle of 1.5 degrees is generally, but the noise and vibration are large. 80 countries in Europe and America have been eliminated; hybrid stepper is a mix of permanent magnet and reactive advantages. It consists of two phases and the five-phase: two-phase step angle of 1.8 degrees while the general five-phase step angle of 0.72 degrees generally. The most widely used Stepper Motor. What is to keep the torque (HOLDING TORQUE) How much precision stepper motor? Whether the cumulative： The general accuracy of the stepper motor step angle of 3-5%, and not cumulative.
目录 目录 (1) 函数的使用和熟悉 (4) 实例3：用单片机控制第一个灯亮 (4) 实例4：用单片机控制一个灯闪烁：认识单片机的工作频率 (4) 实例5：将P1口状态分别送入P0、P2、P3口：认识I/O口的引脚功能 (5) 实例6：使用P3口流水点亮8位LED (5) 实例7：通过对P3口地址的操作流水点亮8位LED (6) 实例8：用不同数据类型控制灯闪烁时间 (7) 实例9：用P0口、P1 口分别显示加法和减法运算结果 (8) 实例10：用P0、P1口显示乘法运算结果 (9) 实例11：用P1、P0口显示除法运算结果 (9) 实例12：用自增运算控制P0口8位LED流水花样 (10) 实例13：用P0口显示逻辑"与"运算结果 (10) 实例14：用P0口显示条件运算结果 (11) 实例15：用P0口显示按位"异或"运算结果 (11) 实例16：用P0显示左移运算结果 (11) 实例17："万能逻辑电路"实验 (11) 实例18：用右移运算流水点亮P1口8位LED (12) 实例19：用if语句控制P0口8位LED的流水方向 (13) 实例20：用swtich语句的控制P0口8位LED的点亮状态 (13) 实例21：用for语句控制蜂鸣器鸣笛次数 (14) 实例22：用while语句控制LED (15) 实例23：用do-while语句控制P0口8位LED流水点亮 (16) 实例24：用字符型数组控制P0口8位LED流水点亮 (17) 实例25：用P0口显示字符串常量 (18) 实例26：用P0 口显示指针运算结果 (19) 实例27：用指针数组控制P0口8位LED流水点亮 (19) 实例28：用数组的指针控制P0 口8 位LED流水点亮 (20) 实例29：用P0 、P1口显示整型函数返回值 (21) 实例30：用有参函数控制P0口8位LED流水速度 (22) 实例31：用数组作函数参数控制流水花样 (22) 实例32：用指针作函数参数控制P0口8位LED流水点亮 (23) 实例33：用函数型指针控制P1口灯花样 (25) 实例34：用指针数组作为函数的参数显示多个字符串 (26) 实例35：字符函数ctype.h应用举例 (27) 实例36：内部函数intrins.h应用举例 (27) 实例37：标准函数stdlib.h应用举例 (28) 实例38：字符串函数string.h应用举例 (29) 实例39：宏定义应用举例2 (29) 实例40：宏定义应用举例2 (29) 实例41：宏定义应用举例3 (30)
杭州电子科技大学信息工程学院毕业设计（论文）外文文献翻译 毕业设计（论文）题目用单片机实现的数字时钟电路设计文献综述题目单片机控制系统系电子工程 专业电子信息科学与技术 姓名郭筱楠 班级08091911 学号08919115 指导教师王维平
单片机控制系统 广义地说，微型计算机控制系统（单片机控制系统）是用于处理信息的，这种被用于处理的信息可以是电话交谈，也可以是仪器的读数或者是一个企业的帐户，但是各种情况下都涉及到相同的主要操作：信息的处理、信息的存储和信息的传递。在常规的电子设计中，这些操作都是以功能平台方式组合起来的，例如计数器，无论是电子计数器还是机械计数器，都要存储当前的数值，并且按要求将该数值增加1。一个系统例如采用计数器的电子钟之类的任一系统要使其存储和处理能力遍布整个系统，因为每个计数器都能存储和处理一些数字。 现如今，以微处理器为基础的系统从常规的处理方法中分离了出来，它将信息的处理，信息的存储和信息的传输三个功能分离形成不同的系统单元。这种主要将系统分成三个主要单元的分离方法是冯-诺依曼在20世纪40年代所设想出来的，并且是针对微计算机的设想。从此以后基本上所有制成的计算机都是用这种结构设计的，尽管他们包含着宽广的物理形式与物理结构，但从根本上来说他们均是具有相同基本设计的计算机。 在以微处理器为基础的系统中，处理是由以微处理器为基础的系统自身完成的。存储是利用存储器电路，而从系统中输入和输出的信息传输则是利用特定的输入/输出（I/O）电路。要在一个以微处理器为基础的时钟中找出执行具有计数功能的一个特殊的硬件组成部分是不可能的，因为时间存储在存储器中，而在固定的时间间隔下由微处理器控制增值。但是，规定系统运转过程的软件却规定了包含实现计数器计数功能的单元部分。由于系统几乎完全由软件所定义，所以对微处理器结构和其辅助电路这种看起来非常抽象的处理方法使其在应用时非常灵活。这种设计过程主要是软件工程，而且在生产软件时，就会遇到产生于常规工程中相似的构造和维护问题。 图1.1 微型计算机的三个组成部分 图1.1显示出了微型计算机中这三个单元在一个微处理器控制系统中是如何按照机器中的信息通信方式而联接起来的。该系统由微处理器控制，微处理器能够对其自身的存储器和输入/输出单元的信息传输进行管理。外部的连接部分与
16位二进制数转换成BCD码的的快速算法－51单片机2010-02-18 00:43在做而论道上篇博文中，回答了一个16位二进制数转换成BCD码的问题，给出了一个网上广泛流传的经典转换程序。 程序可见： http: 32.html中的HEX2BCD子程序。 .说它经典，不仅是因为它已经流传已久，重要的是它的编程思路十分清晰，十分易于延伸推广。做而论道曾经利用它的思路，很容易的编写出了48位二进制数变换成16位BCD码的程序。 但是这个程序有个明显的缺点，就是执行时间太长，转换16位二进制数，就必须循环16遍，转换48位二进制数，就必须循环48遍。 上述的HEX2BCD子程序，虽然长度仅仅为26字节，执行时间却要用331个机器周期。.单片机系统多半是用于各种类型的控制场合，很多时候都是需要“争分夺秒”的，在低功耗系统设计中，也必须考虑因为运算时间长而增加系统耗电量的问题。 为了提高整机运行的速度，在多年前，做而论道就另外编写了一个转换程序，程序的长度为81字节，执行时间是81个机器周期，（这两个数字怎么这么巧！）执行时间仅仅是经典程序的！.近来，在网上发现了一个链接： ，也对这个经典转换程序进行了改进，话是说了不少，只是没有实质性的东西。这篇文章提到的程序，一直也没有找到，也难辩真假。 这篇文章好像是选自某个著名杂志，但是在术语的使用上，有着明显的漏洞，不像是专业人员的手笔。比如说文中提到的：
“使用51条指令代码，但执行这段程序却要耗费312个指令周期”，就是败笔。51条指令代码，真不知道说的是什么，指令周期是因各种机型和指令而异的，也不能表示确切的时间。 .下面说说做而论道的编程思路。;----------------------------------------------------------------------- ;已知16位二进制整数n以b15~b0表示，取值范围为0~65535。 ;那么可以写成： ; n = [b15 ~ b0] ;把16位数分解成高8位、低8位来写，也是常见的形式： ; n = [b15~b8] * 256 + [b7~b0] ;那么，写成下列形式，也就可以理解了： ; n = [b15~b12] * 4096 + [b11~b0] ;式中高4位[b15~b12]取值范围为0~15，代表了4096的个数； ;上式可以变形为： ; n = [b15~b12] * 4000 + {[b15~b12] * (100 - 4) + [b11~b0]} ;用x代表[b15~b12]，有： ; n =x * 4000 + {x * (100 - 4) + [b11~b0]} ;即： ; n =4*x (千位) + x (百位) + [b11~b0] - 4*x ;写到这里，就可以看出一点BCD码变换的意思来了。 ;;上式中后面的位：
The Introduction of AT89C51 Description The AT89C51 is a low-power, high-performance CMOS 8-bit microcomputer with 4K bytes of Flash programmable and erasable read only memory (PEROM). The device is manufactured using Atmel’s high-density nonvolatile memory technology and is compatible with the industry-standard MCS-51 instruction set. The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with Flash on a monolithic chip, the Atmel AT89C51 is a powerful microcomputer which provides a highly-flexible and cost-effective solution to many embedded control applications. Function characteristic The AT89C51 provides the following standard features: 4K bytes of Flash, 128 bytes of RAM, 32 I/O lines, two 16-bit timer/counters, one 5 vector two-level interrupt architecture, a full duplex serial port, one-chip oscillator and clock circuitry. In addition, the AT89C51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port and interrupt system to continue functioning. The Power-down Mode saves the RAM contents but freezes the oscillator disabling all other chip functions until the next hardware reset. Pin Description VCC：Supply voltage. GND：Ground.
外文文献一单片机简介 单片机是一种集成在电路芯片，是采用超大规模集成电路技术把具有数据处理能力的中央处理器CPU随机存储器RAM、只读存储器ROM、多种I/O口和中断系统、定时器/计时器等功能（可能还包括显示驱动电路、脉宽调制电路、模拟多路转换器、A/D转换器等电路）集成到一块硅片上构成的一个小而完善的计算机系统。单片机也被称为微控制器（Microcontroller），是因为它最早被用在工业控制领域。单片机由芯片内仅有CPU的专用处理器发展而来。最早的设计理念是通过将大量外围设备和CPU集成在一个芯片中，使计算机系统更小，更容易集成进复杂的而对体积要求严格的控制设备当中。INTEL的Z80是最早按照这种思想设计出的处理器，从此以后，单片机和专用处理器的发展便分道扬镳。 二、单片机的发展趋势 现在可以说单片机是百花齐放，百家争鸣的时期，世界上各大芯片制造公司都推出了自己的单片机，从8位、16位到32位，数不胜数，应有尽有，有与主流C51系列兼容的，也有不兼容的，但它们各具特色，互成互补，为单片机的应用提供广阔的天地。 纵观单片机的发展过程，可以预示单片机的发展趋势，大致有： 1.低功耗CMOS MCS-51系列的8031推出时的功耗达630mW，而现在的单片机普遍都在100mW左右，随着对单片机功耗要求越来越低，现在的各个单片机制造商基本都采用了CMOS(互补金属氧化物半导体工艺)。象80C51就采用了HMOS(即高密度金属氧化物半导体工艺)和CHMOS(互补高密度金属氧化物半导体工艺)。CMOS虽然功耗较低，但由于其物理特征决定其工作速度不够高，而CHMOS则具备了高速和低功耗的特点，这些特征，更适合于在要求低功耗象电池供电的应用场合。所以这种工艺将是今后一段时期单片机发展的主要途径。 2.微型单片化 现在常规的单片机普遍都是将中央处理器(CPU)、随机存取数据存储(RAM)、只读程序存储器(ROM)、并行和串行通信接口，中断系统、定时电路、时钟电路集成在一块单一的芯片上，增强型的单片机集成了如A/D转换器、PMW(脉宽调制电路)、WDT(看门狗)、有些单片机将LCD(液晶)驱动电路都集成在单一的芯片上，这样 单片机包含的单元电路就更多，功能就越强大。甚至单片机厂商还可以根据用户的要求量身定做，制造出具有． 自己特色的单片机芯片。此外，现在的产品普遍要求体积小、重量轻，这就要求单片机除了功能强和功耗低外，还要求其体积要小。现在的许多单片机都具有多种封装形式，其中SMD(表面封装)越来越受欢迎，使得由单片机构成的系统正朝微型化方向发展。 3.主流与多品种共存 现在虽然单片机的品种繁多，各具特色，但仍以80C51为核心的单片机占主流，兼容其结构和指令系统的有PHILIPS公司的产品，ATMEL公司的产品和中国台湾
51 单片机实用程序库 4.1 流水灯 程序介绍：利用P1 口通过一定延时轮流产生低电平 输出，以达到发光二极管轮流亮的效果。实际应用中例如：广告灯箱彩灯、霓虹灯闪烁。 程序实例（LAMP.ASM） ORG 0000H AJMP MAIN ORG 0030H MAIN: 9 MOV A,#00H MOV P1,A ;灭所有的灯 MOV A,#11111110B MAIN1: MOV P1,A ;开最左边的灯 ACALL DELAY ;延时 RL A ;将开的灯向右边移 AJMP MAIN ;循环 DELAY: MOV 30H,#0FFH D1: MOV 31H,#0FFH D2: DJNZ 31H,D2 DJNZ 30H,D1 RET END 4.2 方波输出 程序介绍：P1.0 口输出高电平，延时后再输出低电 平，循环输出产生方波。实际应用中例如：波形发生器。 程序实例（FAN.ASM）： ORG 0000H MAIN: ;直接利用P1.0 口产生高低电平地形成方波////////////// ACALL DELAY SETB P1.0 ACALL DELAY 10 CLR P1.0 AJMP MAIN ;////////////////////////////////////////////////// DELAY: MOV R1,#0FFH DJNZ R1,$ RET
五、定时器功能实例 5.1 定时1 秒报警 程序介绍：定时器1 每隔1 秒钟将p1.o 的输出状态改变1 次，以达到定时报警的目的。实际应用例如：定时报警器。程序实例（DIN1.ASM）： ORG 0000H AJMP MAIN ORG 000BH AJMP DIN0 ;定时器0 入口 MAIN: TFLA G EQU 34H ;时间秒标志，判是否到50 个 0.2 秒，即50*0.2=1 秒 MOV TMOD,#00000001B;定时器0 工作于方式 1 MOV TL0,#0AFH MOV TH0,#3CH ;设定时时间为0.05 秒，定时 20 次则一秒 11 SETB EA ;开总中断 SETB ET0 ;开定时器0 中断允许 SETB TR0 ;开定时0 运行 SETB P1.0 LOOP: AJMP LOOP DIN0: ;是否到一秒//////////////////////////////////////// INCC: INC TFLAG MOV A,TFLAG CJNE A,#20,RE MOV TFLAG,#00H CPL P1.0 ;////////////////////////////////////////////////// RE: MOV TL0,#0AFH MOV TH0,#3CH ;设定时时间为0.05 秒，定时 20 次则一秒 RETI END 5.2 频率输出公式 介绍：f=1/t s51 使用12M 晶振，一个周期是1 微秒使用定时器1 工作于方式0，最大值为65535，以产生200HZ 的频率为例： 200=1/t:推出t=0.005 秒，即5000 微秒,即一个高电
外文资料翻译 STC89C52 processi ng chip Prime features: With MCS - 51 SCM product compatibility, 8K bytes in the system programmable Flash memory, 1000 times CaXie cycle, the static operation: 0Hz ~ 33Hz, triple encryption program memory, 32 programmed I/O port, three 16 timer/counter, the eight uninterrupted dual-career UART serial passage, low power consumption, leisure and fall after fall electric power mode can be awakened and continuous watchdog timer and double-number poin ter, power ide ntifier. Efficacy: characteristics STC89C52 is one kind of low power consumption, high CMOS8 bit micro-co ntroller, 8K in system programmable Flash memory. Use high-de nsity nonv olatile storage tech no logy, and in dustrial 80C51 product in structi on and pin fully compatible. The Flash memory chips allows programs in the system, also suitable for programmable conventional programming. In a single chip, have clever 8 bits CPU and on li ne system programmable Flash, in crease STC89C52 for many embedded control system to provide high vigorous application and useful solutions. STC89C52 has following standard efficacy: 8k byte Flash RAM, 256 bytes, 32 I/O port, the watchdog timer, two, three pointer numerical 16 timer/counter, a 6 vector level 2 continuous structure, the serial port, working within crystals and horological circuit. In addition, 0Hz AT89S52 can drop to the static logic operation, support two software can choose power saving mode. Idle mode, the CPU to stop working, and allows the RAM, timer/c oun ters, serial, continu ous to work. Protectio n asa na patter n, RAM content is survival, vibrators frozen, SCM, until all the work under a continuous or hardware reset. 8-bit microcontrollers 8K bytes in the system programmable Flash AT89S52 devices. Mouth: P0 P0 mouth is a two-way ope n drain I/O. As export, each can drive eight TTL logic level. For P0 port to write "1", foot as the high impeda nee in put. When access to exter nal programs and nu merical memory, also known as
1．闪烁灯 1．实验任务 如图4.1.1所示：在P1.0端口上接一个发光二极管L1，使L1在不停地一亮一灭，一亮一灭的时间间隔为0.2秒。 2．电路原理图 图4.1.1 3．系统板上硬件连线 把“单片机系统”区域中的P1.0端口用导线连接到“八路发光二极管指示模块”区域中的L1端口上。 4．程序设计内容 （1）．延时程序的设计方法 作为单片机的指令的执行的时间是很短，数量大微秒级，因此，我们要 求的闪烁时间间隔为0.2秒，相对于微秒来说，相差太大，所以我们在 执行某一指令时，插入延时程序，来达到我们的要求，但这样的延时程 序是如何设计呢？下面具体介绍其原理：
如图4.1.1所示的石英晶体为12MHz，因此，1个机器周期为1微秒机器周期微秒 MOV R6,#20 2个 2 D1: MOV R7,#248 2个 2 2＋2×248＝498 20× DJNZ R7,$ 2个2×248 (498 DJNZ R6,D1 2个2×20＝40 10002 因此，上面的延时程序时间为10.002ms。 由以上可知，当R6＝10、R7＝248时，延时5ms，R6＝20、R7＝248时， 延时10ms,以此为基本的计时单位。如本实验要求0.2秒＝200ms， 10ms×R5＝200ms，则R5＝20，延时子程序如下： DELAY: MOV R5,#20 D1: MOV R6,#20 D2: MOV R7,#248 DJNZ R7,$ DJNZ R6,D2 DJNZ R5,D1 RET （2）．输出控制 如图1所示，当P1.0端口输出高电平，即P1.0＝1时，根据发光二极管 的单向导电性可知，这时发光二极管L1熄灭；当P1.0端口输出低电平， 即P1.0＝0时，发光二极管L1亮；我们可以使用SETB P1.0指令使P1.0 端口输出高电平，使用CLR P1.0指令使P1.0端口输出低电平。 5．程序框图 如图4.1.2所示
51单片机中的汇编语言与 C 语言 C 语言, 更多的是为了掌握单片机的应用, C 语言是高效的应用程序开发工具, 与汇编语言比却不是开发高效应用程序的工具。就目前而言, 更多的是为了应用单片机, 开发应用程序, 更多的是强调开发效率, 而不是程序的运行效率 (相对而言。再就是应用程序对单片机内部资源的使用效率, 这在过去, 单片机内部资源紧缺的年代, 特别的强调, 现在已经不是特别重要了。所以, 大多数人都认为,只用 C 语言,就可以应对大多数单片机的应用开发了。 其实,汇编语言跟 C 语言在本质上一样的,只是语言形式不同而已,一个接近底层逻辑, 一个接近人类语言, 本质上都是对寄存器或存储器的读写操作而已。 汇编语言中,用 MOV 来回传送数据, C 语言里,用等号表示数据传送。汇编语言中,用 call 转去执行子过程程序, C 语言里,用个函数名调用子程序。汇编语言中,用 JMP 完成分支转移, C 语言里用 if 、 switch 、 while 、 for 来判断跳转。汇编语言跟 C 一样可以给寄存器指定命名,然后对定义的名称进行操作。汇编语言提供了对很多标志位的操作, C51根据需要也进行了改进, C 语言可以通过 #include给存储器命名来简化操作。 我觉得, C 语言是最接近汇编语言的一种高级语言, 要说不同, 也许具有大量函数的函数库,是 C 语言与汇编语言的最大区别,也是 C 语言比汇编语言有更大开发效率的原因。 在应用汇编语言进行应用程序开发时, 如果精心规划好程序结构, 设计好各种数据结构、子程序、中断程序,积累大量的算法程序(相当于函数库,也可以高效率的用汇编语言进行单片机开发。倒是兼容性、可移植性是汇编语言的最大限制,因为不同单片机有不同的指令系统,而 C 语言把这个问题,交给了机器也就是编译器去解决了。其实, 计算机的发展, 就是把尽可能多的事情交个机器去解决。
SCM is an integrated circuit chip, is the use of large scale integrated circuit technology to a data processing capability of CPU CPU random access memory RAM, read-only memory ROM, a variety of I / O port and interrupt system, timers / timer functions (which may also include display driver circuitry, pulse width modulation circuit, analog multiplexer, A / D converter circuit) integrated into a silicon constitute a small and complete computer systems. SCM is also known as micro-controller (Microcontroller), because it is the first to be used in industrial control. Only a single chip by the CPU chip developed from a dedicated processor. The first design is by a large number of peripherals and CPU on a chip in the computer system, smaller, more easily integrated into a complex and demanding on the volume control device which. The Z80 INTEL is the first designed in accordance with this idea processor, then on the development of microcontroller and dedicated processors will be parting ways. Are 8-bit microcontroller early or 4 bits. One of the most successful is the INTEL 8031, for a simple, reliable and good performance was a lot of praise. Then developed in 8031 out of MCS51 MCU Systems. SCM systems based on this system until now is still widely used. With the increased requirements of industrial control field, began a 16-bit microcontroller, but not ideal because the cost has not been very widely used. After 90 years with the great development of consumer electronics, microcontroller technology has been a huge increase. With INTEL i960 series, especially the later series of widely used ARM, 32-bit microcontroller quickly replace high-end 16-bit MCU status and enter the mainstream market. The traditional 8-bit microcontroller performance have been the rapid increase capacity increase compared to 80 the number of times. Currently, high-end 32-bit microcontroller clocked over 300MHz, the performance catching the mid-90s dedicated processor, while the average model prices fall to one U.S. dollar, the most high-end [1] model only 10 dollars. Modern SCM systems are no longer only in the development and use of bare metal environment, a large number of proprietary embedded operating system is widely used in the full range of SCM. The handheld computers and cell phones as the core processing of high-end microcontroller can even use a dedicated Windows and Linux operating systems. SCM is more suitable than the specific processor used in embedded systems, so it was up to the application. In fact the number of SCM is the world's largest computer. Modern human life used in almost every piece of electronic and mechanical products will be integrated single chip. Phone, telephone, calculator, home appliances, electronic toys, handheld computers and computer accessories such as a mouse with a 1-2 in both the Department of SCM. Personal computer will have a large number of SCM in the work. General car with more than 40 microcontroller, a complex industrial control systems may even hundreds of single chip at the same time work! SCM is not only far exceeds the number of PC and other computing the sum, or even more than the number of human beings. Single chip, also known as single-chip microcontroller, it is not complete a certain logic chips, but to a computer system integrated into a chip. Equivalent to a
外文翻译---51系列单片机的结构和功能
外文资料翻译 英文原文： Structure and function of the MCS-51 series Structure and function of the MCS-51 series one-chip computer MCS-51 is a name of a piece of one-chip computer series which Intel Company produces. This company introduced 8 top-grade one-chip computers of MCS-51 series in 1980 after introducing 8 one-chip computers of MCS-48 series in 1976. It belong to a lot of kinds this line of one-chip computer the chips have such as 8051, 8031, 8751, 80C51BH, 80C31BH,etc., their basic composition, basic performance and instruction system are all the same. 8051 daily representatives- 51 serial one-chip computers . An one-chip computer system is made up of several following parts: (1) One microprocessor of 8 (CPU). (2) At slice data memory RAM (128B/256B),it use not depositing not can reading /data that write, such as result not middle of operation, final result and data wanted to show, etc. (3) Procedure memory ROM/EPROM (4KB/8KB ), is used to preserve the procedure , some initial data and form in slice. But does not take ROM/EPROM within some one-chip computers, such as 8031 , 8032, 80C ,etc.. (4) Four 8 run side by side I/O interface P0 four P3, each mouth can use as introduction, may use as exporting too. (5) Two timer / counter, each timer / counter may set up and count in the way, used to count to the external incident, can set up into a timing way too, and can according to count or result of timing realize the control of the computer. (6) Five cut off cutting off the control (universal asynchronous receiver/transmitter (UART) ), is it realize one-chip computer or one-chip computer and serial communication of computer to use for. (8) Stretch oscillator and clock produce circuit, quartz crystal finely tune electric capacity need outer. Allow oscillation frequency as 12 megahertz now at most. Every the above-mentioned part was joined through the inside data bus .Among them, CPU is a core of the one-chip computer, it is the control of the computer and command center, made up of such parts as arithmetic unit and controller , etc.. The arithmetic unit can carry on 8 persons of arithmetic operation and unit ALU of logic operation while including one, the 1 storing devices temporarily of 8, storing device 2 temporarily, 8's accumulation device ACC, register B and procedure state register PSW, etc. Person who accumulate ACC count by 2 input ends entered of checking etc. temporarily as one operation often, come from person who store 1 operation is it is it make operation to go on to count temporarily , operation result and loop back ACC with another one. In addition, ACC is often regarded as the transfer station of data transmission on 8051 inside. The same as general microprocessor, it is the busiest register. Help remembering that agreeing with a expresses in the order. The controller includes the procedure counter, the order is deposited, the