74LVQ138
3TO 8LINE DECODER (INVERTING)
?
February 1999s HIGH SPEED:t PD =5.5ns (TYP.)at V CC =3.3V s COMPATIBLEWITH TTL OUTPUT s
LOW POWER DISSIPATION:I CC =4μA (MAX.)at T A =25o C s
LOW NOISE:
V OLP =0.2V (TYP.)at V CC =3.3V s
75?TRANSMISSION LINE DRIVING CAPABILITY
s
SYMMETRICAL OUTPUT IMPEDANCE:|I OH |=I OL =12mA (MIN)
s PCI BUS LEVELSGUARANTEED AT 24mA s
BALANCED PROPAGATION DELAYS:t PLH ?t PHL
s
OPERATING VOLTAGERANGE:
V CC (OPR)=2V to 3.6V (1.2V Data Retention)s
PIN AND FUNCTION COMPATIBLE WITH 74SERIES 138
s
IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The LVQ138is a low voltage CMOS 3TO 8LINE DECODER (INVERTING)fabricated with sub-micron silicon gate and double-layer metal wiring C 2MOS technology.
It is ideal for low power and low noise 3.3V applications.
If the device is enabled,3binary select inputs (A,
B and C)determine which one of the outputs will go low.If enable input G1is held low or either G2A or G2B is held high,the decoding function is inhibited and all the 8outputs go high.
Three enable inputs are provided to ease cascade connection and application of address decoders for memory systems.
It has better speed performance at 3.3V than 5V LSTTL family combinad with the true CMOS low power consumption.
All inputs and outputs are equipped with protection circuits against static discharge,giving them 2KV ESD immunity and transient excess voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
M1
(Micro Package)T
(TSSOP Package)
ORDER CODES :
74LVQ138M 74LVQ138T
1/9
INPUT AND OUTPUT EQUIVALENT CIRCUIT LOGIC DIAGRAM PIN DESCRIPTION
PIN No SYMBOL NAME AND FUNCTION 1,2,3A,B,C Address Inputs
4,5G2A,G2B Enable Inputs
6G1Enable Input
15,14,13,
12,11,10,
9,7
Y0to Y7Outputs
8GND Ground(0V)
16V CC Positive Supply Voltage
TRUTH TABLE
INPUTS OUTPUTS
ENABLE SELECT
G2B G2A G1C B A Y0Y1Y2Y3Y4Y5Y6Y7 X X L X X X H H H H H H H H X H X X X X H H H H H H H H
H X X X X X H H H H H H H H
L L H L L L L H H H H H H H L L H L L H H L H H H H H H L L H L H L H H L H H H H H L L H L H H H H H L H H H H L L H H L L H H H H L H H H L L H H L H H H H H H L H H L L H H H L H H H H H H L H L L H H H H H H H H H H H L X:Don’t Care
Thislogic diagram has notbe used to esimate propagation delays
74LVQ138
2/9
74LVQ138
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Value Unit V CC Supply Voltage-0.5to+7V V I DC Input Voltage-0.5to V CC+0.5V V O DC Output Voltage-0.5to V CC+0.5V
I IK DC Input Diode Current±20mA
I OK DC Output Diode Current±20mA
I O DC Output Current±50mA
I CC or I GND DC V CC or Ground Current±200mA
T stg Storage Temperature-65to+150o C T L Lead Temperature(10sec)300o C Absolute Maximum Ratingsarethose values beyond which dam age to the device may occur.Functional operation un der these condition is not implied. (*)500mW:?65o C derated to300mW by10mW/o C:65o C to85o C
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Value Unit V CC Supply Voltage(note1)2to3.6V V I Input Voltage0to V CC V V O Output Voltage0to V CC V T op Operating Temperature:-40to+85o C dt/dv Input Rise and Fall Time(V CC=3V)(note2)0to10ns/V
1)Truth Table guaranteed:1.2V to3.6V
2)V IN from0.8V to2V
3/9
DC SPECIFICATIONS
Symbol Parameter Test Conditions Value Unit
V CC (V)
T A=25o C-40to85o C Min.Typ.Max.Min.Max.
V IH High Level Input Voltage 3.0to
3.62.0 2.0V
V IL Low Level Input Voltage0.80.8V
V OH High Level Output
Voltage 3.0V I(*)=
V IH or
V IL
I O=-50μA 2.9 2.99 2.9
V
I O=-12mA 2.58 2.48
I O=-24mA 2.2
V OL Low Level Output
Voltage 3.0V I(*)=
V IH or
V IL
I O=50μA0.0020.10.1
V
I O=12mA00.360.44
I O=24mA0.55
I I Input Leakage Current 3.6V I=V CC or GND±0.1±1μA I CC Quiescent Supply
Current
3.6V I=V CC or GND440μA
I OLD Dynamic Output Current
(note1,2)3.6V OLD=0.8V max36mA
I OHD V OHD=2V min-25mA
1)Maximum test duration2ms,one output loaded attime
2)Inciden t wave switch ing is guaranteed on transmission lines with impeda nces aslow as50?.
(*)Alloutputs loaded.
DYNAMIC SWITCHING CHARACTERISTICS
Symbol Parameter Test Conditions Value Unit
V CC (V)
T A=25o C-40to85o C Min.Typ.Max.Min.Max.
V OLP Dynamic Low Voltage
Quiet Output(note1,2)
3.3
C L=50pF 0.20.8
V
V OLV-0.8-0.2
V IHD Dynamic High Voltage
Input(note1,3)
3.32
V ILD Dynamic Low Voltage
Input(note1,3)
3.30.8
1)Worst case package
2)Max num ber of outputs defined as(n).Data inputs aredriven0V to3.3V,(n-1)outputs switching and one out put at GND
3)max num ber of data inputs(n)switching.(n-1)switching0V to3.3V.Inputs under test switching:3.3V to threshold(V ILD),0V to threshold(V IHD).f=1MHz 74LVQ138
4/9
C L =50pF or equivalent (includes jigand probe capacitance)R L =R 1=500?orequivalent
R T =Z OU T of pulse generator (typ ically 50?)
CAPACITIVE CHARACTERISTICS
Symbol
Parameter
Test Conditions
Value
Unit
V CC (V)
T A =25o
C -40to 85o
C Min.
Typ.Max.
Min.
Max.
C IN Input Capacitance 3.35pF C PD
Power Dissipation Capacitance (note 1)
3.3
f IN =10MHz
50
pF
1)C PD isdefined as the value of the IC’sinternal equiva lent capacitance which is calculated fromthe operating current consumption without load.(Referto Test Circuit).Average operting curren t can be obtained bythe followingequa tion.I CC (opr)=C PD ?V CC ?f IN +I CC
AC ELECTRICAL CHARACTERISTICS (C L =50pF,R L =500?,Input t r =t f =3ns)
Symbol
Parameter
Test Condition
Value
Unit
V CC (V)
T A =25o
C -40to 85o C Min.Typ.Max.Min.Max.
t PLH t PHL Propagation Delay Time A,B,C to Y
2.77.017.020.0
ns 3.3(*) 5.512.014.0t PLH t PHL Propagation Delay Time G1to Y
2.77.017.020.0ns
3.3(*) 5.512.01
4.0t PLH t PHL Propagation Delay Time G2A or G2B to Y 2.77.017.020.0ns 3.3(*)
5.512.014.0t OSLH t OSHL
Output to Output Skew Time (note 1,2)
2.70.5 1.5 1.5ns
3.3
(*)
0.5
1.5
1.5
1)Skew is defined as the absolute value of the difference between theactual propagation delay for any twooutputs of the sam e device switching in the same direction,either HIGHor LOW (t OSLH =|t PLH m -t PLHn |,t OSH L =|t PHLm -t pHLn |)2)Parameter gu aranteed bydesign (*)Voltag e range is 3.3V ±0.3V
TEST CIRCUIT
74LVQ138
5/9
74LVQ138
WAVEFORM1:PROPAGATION DELAYS FOR INVERTING OUTPUTS(f=1MHz;duty cycle50%) WAVEFORM2:PROPAGATION DELAYS FOR NON-INVERTING OUTPUTS(f=1MHz;
duty cycle50%)
6/9
DIM.
mm inch MIN.
TYP.
MAX.MIN.
TYP.
MAX.A 1.750.068a10.1
0.20.0040.007a2 1.650.064b 0.350.460.0130.018b10.19
0.25
0.007
0.010
C 0.5
0.019
c145(typ.)
D 9.8100.3850.393
E 5.8
6.2
0.228
0.244
e 1.270.050e38.89
0.350
F 3.8 4.00.1490.157
G 4.6 5.30.1810.208L 0.5 1.270.019
0.050M 0.62
0.024S
8(max.)
P013H
SO-16MECHANICAL DATA
74LVQ138
7/9
DIM.
mm
inch MIN.
TYP.
MAX.MIN.
TYP.
MAX.A 1.10.433A10.050.100.150.0020.0040.006A20.850.90.950.3350.354
0.374b 0.190.300.00750.0118c 0.090.200.00350.0079D 4.95 5.10.1930.1970.201E 6.25 6.4 6.50.2460.2520.256E1 4.3
4.4 4.48
0.169
0.1730.176
e 0.65BSC
0.0256BSC
K 0o 4o 8o 0o 4o 8o L
0.500.60
0.70
0.020
0.024
0.028
c
E
b
A2
A
E1
D
1
PIN 1IDENTIFICATION
A1
L
K
e
TSSOP16MECHANICAL DATA
74LVQ138
8/9
74LVQ138 Information furnished is believed to be accurate and reliable.However,STMicroelectronics assumes no responsibility for the consequence s
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use.No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics.Specification mentioned in this publication are subject to change without notice.This publication supersedes and replaces all information previously supplied.STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a trademark of STMicroelectronics
?1999STMicroelectronics–Printed in Italy–All Rights Reserved
STMicroelectronics GROUP OF COMPANIES
Australia-Brazil-Canada-China-France-Germany-Italy-Japan-Korea-Malaysia-Malta-Mexico-Morocco-The Netherlands-Singapore-Spain-Sweden-Switzerland-Taiwan-Thailand-United Kingdom-U.S.A.
https://www.doczj.com/doc/a114400494.html,
.
9/9