实验
目标：
（1）学习和掌握较复杂数字逻辑电路的设计方法
内容：
（1）试用Verilog HDL语言，设计一个秒计数器，将计数过程用两个数码管进行显示（00～59）。要求首先使用Modelsim软件进行功能仿真，然后使用Quartus软件综合，并下载到开发板进行电路功能测试。
module counters(out,sel,clock_128,clear);
input clock_128,clear;
output[6:0] out;
output sel;
reg [6:0] out;
reg sel;
reg [3:0] countl,counth,count;
reg [15:0] fenping;
wire clock_1=fenping[6];
always @(posedge clock_128 or negedge clear)
begin
if (!clear)
fenping <= 16'b0;
else
fenping <= fenping + 1;
end
//countl
always @(posedge clock_1 or negedge clear)
begin
if (!clear)
countl <= 4'b0;
else if (countl == 9)
countl <= 4'b0;
else
countl <= countl + 1;
end
//counth
always @(posedge clock_1 or negedge clear) begin
if (!clear)
counth <= 4'b0;
else if (counth == 5 && countl == 9)
counth <= 4'b0;
else if (countl == 9)
counth <= counth + 1;
else
counth <= counth;
end
always @(posedge clock_128 or negedge clear) begin
if (!clear)
sel <= 0;
else
sel <= ~sel;
end
always @(sel)
count = (sel == 0)?counth:countl;
always @(count)
begin
case(count)
4'b0000: out=7'b011_1111;
4'b0001: out=7'b000_0110;
4'b0010: out=7'b101_1011;
4'b0011: out=7'b100_1111;
4'b0100: out=7'b110_0110;
4'b0101: out=7'b110_1101;
4'b0110: out=7'b111_1101;
4'b0111: out=7'b000_0111;
4'b1000: out=7'b111_1111;
4'b1001: out=7'b110_1111;
default: out=7'b000_0000;
endcase
end
endmodule
`timescale 1ns/1ns
`include"./counters.v"
module test;
reg Clock,Clear;
wire [6:0] Out;
wire Sel;
initial
begin
Clock=0;
Clear=1;
#10 Clear=0;
#100 Clear=1;
end
always #10 Clock=~Clock;
counters m(.out(Out),.sel(Sel),.clock_128(Clock),.clear(Clear)); endmodule