Power-Aware Test Planning in the Early System-on-Chip Design Exploration Process Erik Larsson,Member,IEEE,and Zebo Peng,Senior Member,IEEE
Abstract—Test application and test design,performed to ensure the production of fault-free chips,are becoming complicated and very expensive,especially in the case of SoCs(System-on-Chip),as the number of possible faults in a chip is increasing dramatically due to the technology development.It is therefore important to take test design into consideration as early as possible in the SoC design-flow in order to develop an efficient test solution.We propose a technique for modular core-based SoCs where test design is integrated in the early design exploration process.The technique can,in contrast to previous approaches,already be used in the core selection process to evaluate the impact on the system’s final test solution imposed by different design decisions.The proposed technique considers the interdependent problems of core selection,test scheduling,TAM(test access mechanism)design,test set selection,and test resource floorplanning,and minimizes a weighted cost-function based on test time and TAM routing cost,while considering test conflicts and test power limitations.Concurrent scheduling of tests is used to minimize the test application time;however,concurrent test application leads to higher activity during the testing and,hence,higher power consumption.The power consumed during testing is,in general,higher than that during normal operation since it is desirable with hyperactivity in order to maximize the number of tested faults in a minimal time.A system under test can actually be damaged during testing and,therefore,power constraints must be considered.However,power consumption is complicated to model and,often,simplistic models that focus on the global system power limit only have been proposed and used.We therefore include a novel three-level power model:system,power-grid,and core.The advantage is that the system-level power budget is met and hot-spots can be avoided both at a specific core and at certain hot-spot areas in the chip.We have implemented and compared the proposed technique with a technique that assumes already fixed cores and tests,an estimation-based approach,and a computationally expensive pseudoexhaustive method.The results from the experiments show that,by exploring different design and test alternatives,the total test cost can be reduced,the pseudoexhaustive technique cannot produce results within reasonable computational time,and the estimation-based technique cannot produce solutions with high quality.The proposed technique produces results that are near the ones produced by the pseudoexhaustive technique at
computational costs that are near the costs of the estimation-based technique,i.e.,it produces high-quality solutions at low
computational cost.
Index Terms—Test scheduling,test set selection,design exploration,TAM design,power consumption,hot-spots.
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1I NTRODUCTION
T ECHNOLOGY development has made it possible to design
a chip where the complete system is placed on a single die,a so-called system chip or SoC(System-on-Chip).The production of these systems may lead to faulty chips and it is therefore important that the produced chips are tested. The growing complexity of chips,device size miniaturiza-tion,increasing transistor count,and high clock frequencies have led to a dramatic increase in the number of possible fault sites and fault types and,therefore,a high test data volume is needed for high-quality testing.However,the high test data volume leads to long testing times and, therefore,the planning and organization of the testing becomes a challenge that has to be tackled.
EDA(Electronic Design Automation)tools are devel-oped to reduce the design productivity gap,i.e.,the gap between what technology allows to be designed and what a design team can produce within a reasonable time.A way to handle the increasing complexity of systems is to model the systems at higher abstraction levels.However,modeling at higher abstraction levels means that fewer implementa-tion specific details are visible.The problem is that device size miniaturization has made implementation specific details highly important.A modular core-based design approach has therefore been proposed to allow the design of complex systems in reasonable time and,at the same time,handle implementation specific details[15],[17].The basic idea is that predesigned and preverified blocks of logic,as well as newly designed blocks of logic,called cores, are integrated by the core integrator to an SoC.The cores, provided by core vendors,may each have a different origin, such as from various companies,reuse from previous designs,or the cores can be completely new in-house designs.The test designer is responsible for the design of the system’s test solution,which includes decisions on the organization and the application of test data(test stimuli and test responses)for each core in the system.Test application time minimization is often one of the main objectives since it is highly related to the cost of test,but it is also important to minimize the added overhead,such as additional wiring,while constraints and conflicts should be considered.
A core-based SoC design methodology consists usually of two major steps:a core selection step,where the core
.The authors are with the Embedded Systems Laboratory,Department of
Computer and Information Science,Linko¨ping University,SE-58183
Linko¨ping,Sweden.E-mail:{erila,zpe}@ida.liu.se.
Manuscript received5Dec.2004;revised22Apr.2005;accepted14July
2005;published online21Dec.2005.
For information on obtaining reprints of this article,please send e-mail to:
tc@https://www.doczj.com/doc/ac2830132.html,,and reference IEEECS Log Number TCSI-0397-1204.
0018-9340/06/$20.00?2006IEEE Published by the IEEE Computer Society
integrator selects the appropriate cores for the system,and the core test design step,where the test solution for the system is created,which includes test scheduling and the design of the infrastructure for test data transportation,the TAM(Test Access Mechanism).These two steps are traditionally performed in sequence,one after the other (see Fig.1a).For such an SoC design-flow,it is important to note that the core integrator can,in the initial design step (core selection),select among several different cores,often from several core vendors,to implement a certain function-ality in the system.The core integrator selects,based on each core’s design characteristics given in its specification, the cores that fit the system best.Each possible core may not only have different design characteristics,but may also have different test characteristics(for instance,test sets and test power consumption).For example,one core may require a large ATE(Automatic Test Equipment)stored test set,while another core,implementing the same functionality,requires a combination of a limited ATE test set and a BIST(Built-In Self-Test)test set.The decision on which core to select therefore has an impact on the global test solution.Selecting the optimal core based only on its functionality will lead to local optimum,which is not necessarily the global optimum when the total cost of the system,including test cost,is considered.In other words, the selection(of cores and/or tests)must be considered with a system perspective in order to find a globally optimized solution.This means that there is a need for a test solution design tool that can be used in the early core selection process to explore and optimize the system’s test solution(see Fig.1b).Such a tool could help the test designer to answer the following question from a core integrator:“For this SoC-design,which of these cores are the most suitable cores for the system’s test solution?”
We have previously proposed a technique for integrated test scheduling and TAM design where a weighted cost-function based on test time and TAM wiring cost is minimized while considering test conflicts and test power consumption[11].We assumed that the tests for each testable unit were fixed and the main objective was,for a given system,to define a test solution.In this paper,on the other hand,we assume that,for each testable unit,several alternatives may exist.We propose a technique to integrate core selection,test set selection,test resource floorplanning,TAM design,and test scheduling in a single procedure.Core selection,test set selection,test resource floorplanning,TAM design,and test scheduling are highly interdepen-dent.The test time can be minimized by scheduling the tests as concurrently as possible;however,the possibility of concurrent testing depends on the size of the TAM connecting the test resources(test sources and test sinks). The placement of the test resources has a direct impact on the length of the TAM wires.And,finally,the selected test sets for each testable unit are partitioned over the test resources and have a large impact on the TAM design and the test schedule.Therefore,these problems must be considered in an integrated manner.
Test power consumption is becoming a severe problem. In order to reduce testing times,concurrent execution of tests is explored.However,this may lead to more power than the given power budget of the system being consumed and that can damage the system.The proposed technique includes an improved power model that considers1)global system-level limitations,2)local limitations on power-grid level(hot-spots),as well as3)core-level limitations.The motivation for the more elaborate power model is that the system is designed to operate in normal mode;however, during testing mode,the testable units are activated in a way that would not usually occur during normal operation. It can lead to1)the systems power budget being exceeded or2)hot-spots appearing and damaging a certain part in the system or3)a core being activated in such a way that the core is damaged.
The proposed technique can be used to explore alter-native cores for an SoC,different test alternatives for each testable unit,as well as the placement of test resources.As the design alternatives increase,we make use of Gantt charts to limit the search space.We have implemented the proposed technique,an estimation-based technique,and a pseudoexhaustive technique.In the experiments,we have compared with our previously proposed technique,where the cores are fixed and the tests are fixed.The experiments show that allowing design and test selection can reduce the final test cost and the experiments using the estimation-based technique show that it is difficult to produce high-quality solutions and the experiments with the pseudoex-haustive technique demonstrate that the search space is enormous.The proposed technique,on the other hand, produces solutions with a total cost that is near the cost produced by the pseudoexhaustive technique but at a computational cost that is near the estimation-based technique.
The rest of the paper is organized as follows:Background and an overview of prior work are given in Section2and the problem formulation is in Section3.The test problems and their modeling are in Section4and the algorithm and an illustrative example are in Section5.The experimental results are in Section6and the conclusions are in Section7. 2B ACKGROUND AND R ELATED W ORK
The technology development has,as discussed above, enforced the introduction of the core-based design environ-ment where reusable logic blocks(cores)are combined to form a system that is placed on a single die[17].A core-based design and production flow is typically a sequential process that starts with core selection,followed by test
Fig.1.Design flow in a core-based design environment:(a)traditional and(b)proposed.
solution design,and,after production,the system is tested (Fig.1a).In the core selection stage,the core integrator selects appropriate cores to implement the intended functionality of the system.For each function,there are often a number of possible cores to select from and each candidate core has its specification.The specification includes,for instance,data on performance,power con-sumption,area,and test characteristics.The core integrator explores the design space (search and combines cores)in order to optimize the performance of the SoC.Once the system is fixed (the cores are selected),the test designer designs the TAM and schedules the tests based on the test specification for each core.In such a design flow (illustrated in Fig.1a),the test solution design is a consecutive step to core selection.This means that,even if each core’s design is highly optimized,when integrated as a system,the system’s global test solution is not optimized.
A design flow such as the one in Fig.1b,on the other hand,integrates the core selection step and the test solution design step.The advantage is that it is possible to consider the impact of core selection when designing the test solution.In such a design flow (Fig.1b),the global system impact on core selection is considered and it is possible to develop a more optimized test solution.The impact of the design flow in Fig.1b can be illustrated as in Fig.2,where the core type is floorplanned in the system,but there is not yet a design decision on which core to select.For each core type (the floorplan position),several alternative cores can be used.For instance,for the cpu core,there are three alternative processor cores (cpu1,cpu2,and cpu3),as illustrated in Fig.2.And,for each core,several tests can be given.
In this paper,we make use of the test concepts introduced by Zorian et al.[15],which are illustrated with an example in Fig.3.The example consists of three main blocks of logic,core A (CPU core),core B (DSP core),and core C (UDL,user-defined logic,block).A test source is where test stimulus is created or stored and a test sink is where the test response is stored or analyzed.The test resources (test source and test sink)can be placed on-chip or off-chip.In Fig.3,the ATE serves as an off-chip test source and off-chip test sink,while TG1,for instance,is an on-chip test source.The TAM is the infrastructure 1)for test stimulus transportation from a test source to the testable unit and 2)for test response transportation from a testable unit to a test sink.A wrapper is the interface between a core and the TAM and a core with a wrapper is said to be wrapped while a core without a wrapper is said to be unwrapped .Core A is a wrapped core,while Core C is
unwrapped.The wrapper cells at each wrapper can be in one of the following modes at a time:internal mode,external mode,and normal operation mode .In addition to the definitions by Zorian et al.[15],we assume that a testable unit is not a core,but a block at a core,and that a core can consist of a set of blocks.For example,core A (Fig.3)consists of two blocks (A.1and A.2).
For a fixed system where cores are selected and floor-planned and,for each testable unit,the tests are fixed,the main tasks are to organize the testing and the transportation of test stimuli and test responses (as the example design in Fig.3).Several techniques have been proposed to solve different important problems under the assumption that the cores are already selected (design flow as in Fig.1a).
Zorian [14]proposed a test scheduling technique for a fully BISTed system where each testable unit is tested by one test with a fixed test time and each testable unit has its dedicated on-chip test source and its dedicated on-chip test sink.A fixed test power value is attached to each test and the aim is to organize the tests into sessions in such a way that the summation of the power consumed in a session is not above the system’s power budget,while the test application time is minimized.In a system where the testable units share test sources and test sinks,the test conflicts must be taken into account.Chou et al.proposed a test scheduling technique that uses a conflict graph to handle general conflicts and minimizes the test time for systems where both the test time and power consumption for each test are fixed [1].
The approaches by Zorian and Chou et al.assume fixed testing times for each testable unit.The test time for a core can be fixed by the core provider,which may be due to the core providers having optimized their cores in order to protect the IP-blocks,for instance.However,the test time at a core is not always fixed.For scan-tested cores,the scanned elements can be connected to any number of wrapper chains.If the scanned elements (scan-chains,inputs,and outputs)at a core are connected to a small number of wrapper chains,the testing time is longer compared to when the scan elements are connected into a larger number
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Fig.2.System design with different alternatives.
Fig.3.A system and the illustration of some test concepts.
of wrapper chains.Iyengar et al.proposed a scheduling technique for systems where the testing time for all cores is flexible and the objective is to form a set of wrapper chains for each core in such a way that the testing time for the system is minimized[7].
In order to minimize the test times,as many fault locations as possible are activated concurrently,which leads to high power consumption.Zorian[14]and Chou et al.[1] assign a fixed power value to each test and make sure that the scheduling does not activate the tests in such a way that the system’s power budget is exceeded at any time. Bonhomme et al.[2]and Saxena et al.[12]proposed a clock-gating scheme intended to reduce the test power consumed during the scan-shift process.The advantage is that the test power can be reduced at a core with such a scheme and,hence,a higher number of cores can be scheduled for test concurrently.The basic idea is if n scan-chains at a core are to be connected to m wrapper-chains (n>m),only m scan-chains can be loaded at a time,which means that not all n chains are active at the same time, hence,lower power consumption.
There has been research to find the most suitable ATE/ BIST partition for each testable unit.Sugihara et al. investigated the partitioning of test sets where one part is on-chip test(BIST)and the other part is off-chip test using an ATE[13].A similar approach was proposed by Jervan et al.[8],which later was extended to not only locally optimize the test set for a core but to consider the complete system by using an estimation technique to reduce the test analysis complexity[9].
Hetherington et al.discussed several important test limitations such as ATE bandwidth and memory limitations [5].These problems,as well as the problems described above,are important to consider in the search of a final test solution for the system.
The problems addressed above are all individually important to consider when designing the test solution for a SoC.However,it is important to consider them all simultaneously and from a system test perspective.We have previously proposed an integrated technique for test scheduling and TAM design where the test application time and the TAM design are minimized while considering test conflicts and power consumption[11].The technique handles unwrapped as well as wrapped cores and also systems where some cores have a fixed testing time and some cores have a flexible testing time.The technique is also general in the test source and test sink usage.Each test can be defined to use any test source and any test sink.It is not necessary for a test to use a test source and a test sink where both are placed on-chip or both are placed off-chip. Furthermore,the technique allows an arbitrary number of tests per testable unit,which is an important feature in order to handle testing for timing faults and delay faults and not only stuck-at faults.However,that technique assumes that the tests for each testable unit are fixed and defined.
3P ROBLEM F ORMULATION
Fig.4illustrates the problem we address.We assume that a floorplan is given of an SoC where the core types are defined but the particular core is not yet selected.For example,at position c x,c1and c2are the alternatives.Each of the alternative cores may consist of a set of blocks (testable unit)where each block has multiple test alter-natives.For instance,b1at c1can be tested by test t1or by tests t2and t3.Each test is attached to one block and each test has its combination of test source and test sink.For instance,t1makes use of r1and s1.Since no other test in the system makes use of r1and s1,r1and s1will most likely not limit the test time.On the other hand,since s1and r1are not used by any other test,the added TAM has a low utilization,which leads to the waste of resources.
An example of an input specification of the example system in Fig.3,the starting point in our approach,is given in
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Fig.5.The structure of the input specification is based on the specification we made use of in [11].The major extensions are 1)for each block (testable unit),several alternative lists of tests can be specified,instead of as before where it was only possible to assign one dedicated list of tests per block,and 2)the improved power-grid model makes it possible to more accurately model power dissipation.
The advantage of the possibility of specifying several lists of tests for each block (testable unit),where each test in a list makes use of its specified resources (test source and test sink)and each test has its test characteristics,is that it makes it possible to explore different design alternatives.The test problems that are considered in our technique and their modeling are discussed in Section 4.The input specification is explained in the following text,where the notations are defined and illustrated with the example given in Fig.5.
The cores are floorplanned,i.e.,given (x,y)coordinates and each core consisting of a set of blocks (testable units):[Cores]#name
x y block_list
coreA
2010{blockA1,blockA2}
For each block,several sets of tests are available,where each set of tests is sufficient for the testing of the block.For instance,to test block blockA1,three possible test sets are given:
[Blocks]#name
test_sets {}{}blockA1{tA1.2tA1.3}
{tA1.1}or {tA1.2tA1.3}should be selected where each test has its resources and characteristics.
The proposed technique will select cores and corre-sponding blocks and,for each block,the set of tests to use in order to produce an optimized test solution for the system.The cost of a test solution is given by the test application time and the amount of routed TAM wires:
cost ? ? total t ?T AM;
e1T
where total is the total test application time (the end time of the test with the latest test time),T AM is the routing length of all TAM wires,and and are two user-defined constants used to determine the importance of test time in relation to TAM cost.The selection of the user-defined constants and is based on the characteristics of the particular SoC;hence,it is therefore not possible to define universal values on and .
The produced output from our technique is a test schedule where the cores are selected and,for each block (testable unit)at the selected cores,the tests are selected and given a start time and an end time in such a way that all conflicts and constraints are not violated,and a correspond-ing TAM layout,where the cost (1)is minimized.
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Fig.5.Input specification for the example system in Fig.3.
4T EST P ROBLEMS AND T HEIR M ODELING
In this section,we discuss the test problems that have to be considered in our approach and the modeling of the problems.
4.1Test Time
The testing time for a testable unit can be fixed or flexible prior to the design of the test solution.A core provider might protect the core and,therefore,optimize the core and its core wrapper prior to delivery,hence,having the testing time fixed.On the other hand,the testing time for a core can be flexible,such as for a scan-tested core where the scanned elements(scan-chains and wrapper cells)can be connected into one or several wrapper-chains.The testing time for a test with flexible test time depends on the number of wrapper-chains.It is important to note that tests with fixed and flexible testing times can be mixed in the system.The test time model must therefore handle systems where some cores have fixed test time while other cores have flexible testing time.
A higher number of wrapper-chains at a core results in lower testing time compared to if fewer wrapper-chains are used.The scan-chains at a core can be few and unbalanced (of unequal length),and the testing time might not be linearly dependent on the number of wrapper chains. Therefore,we analyzed the linearity of the testing time( ) versus the number of wrapper-chains(w),that is,if ?w?constant.We selected the scan-tested cores in one of the largest ITC’02designs,namely,the P93791design [11].We observed that the testing time for core11was the most nonlinear(as shown by the curve labeled as Core11-original in Fig.6).We noted that the576scanned elements were partitioned into11scan-chains(with the length8282 828181811818171717).We redesigned core11into four new cores with11,22,44,and88balanced scan-chains, respectively.We plotted the ?w curves for all these cores in Fig.6.As the number of scan-chains increases,the value ?w becomes more or less constant at any TAM width. The testing time at a single wrapper chain times TAM width one is149,381(marked in Fig.6).For core11with 44balanced scan-chains,the value ?w at any TAM width is always less than5percent from the constant theoretical value.It is important to note that,for all cores,the value ?w is almost constant within a certain range.We assume that the core test designer optimizes the cores,hence,the number of scan-chains at a core is relatively high and of nearly equal length.
In our model,we specify the testing time for a testable unit at a single TAM wire and the bandwidth limitations. For instance,a test tA1.1has a test time of60time units at a single wrapper chain and where the scanned elements can be arranged into wrapper-chains in the range1to4(only test time and bandwidth are mentioned):
[Tests]#name test time minbw maxbw
tA1.16014
We assume,based on our experiments,that the test time is linear to the number of TAM wires within the bandwidth range.It means that,given the test time at a single TAM wire( 1),the test time t i can be computed by:
i?
1
i
;e2Twhere i is in the range?minbw;maxbw .If the testing time is fixed,minbw?maxbw.
4.2Test Power Consumption
The test application time is reduced if a high number of cores are activated and tested concurrently;however,it leads to higher switching activity and higher power dissipation.The system-level power budget can be ex-ceeded and high power consumption can damage the system.Furthermore,if cores that are floorplanned close to each other are activated concurrently,a hot-spot can be created and it also can damage the system.For instance, assume a memory organized as four banks where,in normal operation,only one bank is activated at a time. However,during testing,in order to shorten the test time, all banks are activated concurrently.The system’s total power limit might not be exceeded,however,a local hot-spot is created in the memory subsystem and the system may be damaged.
The switching activity and power consumption are higher during testing than during normal operation.It means that a core during testing can dissipate power above its specified limit due to the nature of the test stimuli and/ or the test clock frequency.
We therefore make use of a three-level power model: system-level,power-grid-level(local hot-spot),and core-level.For the system-level,we make use of the power model defined by Chou et al.where the summation of power values of the concurrently executed tests is below the power budget of the system[1].
As an example,we can specify the system budget as:
MaxPower?100
and,for each test,we specify the power consumed when the test is activated:
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Fig.6.Test time analysis for core11in design P93791,where the cost w? is plotted for the cores at TAM widths(w)1to16.
[Tests]#name
pwr time tpg tre min_bw max_bw tA1.16060TG1TE114mem ict flexible_pwr 10no no
Additionally,the idle power,the power consumed when a block is in stand-by mode and not active,is also specified for each block:
[Blocks]#name idle pwr test sets {}{}
blockA10{tA1.1}{tA1.2tA1.3}
For local hot-spots,we introduce a power grid model,
which has similarities to the approach proposed by Chou et al.[1],but,instead of having a single maximal power constraint for the whole system,we have local power constraints for subparts of the system.We assume that each block (testable unit)is assigned to a power grid,where the power grid has its power budget.The system can contain an arbitrary number of power grids.Blocks assigned to a power grid cannot be tested in such a way that the power grid budget is exceeded at any time;the scheduling algorithm prevents such a situation from occurring by selecting alternative tests or scheduling tests later.
An example to illustrate the need for power grids is as follows:A memory can be organized as a bank of memory blocks (see Fig.7).Assume that the memory,during normal operation,never accesses more than a single memory block at a time and the power grid is designed accordingly.A single grid is specified as:[PowerGrid]#name power_limit
p_grid150
For each block the power grid usage is given as:
[Blocks]#name idle pwr pwr_grid test sets {}{}
blockkA10p_grid1{tA1.1}{tA1.2tA1.3}As discussed above,some tests have a fixed testing time
while other tests allow flexible testing times.Regarding test power consumption,we have some tests where the power is fixed regardless of the number of assigned TAM wires,while other tests allow the power to be adjusted by clock-gating [12].Clock-gating can be used to reduce the power consumption so that a higher number of tests can be executed concurrently,but it also can be used for the units under test where its own power dissipation is higher than its allowed power consumption due to,for instance,a too high test clock frequency.
The motivation behind core-level adjustments is two-fold.First,by lowering the power consumption at a core,a higher number of cores can be activated concurrently without violating the total power budget.Second,since test
power consumption often is higher than that during normal operation,the power dissipation during test at a specific core can be higher than its own power budget.
The power consumption for a test is given as a single value,which corresponds to the power consumption when a single TAM wire is used,for instance,as in the following example (interconnection test flag,test source,and test sink usage are omitted):
[Tests]#name pwr time minbw maxbw
flexible_pwr
tA1.1606014yes tC1.1708014
no
Note that we include the possibility of specifying if clock-gating can be used by setting flexible_pwr to yes or no.If power can be modified,we assume a linear dependency [12]:
p i ?p 1?tam;
e3T
where p 1is the power at a single TAM wire,p i is the power consumed when i number of TAM wires are used;i has to be in the specified range ?minbw :maxbw .
4.3Test Conflicts
During the test solution design,there are a number of conflicts that have to be considered and modeled.Each test may have its defined constraints depending on the type of test;stuck-at,functional,delay,timing,etc.For general conflicts,we make use of the following notation [11]:[Constraints]#name {block1,block2,...,block n}
tA1.1{blockA1}
The notation means that,when applying test tA1.1,blockA1must be available and no testing can be performed on it since it is used by test tA1.1or tA1.1might interfere with blockA1.This modeling supports general conflicts,which can be due to hierarchy where cores are embedded in cores or interference during testing.The model can also be used for designs where an existing functional bus is used as the TAM.A functional bus can be modeled as a dummy block,where,usually,only one test can be active at a time.A test source ([Generators])may have limited bandwidth and memory.The bandwidth limitation and the memory limitation are especially critical for ATEs,but are also important if on-chip resources such as memories are used for test data storage.We denote bandwidth limitation as an integer stating the highest allowed bandwidth for the test source.For memory limitations,an integer is used as the maximal memory capacity.A test sink ([Evaluators])can also have a limited bandwidth and,in a similar way as with test sources,we denote it with an integer.For simplicity,we only assign memory constraint at the test source.For each test,we give an integer value as its memory requirement.An example with testA1.1using test source ATE and test sink ATE with memory requirement 10is given below (for the test,only name,source,sink,and memory limitation are given):[Generators]#name x y
maxbw
memory ATE 100
4
100
[Evaluators]#name x y
maxbw ATE 500
4[Tests]#name tpg tre
mem tA1.1ATE ATE
10
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Fig.7.A memory organized as a bank of four blocks powered by a common grid.
The wrapper conflicts are slightly different compared to general conflicts because of the TAM routing.The testing of a wrapped core is different from the testing of an unwrapped one.The testing of the wrapped core A (Fig.3),for example,is performed by placing the wrapper in internal test mode and test stimuli are transported from the required test source using a set of TAM wires to the core and the produced test responses are transported from the core using a set of TAM wires to the test sink.In the case of an unwrapped testable unit such as the UDL block,the wrappers at cores A and B are placed in external test mode .The test stimuli are transported from the required test source on the TAM via core A to the UDL block and the test responses are transported via core B to the TAM and to the test sink.It means that,for the TAM design,the TAM should be routed to core A and B (and not to the UDL block).
We model the wrapper conflict as in the following example,with two blocks (bA and bB)and one test per block (tA and tB):[Blocks]#name
{test1,test2,...,test m}{test1,...,test n}bA {tA1.1}bB
{tB}
[Tests]name
tg tre ict tA r1s1bB tB
r1s1no
The difference between these tests is illustrated in Fig.8.Test tB is not an interconnection test,hence,ict (inter-connection test)is marked as no.It means that there will be a connection between r1to bB and from bB to s1,marked as TAM for tB in Fig.8.Test tA,on the other hand,is an interconnection test with bB.It means that r1is connected to bA and bB is connected to s1.The required TAM is marked as TAM for tA in Fig.8.
5T EST D ESIGN A LGORITHM
In this section,we describe the proposed test design algorithm (outlined in Fig.9,and detailed in Fig.10and Fig.11).
In order to evaluate the cost of a test solution,we make use of (1).At a design modification,the cost change before and after modification is given by:
eá ? táT AM ? T;
e4T
where á (áT AM )is the difference in test time (TAM cost)before and after the modification.
The TAM cost is given by the length l and its width w (T AM ?l ?w )and by combining the cost function (1)considering only one testable unit and the test time versus TAM cost (2),the optimal TAM bandwidth is given by [11]:
w ?????????????????????????????????e ? T=e ?l Tp :e5TA detailed description of the algorithm (Fig.9)is in
Fig.10(test set selection algorithm)and Fig.11(test scheduling and TAM design).The algorithm starts by the part given in Fig.10,where the list of test sets for each testable unit is sorted based on the cost function (1).The cost for each testable unit is locally optimized;however,there is,at this point,no global consideration on the sharing of TAM wires or conflict avoidance.For each testable unit,the first set of tests for each testable unit is selected and the set is scheduled and the TAM is designed (Fig.11).From the test schedule,the test application time is given and,from the TAM layout,the TAM cost for the solution is given.The algorithm checks the use of resources from a Gantt-chart for the solution (explained below in Section 5.1).For example,assume that a test solution generates a Gantt chart as in Fig.12,where TG:r1is the critical resource.For all tests that use the critical (limiting)resource,the algorithm tries to find alternative tests.Equation (4)is used to evaluate the change in cost for each possible alternative (at the critical resource).Instead of trying all possible alternatives,a limited number of design modifications (given from the Gantt chart)are explored.And,to reduce the TAM cost,existing TAMs are reused as much as possible (a test may be delayed and applied later).
234IEEE TRANSACTIONS ON COMPUTERS,VOL.55,NO.2,FEBRUARY
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Fig.8.Illustration of TAM requirements for a core test and an interconnection
test.
Fig.9.The algorithm.
5.1Resource Utilization
We make use of a machine-oriented Gantt chart to track bottlenecks (the resource that limits the solution)[3].We let the resources be the machines,and the tests be the jobs to show the allocation of jobs on machines.For example,a Gantt chart is given in Fig.12,where test B2needs TG:r2and TRE:s2.An inspection of Fig.12shows that TG:r2and TRE:s2are not critical to the solution.On the other hand,test source TG:r1is the most critical one.It means that testA,testB1,and testC are the obvious candidates for modifica-tion.The Gantt chart pinpoints bottlenecks and therefore reduces the search for candidates for modification.Note that the Gantt chart does not show a valid schedule,only the usage of resources in the system.
5.2Illustrative Example
We use the design example in Fig.13to illustrate the algorithm described above.The example (Fig.13),simpli-fied by removing power grids,memory limitations,and the list of general constraints,consists of two cores,each with a single block (testable unit),where each block can be tested in two ways;there are two alternative test sets for each block.For instance,blockA can be tested by testA1or testA2.Each of the tests is defined with its test time,combination of test sink and test source,etc.
The algorithm proceeds as follows:Initial step:For each block,the test sets are ordered ascending according to the cost function ((1)assuming ? ?1):test time TAM total cost testA1:6040100testA2:10020120testB1:7240112testB2:
120
20
140
The evaluation results in the following sorted lists per block (first in the list is the best candidate):blockA:{{testA1},{testA2}}blockB:{{testB1},{testB2}}
LARSSON
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SYSTEM-ON-CHIP DESIGN EXPLORATION PROCESS 235
Fig.
10.Test set selection algorithm.
Fig.11.Test scheduling and TAM design algorithm.
Fig.12.A machine-oriented Gantt chart [3].
The first set of tests are selected as active,that is,for blockA {testA1}and for blockB{testB1}.The test scheduling algo-rithm sorts the tests based on test time and starts with the longest test,making the test schedule:testB starting at time0 followed by testA starting at time72.The resulting total test application time is132.The TAM design algorithm connects TG1,coreB,coreA,and TA1,and the Manhattan length is 20t20t20?60.The total cost(at ? ?1)for the test solution is then:132(test time)+60(TAM cost)=192.
From the Gantt chart for this test solution,we observe that TG1and TA1both are used for132time units,while TG2and TA2are not used at all and we note that TG1and TA1limit the solution.Based on the Gantt-chart,the algorithm tries to find an alternative that does not use TG1and TA1.For each test that uses the limiting resources in the Gantt chart,in our example TG1and TA1,the algorithm computes the alternative cost of using other resources.It is important to note that,in order to limit the number of possible options,we only try with the tests that depend on the resources critical to the solution.
As the first alternative modification,we try to use testA2 to test BlockA instead of using testA1.It means that testA1 will not be executed(only one of the set of tests for each block is required and each list contains only one test).We evaluate the impact of the test modification on the TAM layout and we observe that we do not have to include coreA in the TAM layout.Taking coreA out of the bus layout means that TAM corresponding to20units can be removed (testA2makes use of different test resources compared to testA1).However,in order to execute testA2,we have to include wires from TG2to coreA and from coreA to TA2. The additional required wiring corresponds to20units.
The difference in test time between testA1and testA2is (100à60?)40.It means that the total cost difference is estimated to be:à20(gain by not including coreA for testA1)+20(what we have to add to include TAM for TG2->coreA->TA2)+40=40.
For the second alternative modification,we try testB2 instead of testB1.It means that a TAM(length and width) corresponding to20units can be removed.The additional TAM cost of adding testB2(its resources)is20and the difference in test time between testB2and testB1is48 (120à72).The cost difference for this alternative is à20t20t48?48.
In this example,we have two tests using the resources that are critical to the solution and we also had only one possible alternative per test.Since the first alternative is better than the second,the first one is selected.A new test schedule and a TAM layout are created where both testA1and testB1are
236IEEE TRANSACTIONS ON COMPUTERS,VOL.55,NO.2,FEBRUARY
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TABLE1
Design
Data
scheduled to start at time 0and there are two TAMs,one connecting TG2->coreA->TA2with a length 20and one connecting TG1->coreB->TA1with length 40.The total cost is 60t72?132(an improvement from 192to 132).
6E XPERIMENTAL R ESULTS
The objective with the experiments is to check that the proposed technique produces high quality solutions at a reasonable computational cost (CPU time).For comparison purposes,we compare the proposed technique with the
LARSSON AND PENG:POWER-AWARE
TEST PLANNING IN THE EARLY SYSTEM-ON-CHIP DESIGN EXPLORATION PROCESS 237
TABLE 2Results
technique[11]that does not support core selection and two techniques that do support selection,an estimation-based technique[10]and a pseudoexhaustive algorithm.The technique[11]that does not support core selection is used as a reference point to show that the test solution can be improved by allowing selection of tests and cores;the estimation-based technique,which tries to predict the cost at a low computational cost,is used to demonstrate that finding a high quality test solution is not trivial;and the pseudoexhaustive algorithm,which basically tries all possible solutions,is used to demonstrate that the search space is enormous in size.
We have created a set of nine designs with data as in Table1.The experimental results are collected in Table2, where we have used ? ?1for the cost function,and the total cost is therefore the sum of the two.Table2reports test application time,the TAM cost,and the CPU time.Note that the total cost is optimized,which means that the combination of test time and TAM cost are optimized.It can lead to cases where one of the optimization parameters(test time or TAM cost)is not minimal since the algorithm can find a solution where the most optimization can be gained from the other parameter and,most importantly,the combination of the two,which is optimized,is minimal. In the experiments,we compared the test scheduling and TAM design technique[11],the estimation-based technique, and the pseudoexhaustive technique with the proposed technique for test set selection.For the test scheduling and TAM design technique[11]that does not allow core selection and test set selection,we assumed preselected cores and test per testable unit for the experiments.We explored different strategies for the preselection.In experi-ments1,2,and3,we selected the cores with the lowest test time of an ATE test as well as BIST test.In experiments8 and9,we selected the cores that consumed the lowest test time and,also,the lowest power.The results show that,by allowing selection,it is possible to select cores and tests in a such a way that the total cost of the test solution is reduced. The results show that the proposed technique produces results that are better than the results produced by the estimation-based technique and near the results produced by the pseudoexhaustive technique.The computational costs(CPU time)for each of the experiments are all reasonable,but,for the pseudoexhaustive technique on experiments4,6,and7,we terminated after12hours; hence,the total cost for each one is the best found until abortion time.
7C ONCLUSIONS
Test design is traditionally considered as a final step in the system design-flow.However,as test design is becoming a significant part in terms of cost in the design-flow,it is important to consider test design as early as possible in the design-flow.Technology development has made it possible to design high-speed system chips that are shrinking in size but include an increasing number of transistors.In these system chips,the number of fault sites increases drastically and,therefore,a high test data volume is required.It is becoming important to consider test planning as early as possible in the design-flow.In this paper,we propose a technique where system test design is included in the core selection phase.The advantage is that the technique makes it possible to explore the impact of test design already taking a system’s global perspective when deciding on which cores to be used to implement the system.The proposed technique can be used to explore the impact of 1)the core selection on the test solution,2)the test set partitioning(BIST size versus ATE size)on the test solution, and/or3)the placement of test resources(test source and test sink)on the test solution.
Prior works assume a system where cores,tests,and placement of test resources are already fixed when test planning is to be performed.It means that test scheduling and TAM design are the main problems.Our approach includes the interdependent problems of test scheduling, TAM design,test set selection,and test resource placement, together with core selection.Our technique defines a test solution where the test time and the TAM routing cost are minimized while test conflicts and power limitations are considered.
Test power consumption is becoming an important aspect to be considered;however,previously proposed power models have all been rather simplistic and have only focused on the global power budget.We have improved test power modeling by introducing a three level power budget model:system-level,power-grid(local hot-spot) level,and core-level.The advantage is that,with such a model,it is possible to have more elaborate power constraints on where the power is consumed in the system, at cores,at certain hot-spot areas,and at the global level.
The design space is enormous when integrating core selection,test set selection,test resource placement,and TAM design and,in order to limit it,we make use of Gantt charts to find the limiting resources(bottlenecks).For validation of the proposed technique,we have implemen-ted the proposed technique,an estimation-based technique, and a pseudoexhaustive technique.We have compared the three techniques with a technique where cores and tests are selected prior to scheduling and TAM design and the results show that the total cost can be reduced by including core selection and test selection.Further,the experimental results show that the pseudoexhaustive technique cannot produce solutions within a reasonable CPU time and the estimation-based technique does not produce high quality solutions.The proposed technique can,on the other hand, produce high quality solutions at a reasonable CPU time.
A CKNOWLEDGMENTS
This research is partially supported by the Swedish National Program STRINGENT.A preliminary version of this paper was presented at the International Test Con-ference in2004[16].
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Erik Larsson received the MSc,Tech.Lic,and
PhD degrees from Linko
¨ping University in 1994,1998,and 2000,respectively.From October 2001to December 2002,he held a Japan Society for the Promotion of Science (JSPS)funded postdoctoral position at the Computer Design and Test Laboratory at the Nara Institute of Science and Technology (NAIST),Nara,Japan.Currently,he is an assistant professor and director of Studies of the Division for
Software and Systems in the Department of Computer and Information
Science,Linko
¨ping Universitet,Sweden.His current research interests include the development of tools and design for testability methodolo-gies to facilitate the testing of complex digital systems.The main focuses are on system-on-chip test scheduling and test infrastructure design.He is the author of the book Introduction to Advanced System-on-Chip Test Design and Optimization (Springer 2005)and is a coguest editor for the IEE Computers &Digital Techniques special issue on resource-constrained testing of system chips.He received the best paper award for the paper “Integrated Test Scheduling,Test Paralleliza-tion and TAM Design”at the IEEE Asian Test Symposium (ATS)2002and he supervised the thesis which was selected as the best thesis by Fo
¨reningen Svenskt Na ¨ringsliv,2002,and the thesis which was selected as the best thesis in the Department of Computer Science,2004.He is a member of the program committee of Design and Test Automation in Europe (DATE)2004,2005,2006,the IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS)2004,2005,2006,and the Workshop on RTL ATPG &DFT (WRTLT)2005,2006.He is a member of the IEEE.
Zebo Peng (M’91-SM’02)received the BSc degree in computer engineering from the South China Institute of Technology,China,in 1982and the Licentiate of Engineering and PhD
degrees in computer science from Linko
¨ping University,Sweden,in 1985and 1987,respec-tively.Currently,he is a professor of computer systems,director of the Embedded Systems Laboratory,and chairman of the Division for Software and Systems in the Department of Computer Science,Linko
¨ping University.His research interests include design and test of embedded systems,electronic design automation,SoC testing,design for testability,hardware/software codesign,and real-time systems.He has published more than 180technical papers in these areas and coauthored the books System Synthesis with VHDL (Kluwer,1997),Analysis and Synthesis of Distributed Real-Time Embedded Systems (Kluwer,2004),and System-Level Test and Validation of Hardware/Software Systems (Springer,2005).Professor Peng was a corecipient of two best paper awards at the European Design Automation Conferences (1992and 1994),a best paper award at the IEEE Asian Test Symposium (2002),a best paper award at the Design Automation and Test in Europe Conference (2005),and a best presentation award at the IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (2003).He has served on the program committees of a dozen international conferences and workshops,including ATS,ASP-DAC,DATE,DDECS,DFT,ETS,ITSW,MEMOCDE,and VLSI-SOC.He was the general chair of the Sixth IEEE European Test Workshop (ETW ’01),the program chair of the Seventh IEEE Design &Diagnostics of Electronic Circuits &Systems Workshop (DDECS ’04),and the test track chair of the 2006Design Automation and Test in Europe Conference (DATE ’06).He is the vice-chair of the IEEE European Test Technology Technical Council (ETTTC).He is a senior member of the IEEE.
.For more information on this or any other computing topic,please visit our Digital Library at https://www.doczj.com/doc/ac2830132.html,/publications/dlib.
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外汇保证金交易新手入门 【字体：大中小】【收藏】【复制网址】【打印】 随着网络炒汇的兴起，外汇保证金交易飞速发展。相对于外汇实盘交易来讲，保证金交易最大的特点是以小搏大，其利用杠杆效应，使实际交易金额在原基础上放大几十倍甚至上百倍。 何谓外汇保证金交易？作为一种外汇交易方式，外汇保证金系由外汇期货衍生而来，它们具有共同的特点：都是合约而不是现货，看涨看跌都有可能获利，并且都具有保证金放大功能。二者的区别是，前者没有期限的约定，可以长期持仓。 作为一种投资工具，外汇保证金交易拥有适合不同类型投资者的优点：杠杆灵活，目前国内拥有自主交易平台并推出外汇保证金交易的三家银行——交通银行、中国银行、民生银行，其杠杆倍数从5倍到30倍不等；可以双向交易投资，没有熊市、牛市之分；资金进出灵活，随时可以补仓也可以调回资金；24小时连续交易，投资者能自主安排交易时间。另外，全球外汇市场交易量巨大，几乎没有被庄家操纵的可能，即使是国际财团抑或一国央行。 炒汇不需要高深的学问。知名外汇分析师何志成认为，“只要一台连接宽带的电脑，一个高中生都可以炒汇”。一般来讲，炒汇获利的主要因素是心理素质、经验积累、信息分析和一定程度的运气。 开户步骤 开设交易账户步骤 交通银行“满金宝” （目前仅限上海地区） 1、在中行网点办理CA证书，领取数字证书软盘和密码信封，并支付10元的证书工本费； 2、持本人有效身份证件和主账户为活期一本通的长城电子借记卡至上海市分行各理财中心办理开户及签约手续，限本人办理。 中国银行“外汇保” 1、办理交行个人N太平洋借记卡； 2、在交行网点将人民币兑换成美元，存入办好的太平洋借记卡内；
许强《外汇交易快速入门》 (一) 觀念篇 1.人人平等﹑機會各半 2.風險大小操之在我 3.小戶一樣有機會 4.是投資不是賭博 5.我們是人不是賭神 (二)買賣實戰篇 6.從小錢做起 7.先學虧再學賺 8.不怕錯就怕拖 9.止蝕單永隨左右 10.撿了銅板﹑掉了金塊 11.不要敢虧不敢賺 12. 重勢（市）不重價 (三) 贏家教戰手冊篇 13.乘風破浪｀順市而爲——市匯楊百萬的故事 14.不要猜頭猜底,去頭去尾賺中間；留一點給別人賺 15.控制好自己的ＥＱ
1、人人平等﹐機會各半 客戶最常問我的一個問題之一是﹕投資期貨﹑外匯是不是很多人賠錢﹖難道真是十賭九輸嗎﹖我十有八九也立即反問我的客戶﹐如果有人輸錢﹐而且很多人輸錢﹐那請問錢輸到哪里去了﹖輸到神秘而且常讓舟船無故消失的百慕達大三角嗎﹖答案當然不是。真正的答案是當你買入時﹐市場相對地有人賣出﹔當你賣出時﹐市場相對有人買入。故你輸錢﹐市場必定有人賺錢。哪里會大部份虧損﹐是“贏家”贏走了大部份的錢. 我久居金融投資中心新加坡﹐以前也在臺北的大型外資銀行工作多年。姑且不論自己的操盤能力﹐周遭所及﹐放眼望去﹐交易高手彼彼皆是﹐看他們賺市場的錢﹐有如呼吸一樣簡單自然。多年的磨煉(當然也有年輕天生者)使之有節奏地長期從市場中獲取豐厚的回報率。事實證明這個市場有輸家﹐就有贏家。看錯的送錢給看對的﹐贏家贏盡天下﹐沒有僥倖﹐真有專家在長期贏錢。買家賣家其實機會幾乎各半(當然買賣手續費須合理的前提下)﹐無關乎學歷﹑身份﹑地位﹑家勢背景。概率一半一半﹐在機會之神面前﹐人人平等。而且做多做空,買大買小全由自己決定﹐沒人能勉強﹐是世界上最公平的市場。 至於誰賺誰賠，誰賺多誰賺少，也無一定公式可循。市場的參與者包含了各國中央銀行.金融機構.公私企業及社會大衆。因參與者的目的不同，故無法用其進出場價格定義賺賠。 大多數國家中，中央銀行的主要功能在監督金融體系的運作，並維持金融體等穩定成長，以實現政府的政策目標。中央銀行必須負責監督本國貨幣對外國貨幣的價值。若因貨幣兌換價值的改變而影響到本國經濟的發展，中央銀行就必須出面干預以維持其兌換價值，以保護本國産業及經濟的發展。因此中央銀行不只要維持一個有次序｀有效率的外匯市場，而且扮演外匯的最終供給者或需求者。故中央銀行對所擁有的外匯頭寸以穩定的組合爲主，不以賺取彙差爲目的。 另外金融機構亦扮演了舉足輕重的角色，亦可說是最主要的參與者。其規模大者，甚而可與中央銀行之力量抗衡而左右市場。若持有自營頭寸，則涉及很大的賺賠損益。 而各企業亦需要通過其在外匯市場的參與，以達到商品｀勞務的交易與資本移動等目的，亦是外匯市場的主要參與者。 社會大衆因其有國外旅行｀商務｀國際投資與投機等需求，亦爲外匯市場的重要參與者。各參與者必須視本身之個別需求，以控制期貨﹑外匯風險爲首務，進而累積成功交易的經驗，加上好的市場分析及資金管理，從行情中賺取利潤。虧少賺多，慢慢便能站到贏家的行列。 2、風險大小﹐操之在我 我們做任何生意皆有風險﹐皆在獲利前付出“成本”。就是開一個小店鋪也需店租﹑裝修﹑員工薪水﹐每月維持開銷的費用﹐而且還不保證賺錢。也就是說獲利與風險是一體兩面之物﹐常伴隨接踵而至。投資國際市場一如開店鋪﹐不可腦中只想如何好賺﹐如何發大財去吃魚翅鮑魚。應先在心中估算出願意付出的“成本”有多少﹐也就是說其實外匯投資的風險大小可完全在自己的掌握之中。主要的風險控制方式﹐就是善用止損單(STOP LOSS ORDER)。你必須在進場的同時﹐就訂立出認賠的額度﹐設好止損(單)點﹐預先下好萬一斷臂的單子。
外汇交易技巧初级教程 Company Document number：WUUT-WUUY-WBBGB-BWYTT-1982GT
外汇黄金股票喊单咨询收费群,每月赢利8％－10％，史上最大优惠，月费只需200 元，每天 美元，每天仅限前10 名，报名联系李财师卧龙师兄 外汇黄金股票喊单咨询收费群 你是否还在亏损的泥潭里苦苦挣扎你是否认真想过自己为什 么在市场中亏钱你是否想把亏损的资金从市场中赚回来你 是否想成为金融战场中的强者不用犹豫，赶快加入我们团队， 散户一样可以轻松获利，从市场中赚取大量美金．老李投资团队由五名核心成员组成，有近十年的投资理财经验，从事过股票、期货、黄金、外汇等各类投资，分析技术成熟而且全面，具备专业的投资心态和良好的资金管理策略，已经成功为广大汇友、期友、股民带来丰厚的收益！！外汇黄金每天在线喊单盈利30-100点，每天至少一单，最多三单。每天美元，你可以像我们 的分析师一样轻松赚到30-100 点．股票咨询服务，告诉你在慢 牛市中如何把握行情，真正赚到利润,每周推荐一只股票，每月至少推荐一只金股．为回报朋友们一直以来的默默支持，回馈新老朋友，现在加入本投资团队收费群，仅需月费200 元，平均 每天美元，就可以获得老李投资团队专业分析师为你提供 的喊单咨询服务，实现你的财务自由！！天堂和地狱隔着一扇门，等待你来开启！！现在加入你还将获得霸王k 线一套4h macd 交易系统资料一套，以及各类炒股、炒金、炒汇资料。由于群空间名额有限，每天我们只接收前10 名到成功投资者伊甸园。报名联系李财师卧龙师兄QQ：
外汇黄金每天在线喊单盈利30-100 点，每天至少一单，最多三单，仅需美元，另提供股票咨询，每周推荐一只股票，每月至少推荐一只金股
外汇市场并不是随便可以捡钱的地方，它是勤奋、律己和耐心的人的乐园，也是贪婪、幻想和固执的人的葬身之地。外汇走势既简单又复杂。简单的是就那么3个方向：上升下降和盘整，而复杂的是大浪之中有小波，大波之中有小浪。说它是“人性弱点的照妖镜”一点也不为过。那么做外汇需要注意那些呢？为此皇玛外汇hmarl分析师就给我们大家讲解一下外汇交易需要注意的事情。 第一：完善思维上的交易系统，一个完善的交易系统是系统交易思维的立体化。系统交易思维是一种理念，它体现为在行情判断分析中对价格运动的总体性的观察和时间上的连续性观察。交易系统必须能够充分体现你的操作规则的每一个细节，必须是机械性和灵活性的结合体。通俗一点就是你的思维交易系统必须能够应付行情的各种变化，兵来将挡，水来土掩。 第二：炒汇前的准备 1. 确定风格：根据自己的性格和习惯确定适合自己的风格。短线、中线和长线的操作规则是不同的。短线是短平快，要求命中率得高，快进快出，绝不能有丝毫贪婪和幻想。中线是稳准狠，长线要结合基本面分析。 2. 制定规则：根据自己的风格制定交易规则。 (1). 趋势判断规则：趋势的判断是炒汇的重中之重。顺势交易是炒汇的基本原则。所谓大趋势是由一级一级小级别的趋势累积形成的。汇价的运行规律是趋势过去是盘整，盘整过后是趋势，周而复始，循环往复。具体操作时应该先看大势，然后到小级别图上等候汇价运行方向顺应大趋势时进场。汇价的高点低点依次抬高是上升趋势，依次降低是下降趋势。汇价的高点和低点一般不会呈直线运行，用画趋势线的方法判断趋势应注意趋势线的修正。通过趋势判断应该得出以下几个结论： (a)：当前趋势：大趋势里面有小波段，观察当前汇价运行在大趋势的顺势波段还是逆势波段，只做顺势波段。 (b)：趋势状态：当前汇价运行到本趋势的前期中期还是后期，前期是趋势延续，中期是趋势放缓，后期是趋势停顿。在同一趋势里汇价运行到不同时期的操作方法截然不同。前期应该等回撤顺势进场，中期的时候应该无单观望有单持单，后
深圳市优质结构工程奖申报表 项目名称: 主体结构施工单位：（盖章） 桩基施工参建单位：（盖章） 申报日期: 深圳建筑业协会制
填表说明及申报要求 一、填表说明 1. 填表字迹应该工整； 2. 工程名称、工程地址、建设（开发）单位、设计单位、监理单位、施工企业名称应详细，并填写全称； 3. 建筑类型栏:可在相应栏目后的括号中打勾选择。 二、申报范围 (一）工业与民用建筑工程 1、单体建筑面积在5000平方米以上的公共建筑工程或住宅工程； 2、建筑面积在30000平方米以上设施配套的住宅小区或群体工程； 3、1000座位以上的剧院或礼堂、3000座位以上的体育馆、20000座位以上的体育场； 4、5000平方米以上的生产厂房、仓库。 （二）市政工程 1、投资在1000万元以上的桥梁、城市道路（该标段中的桥梁、箱涵、永久边坡、给水排水管道工程中的不开槽施工管道主体结构、城市人行天桥与人行地道等必须申报深圳市优质结构工程奖）等基础设施工程； 2、投资在5000万元以上的污水处理厂、水厂、城市轨道交通、隧道等工程。 二、申报要求 1. 所有施工资料必须采用现行的《广东省建筑工程竣工验收技术资料统一用表》电子版编制； 2. 施工材料的检测必须全部选用建设行政主管部门颁发的有资质证书的试验室； 3．主体工程各工序开始施工前，项目上必须首先施工样板供专家组验收，样板验收通过后，方可全面开展各工序施工； 4. 结构评优汇报资料应按“深圳市优质结构工程验收汇报提纲“要求准备，该资料可在深圳建筑业协会网站“网上申报通道”中的“资料下载”栏目中下载； 5．结构评优检查和验收要求必须按“深圳市优质结构工程评审程序”进行，该资料可在深圳建筑业协会网站“网上申报通道”中的“资料下载”栏目中下载； 6．结构评优工程资料必须按“优质结构工程资料检查要求（土建部分）”和“优质结构工程资料检查要求（钢结构部分）”要求准备，该资料可在深圳建筑业协会网站“网上申报通道”中的“资料下载”栏目中下载； 7．桩基施工单位是否作为结构评优的参建单位由桩基施工单位自行选择，但上部主体结构施工单位参评主体结构评优必须包括桩基部分； 8．2010年7月1日以后开工的项目，如果申报深圳市优质工程金牛奖的工程必须获得“深圳市建筑业新技术应用示范工程奖“。 9．企业有计划参评鲁班奖的项目，需在申报深圳市优质结构评优的同时，向广东
炒外汇入门，外汇基础知识 最近有很多朋友想要炒外汇，问了我很多关于外汇的一些基本知识，想必还有更多的年 轻朋友想要靠此赚点外快。因此我从外汇论坛、…..一些权威机构，东凑西拼整理了此文章，如果觉得不够好的请原谅。 炒外汇我们需要了解几个问题的回答： 1、什么是个人外汇买卖 个人外汇买卖一般有实盘和虚盘之分,目前只能进行实盘外汇买卖。 2、个人实盘外汇买卖和个人虚盘外汇买卖有什么区别 个人实盘外汇买卖，俗称“外汇宝”，是指个人客户在银行通过柜面服务人员或其他电子金融服务方式进行的不可透支的可自由兑换外汇（或外币）间的交易。 5、个人实盘外汇买卖可交易货币有哪些 美元、欧元、日元、英镑、瑞士法郎、港元、澳大利亚元等主要货币，也包括加拿大元、荷兰盾、法国法郎、德国马克、比利时法郎、新加坡元等货币。 6、止损 在进行个人实盘外汇买卖时，如果市场汇率向不利客户的方向变化，使投资者面临较大的汇率波动风险。为了防止损失进一步扩大，投资者应及时将头寸平仓。 空头：持有卖单的投资者 多头：持有多单的投资者 空开：没有持仓的投资者，判断市场将下跌，而进行卖出开仓 多开：没有持仓的投资者，判断市场将上涨，而进行买入开仓 空平：原进行卖出开仓的投资者，进行买入平仓 多平：原进行买入开仓的投资者，进行卖出平仓 7、外汇市场 外汇市场是指由银行等金融机构、自营交易商、大型跨国企业参与的，通过中介机构或电讯系统联结的，以各种货币为买卖对象的交易市场。它可以是有形的---如外汇交易所，也可以是无形的---如通过电讯系统交易的银行间外汇交易。 █外汇市场的特点 如果从外汇交易的区域范围和周围速度来看，外汇市场具有空间统一性和时间连续性两个基本特点。 所谓空间统一性是指由于各国外汇市场都用现代化的通讯技术（电话、电报、电传等）进行外汇交易，因而使它们之间的联系非常紧密，整个世界越来越联成一片，形成一个统一的世界外汇市场。 所谓时间连续性是指世界上的各个外汇市场在营业时间上相互交替，形成一种前后继起的循
外汇交易入门基础知识 1、汇率与标价方式 汇率，又称汇价，指一国货币以另一国货币表示的价格，或者说是两国货币间的比价。 按国际惯例，通常用三个英文字母来表示货币的名称，以上中文名称后的英文即为该货 币的英文代码。 汇率又分为基本汇率和交叉汇率 基本汇率（也叫直盘或基础汇率）：一般指一国货币与美元的比价，又叫做主要货币对。六大主要货币对是： EUR/USD 即欧元 / 美元（简称欧美） GBP/USD 即英镑 / 美元 ( 简称镑美) USD/JPY 即美元 / 日元（简称美日） USD/CHF 即美元 / 瑞郎（简称美瑞） AUD/USD即澳元/美元（简称澳美） USD/CAD即美元/加元（简称美加） 交叉汇率（也叫交叉盘）：是指两种非美元货币之间的比价，交叉汇率可从基本汇率套 算而来。 按市场惯例，外汇汇率的标价通常由五位有效数字组成，从右边向左边数过去，第一 位称为“X个点”，它是构成汇率变动的最小单位；第二位称为“X十个点”，如此类推。如：1欧元 = 1.1011 美元； 1美元 = 120.55日元 欧元对美元从 1.1010变为1.1015, 称欧元对美元上升了5点 美元对日元从120.50变为120.00，称美元对日元下跌了50点。 2、汇率与美元指数的关系 各币种在美元指数中所占权重 欧元57.6% 日元13.6% 英镑11.9% 加拿大元9.1% 瑞士法郎 3.6% 由于欧元所占权重大，所以EUR/USD走势和美元指数一般来说是呈现较紧密负相关 的关系，如美元指数涨，EUR/USD跌；在实盘中，可以结合美元指数判断欧美走势。（有 些交易商也将美元指数作为交易品种）其他有些汇率虽然也跟美元指数有相关性，但并 不是非常紧密。 欧美也是汇市中交易量最大的品种，技术走势也最为标准，最适合新人操作。而日 元虽然权重也较大，但美日走势一般来讲波动较小，跟美元指数相关性也不是很紧密， 个人认为除非大机会，一般不操作。
外汇交易新手需要了解哪些基础知识？ 想要成为外汇高手，那是需要大量的时间和精力的，所以需要打好基础。为了避免更多的交易者在自我摸索中走太多的弯路，在此就给大家介绍一下，外汇交易入门需要掌握的哪些基础知识，新手交易者从这里开始学习可以取得更好的效果。 了解外汇市场的特点 由于所处的时区不同，各外汇交易市场在交易时间上此开彼关，市场的参与者可以在世界各地进行涨跌双向交易，市场便捷灵活、交易透明，资金流动顺畅，市场间的汇率差异极小，形成了全球一体化运作、全天候运行的国际外汇交易市场。 了解如何选择外汇平台 对于外汇新手来说，最快融入到外汇市场的方法莫过于找一个可靠的外汇交易平台。继续以之前提到的巨汇ggfx为例，作为一个正规的国际平台，巨汇ggfx有国际上比较权威的FSP和NFA的双重监管，使用最稳定的MT4平台提供交易，在业内拥有最快的秒速交易和闪电出金的操作速度，安全性和稳定性皆有保障。而且它有针对新手的导师1对1指导服务，可以帮助新手快速入门。 了解基础货币 新手进入外汇市场，首先必须要了解的就是可交易的基础货币有哪些。目前外汇市场上可交易的每一种货币，都有国际统一的符号，如：USD(美元)、EUR(欧元)、GBP(英镑)等。而需要注意的是外汇都是以货币对形式交易，例如：欧元/美元(EUR/USD)或美元/日元(USD/JPY)等。 了解点差的概念 点，即“最小浮动单位”。如英镑美元(GBPUSD)的报价是0.98000，若英镑美元的报价变为0.97990，就可以说英镑美元的价格波动了1个点。在外汇市场上，点差就是投资者的交易成本，点差越小成本越低，因此巨汇ggfx等低点差、低手数交易的平台普遍受到大众投资者的喜爱。 学会控制风险 投资有风险，尤其是在震荡的行情中，也许上一秒还在盈利，下一秒已经亏损。所以建议新手一定要学会止损，不要贪图一时的利益，有小利皆可出，若无小利，当行情与自己预期的走势不同时，也要先退出市场观望。 最后，做外汇投资也和大多数投资一样，保持良好的心态非常关键，但是也最难做到建议投资者们在外汇投资中遇到问题时一定要头脑清晰，避免盲目操作交易。
申报省、市优质结构工程的条件及所需资料 ①、申报条件： a、单位公共建筑工程，建筑面积在8000平方米以上； b、单位住宅工程，建筑面积在5000平方米以上； c、实行总承包制的住宅小区，总建筑面积在50000平方米以上； d、总造价在2000万元以上的道路、桥梁、供水、供热、供气、污水处理等市政基础设施工程； e、实行总承包制的建筑面积10000平方米以上的村镇； f、投资在3000万元以上的大中型企业新建、扩建项目。 ②、所需资料： a、河南省、市优质结构工程评审报表； b、工程施工组织设计； c、创优质结构工程质量目标及质量保证措施； d、监督注册表（工程立项批文）； e、施工图审查批准书； f、工程抗震设计审批书； g、建筑工程消防设计审核意见书； h、建设工程规划批准书； i、建设工程施工许可证或开工报告； j、结构工程验收报告； k、市优质结构工程证书（申报河南省优质结构工程必须提供）； l、工程照片（按要求制作光盘）； m、工程录像； n、优质结构工程附表（附各方资质证明复印件） p、申报费0.5元/平方米；（申报省、市优质结构工程申报费各为0.5元/平方米。）
③、检查内容及节点： 第一次检查点： （1）、桩基础的工程，在承台梁砼施工完1/2、模板已拆，能反映砼的截面尺寸及外观质量，另外1/2承台梁钢筋绑扎及模板支撑完。 （2）、条形基础的工程，在条形基础砼施工1/2，其他同（1）。 （3）、带有地下室的工程，在地下室±0.00处梁板砼施工1/2，其他1/2的钢筋绑扎、模板支撑完毕。 第二次检查点： 主体施工至1/3—1/2期间，能看到钢筋绑扎、模板支撑、砼外观、砌体工程。工程第二次检查完后，需要检测；检测的内容包括：混凝土构件的强度；构件钢筋的数量，保护层；层高，轴线尺寸。工程经检测合格后方可进入装饰。 第三次检查点： 主体结顶，检查包括钢筋绑扎完毕、砼浇注期间或砌体。 申报材料在第一次检查前：注：项目部提前7个工作日通知公司质量管理部以便安排检查。并将完整同步的技术资料上报公司审核。 以上1-9、14项材料在省、市第一次检查前15-20天报公司质量安全环境管理部；10-13项材料在第三次现场检查后1个月内报到公司质量安全环境管理部。
外汇交易新手入门：认识最简单的外汇交易系统 一个最简单的交易系统，至少包括四个部分：买进，卖出，止损，头寸控制。 作为投机者，我们是在利用市场的价格波动来获得利益。只有当市场出现你所能够把握的波动的情况时，你才有可能获利--看起来很简单，但是这一点非常非常重要--就是说，一些波动你能够把握，另一些波动你不能把握，或者根本不需要，比如向下的波动(股票市场)，或者幅度非常小的波动。因此，交易是参与你的系统能够参与的波动，而不是所有的。 一、买进 一个交易是一个过程，不是一次简单的预测。简单的说，你要判断在什么情况买入，买多少，如果市场并非想你想象的发展，你应该如何处理你的头寸，如果市场向你想象的那样发展，你应该如何处理。 在我的交易系统(杠杆操作法)中，关于买入有四个原则： 1、在简单上升趋势中买入; 2、在复杂上升趋势的回调中，出现向下分形的时候买入; 3、向上突破前期高点的时候买入; 4、在横盘趋势停顿的下沿买入;
这四条原则是买入交易的基本原则，当市场没有出现这四中情况之一的时候，我根本不会考虑买的。巨汇外汇分析师这么写的意思，并非要你也这么做，而是想说，做为交易者，你同样需要类似的原则，在你的交易系统中。另外，你还需要相当的卖出的原则。 二、卖出 如果你有一些交易经验，很多时候对市场变化会有一些“感觉”，这些“感觉”应该建立在你的交易系统之上。我们相信，交易在更多的时候是要依靠感觉的。 当市场按照你的系统发展的时候，你不需要做什么，耐心看着就可以，你必须明白，就交易的行为而言，是一瞬间的事情，一年二百多个交易日，真正交易的时候，可能只有几个小时，其他都是漫长而寂寞的等待。 在市场有利的时候，你必须学会习惯于获利，这是区别交易者是否成熟的一个重要标志。假设你的成本是8元，市场价格现在是80元，但是趋势依然向上，你是否会坚定的持有?很多的交易者在获利的时候惴惴不安，而亏损的时候却心安理得，这样如何能够长期稳定的获利?
炒外汇入门详细全集 入门入籍，建议你看了后再加油看蜡烛图分析，货币战争等。 炒外汇教程 1、什么是个人外汇买卖？ 答：个人外汇买卖一般有实盘和虚盘之分,目前只能进行实盘外汇买卖。 2、个人实盘外汇买卖和个人虚盘外汇买卖有什么区别？ 答：个人实盘外汇买卖，俗称“外汇宝”，是指个人客户在银行通过柜面服务人员或其他电子金融服务方式进行的不可透支的可自由兑换外 汇（或外币）间的交易。 个人虚盘外汇买卖，是指个人在银行交纳一定的保证金后进行的交易金额可放大若干倍的外汇（或外币）间的交易。 3、个人实盘外汇买卖业务与传统的储蓄业务有什么不同？ 答：传统的储蓄业务是一种存取性业务，以赚取利息为目的。个人实盘外汇买卖是一种买卖性业务，以赚取汇率差额为主要目的，同时客户还可以通过该业务把自己持有的外币转为更有升值潜力或利息较高的外币，以赚取汇率波动的差价或更高的利息收入。 4、哪些人可以进行个人实盘外汇买卖？
答：凡持有有效身份证件，拥有完全民事行为能力的境内居民个人，具有一定金额外汇（或外币）均可进行个人实盘外汇交易。 5、个人实盘外汇买卖可交易货币有哪些？ 答：美元、欧元、日元、英镑、瑞士法郎、港元、澳大利亚元等主要货币，也包括加拿大元、荷兰盾、法国法郎、德国马克、比利时法郎、新加坡元等货币。 6、个人实盘外汇买卖可以进行那些货币之间的交易？ 答：客户可以通过个人实盘外汇买卖进行以下两类的交易：一、美元兑欧元、美元兑日元、英镑兑美元、美元兑瑞士法郎、美元兑港元、澳大利亚元兑美元（还可以进行美元兑加拿大元、美元兑荷兰盾、美元兑法国法郎、美元兑德国马克、美元兑比利时法郎、美元兑新加坡元）。二、以上非美元货币之间的交易，如英镑兑日元、澳大利亚元兑日元等，在国际市场上，此类交易被称为交叉盘交易。 7、个人实盘外汇买卖中的基准货币指的是什么货币？ 答：在个人实盘外汇买卖中，英镑、澳元、和欧元兑美元的报价，英镑、澳元和欧元是基准货币，其余的货币兑美元的报价中，美元是基准货币。 8、客户手上只有人民币没有外币，可以进行个人实盘外汇买卖吗？
操盘手教程外汇交易 Prepared on 22 November 2020
谭建飞先生外汇交易培训材料精选 一. RST RST是一种相当有效的价格逆转图形，全称叫做Reverse Symmetrecal Triangle，翻成中文叫做“反向对称三角形”。这 是一种当价格振动性扩大时出现的图表形态。 我们先看一下常见的对称三角形Symmetrical Triangle 对称三角形是一般技术分析资料中经常提到的图形。 对称三角形一般来说有5 个价格转折点，其中第五点往往不接触三角形的一边，提早显示价格有可能向另一面突破。见图-9 下降趋势中的对称三角形则和上面讲的正好相反。价格在突破三角形的下边之后，往往会形成新的下滑趋势。见图-10 对称三角形这一类的图形都应用了价格的震动性在逐步由大变小之后，又会从小变大，带来价格的突破。 反向对称三角形则和上面的对称三角形正好相反。见图-11（买入图形）和图-12（卖出图形） 反向对称三角形（RST）这样的图表形态一直是存在的，但是很少有操盘手会按照RST图形进行操作，因为这类图形往往使观察者得出和我们要操作的方向正好相反的结论，特别是在即日操盘或超短线的时间阶段内。 我们做的恰恰是和大多数人得到的结论相反，当振动性达到极端时，我们就要考虑应用RST图形来选择高概率的入场时机。 在实际操作中，RST并不一定每次都是具备完美规则的对称图形，但经过一定的练习，你就不会有什么困难来找出这样的图表形态。 具体寻找RST图形的方法是从图表的右边向左看起，确认五个明显的价格转折点。最靠右边的高点或是低点就是第五点。如果这些价格转折点不全是上升高点和下降低点的话，则该图形就不能算是有效的RST图形。 从RST图形的定义来看，一个有效的RST图形必须至少包括7 条价格线，见图-13 当然，绝大多数时候一个有效的RST图形包含远远多于7 条的价格线。见图-14，这是一个RST买入图形。 图中从右向做看起，最新的一个价格转折低点为第五点。 然后我们向左确认其余的四个价格转折点。 图中价格转折高点都是上升趋势（2、4），而转折低点都是下降趋势（1、3、5）。 RST卖出图形，见图-15。 此图形和上面买入图形正好相反。 应用RST图形进行操作，我们是希望在价格出现逆转时尽早的入场，在应用RST图形时，也要尽量结合其他的分析手段，包括轴线，支撑/阻力线，振动带，费伯纳奇，移动平均线等等。 我们会结合实例对这种图表分析方法做更多讲解。
外汇新手入门教程 一、认识外汇市场 （一）外汇汇率定义 外汇汇率是一国货币对外国货币的兑换率，取决于两国相互间的国际收支状况，或两国货币的购买力，在实际经验上，外汇汇率决定于两国间的长期经济因素，也是投资人预期的表现。 （二）外汇市场 外汇市场从广义上讲泛指外汇交易场所，包括个人外汇买卖场所，外币期货交易所等；从狭义上讲是指以外汇专业银行，外汇经纪商，中央银行等为交易主体，通过电话、电传、交易机等现代化通讯手段实现交易的交易市场；外汇市场既是一个有形的市场也是一个无形的市场，有形是指外汇交易市场有自己的地理位置，比如东京外汇市场、纽约外汇市场等；而无形则是表明市场并没有一个具体的范围，个人、机构、银行之间发生货币转化也可以无形中形成外汇市场。 国际上主要的外汇市场有：悉尼、东京、新加坡、香港、法兰克福、苏黎世、伦敦、纽约，由于以上各个城市地跨多个时区，工作时间基本上为当地时间的早9点到下午4点，因此基本上可以将一天24小时覆盖。 以下按北京时间计算的各个主要外汇市场开休市时间表： 悉尼开市时间早7：00 东京开市时间早8：00 欧洲开市时间下午14：30 伦敦开市时间下午15：30 纽约开市时间晚21：00 伦敦休市时间晚24：30 纽约休市时间早4：00
了解各个外汇市场的开市时间的现实意义在于：及时掌握市场信息，通过阅读经济数据对汇率预测有很大帮助，理解汇率的真实性。 一般汇率会在市场开市的时间内较为活跃，许多重要的经济数据也会在这些时候公布。像日本央行干预日元一般都发生在北京时间的白天，也就是在东京市场开市的时候，德国、英国公布央行利率决定一般会在我们北京时间的下午5点到7点，而美国公布一些重要的数据在晚上8点半，9点半这样的时间，美联储的重要决议一般在北京时间的凌晨公布。 通常我们所说的收盘价格是指纽约市场的收市价格。 （三）外汇汇率的表达方式 工商银行的汇率表示方式一般采取的是国际常用报价方式，按照直接报价法、间接报价法进行报价。 直接报价法：以本国货币表示每一单位外国货币的价格。（本国货币是价格，外国货币是商品）例如在日本，一件衣服＝5000日元，一辆汽车＝15万日元，在日本，货币的报价方式也采用了此种方法，如1美元=118.35日元。还有几个常见的币种也是采取此报价方式：瑞士法郎（CHF）、加拿大元（CAD）、新加坡元（SGD）、日元（JPY）、港币（HKD）、瑞典克朗（SEK）。 间接报价法：每一单位的本国货币折合若干的外国货币。（本国货币是商品，外国货币是价格）如：在英国，1英镑=1.5980美元。在国际市场上：英镑（GBP）、澳大利亚元（AUD）、新西兰币（NZD）、欧元（EUR）采用此报价法。 （四）基础货币与非基础货币 基础货币是指一个货币对中写在前面的货币；非基础货币是指一个货币对中写在后面的货币。 例如：美元/日元中美元是基础货币，日元是非基础货币；欧元/英镑中欧元是基础货币，英镑是非基础货币。工商银行基础与非基础货币的表现方式按照国际常用方式。 （五）买入价（BID）与卖出价（OFFER或ASK） 在国际市场上，买入价与卖出价表示的含义是指银行准备从对手（通常指客户）那里的买入（BID）价、卖出（OFFER）价，买入价（BID）在左，卖出价（OFFER）价在右。 对于买入价与卖出价实际应用中的说明：银行所标示的买入价均是对基础货币而言的买入价格，银行所标示的卖出价均是对基础货币而言的卖出价格。例如：工商银行的美元兑日元买入、卖出价分别为109.30/109.60；即表明工商银行从客户处买入美元卖出日元使用的牌价为109.30，则客户卖出美元买入日元就要使用109.30的牌价，反之亦然。 银行的卖出价均要高于银行的买入价，也就是客户在与银行进行交易的时候，客户的买入价高于客户的卖出价；原因有二：(1)客户不论何时均可与银行进行交易，银行要无条件的买入或卖出，这样就要求银行必须要用这样的价差来保证自己的利益。(2)对于投资者而言，只有市场发生变化时，才有可能获利，如果市场没有任何变动，投资者在汇率静止的情况下，进行一买一卖是要赔钱的。而投资者的投资的目的是为了获利，获利的要素就是要求我们看准汇率走势方向，待汇市变化的时候，才有获利的可能，汇市汇率静止，客户将不可能获利。 （六）国际外汇市场主要币种及其符号 美元：USD、英镑：GBP、欧元：EUR、日元：JPY 澳元：AUD、港币：HKD、加元：CAD、瑞郎：CHF、瑞典克朗：SEK 新加坡元：SGD、挪威克朗：NOK、丹麦克朗：DKK
一．为什么投资外汇？ 1、成交量大，市场透明度高 全球外汇市场日均成交量达4万亿美元，如此大的市场不存在庄家，且外汇投资的对象是国家经济，数据和新闻都是在全球范围内共享的； 2、杠杆灵活，交易成本轻 可调节的杠杆比例可有效降低交易成本，提高资金利用率； 3、双向交易，获利不受市况所限 外汇交易可买涨，可卖跌，无论熊市牛市，只要市场行情波动均有机会获利； 4、T+0交易，24小时市场 全球7x24小时不间断的外汇市场，不同于股票，外汇是T+0交易，随时可买卖； 5、风险可控，可预设止损和限价点 通过设置止损和限价点，可以帮助交易者及时控制亏损或锁定获利； 6、交易迅速，即时成交无需等待 在通常的市况下，所有订单都可以在指定的价位或者指定的范围内即时成交。 二．外汇基础知识 认识外汇市场 外汇市场，也称为“FOREX”或“FX”市场，是全球最大的金融市场，其日交易量达到 4万亿美元。巨大的交易量，使得任何一个机构都没有能力操纵这一市场，价格的走动有规律可循，对普通的投资者比较公平。 外汇市场是真正意义上的全球市场，目前世界上有30多个主要的外汇交易市场，由于时差的关系，一国的交易结束将有其他国家的交易开始，如此形成了周一到周五，7x24小时的不间断的全球性外汇市场。24 小时的市场使得外汇交易者可以根据自己的生活习惯安排交易时间，以及对每一时段发生的经济，社会和政治事件所导致的外汇波动做出反应，获得交易机会。这也是为什么众多上班族选择炒汇的原因之一。 认识外汇交易 外汇交易是指投资者利用货币之间兑换率的变动，赚取其中的差额。因为兑换率是两个货币之间的兑换比率，所以外汇是以货币对的形式进行交易的，每一种货币对都有特定的符号，例如欧元/美元(EUR/USD)或美元/日元(USD/JPY)。买卖一个货币对，实际上意味着买卖两种货币之间兑换率的升跌。
关于印发《成都市优质结构工程评选暂行办法》的通知 发布日期:2007-1-30 文号:成建委发[2006]306号 各区（市）县建设局，在蓉各建设、监理、施工单位：现将《成都市优质结构工程评选暂行办法》印发给你们，请遵照执行，并将执行过程中遇到的问题及时反馈给我委。 附件：1、成都市优质结构工程评选暂行办法 2、成都市优质结构工程申请表（可点击此处下载） 3、创建成都市优质结构工程计划目标书（可点击此处下载） 成都市建设委员会 二○○六年六月十六日
附件1： 成都市优质结构工程评选暂行办法 第一条为贯彻落实国家《中华人民共和国建筑法》、《建设工程质量管理条例》，引导和激励建筑施工企业加强管理，提高建设工程质量，依据国家有关技术标准和《四川省结构优质工程评审试行办法》，结合成都市实际，制定本办法。 第二条本办法适用于成都市行政区域范围内新建的房屋建筑和市政基础设施工程。 第三条本市优质结构工程评选遵循自愿、公开、公平、公正的原则，并不得收取任何费用。 第四条成都市优质结构工程是本市房屋建筑和市政基础设施工程部分施工质量的一项荣誉奖。获得成都市优质结构工程的项目是申请成都市优质工程（芙蓉杯）的必备条件。 第五条成都市优质结构工程必须保证地基基础、主体结构
安全，内坚外美，符合国家工程建设标准强制性条文和现行国家标准、规范及设计文件的要求。 第六条成都市优质结构工程由工程总承包或主承建单位自愿申报，并由建设单位、勘察单位、设计单位、监理单位共同认可。鼓励参评成都市优质结构工程的项目采用新技术、新工艺、新设备、新材料，提高工程质量。 第七条成都市优质结构工程的评审活动在成都市建设委员会领导下开展，成都市建设委员会成立成都市优质结构工程评审委员会，负责审查和认定成都市优质结构工程。评审委员会办公室设在市建设委员会质安处，负责组织、协调成都市优质结构工程的评选工作。 成都市建设工程质量监督站负责锦江、青羊、金牛、武侯、成华五城区（含高新区）范围内成都市优质结构工程的申请受理、日常核查和初评推荐工作。各区（市）县建设局可委托当地质量监督机构，负责辖区内成都市优质结构工程的申请受理、日常检查和初评推荐工作。 第八条评审委员会建立评审工作专家库。评审专家应是具有中、高级工程师的专业工程技术人员，有专业技术知识和施工
每个人都想要挣大钱，从而会进行投资，想要通过钱生钱来获得更多的利益。但在投资上，每个人都是新手，都有很多不了解的知识和技巧。这里给大家分享一些外汇投资的知识和技巧，希望对大家有所帮助。 外汇入门从何开始学起 1、仓位控管、风险控管，另一个你必须花心力学习的，就是风险控管了!所有的交易第一考量绝对不是获利，而是风险，只有做好风险控制你才能够在市场上长期存活，否则技术再牛逼也无法让你长期赚钱，市场一次又一次的告诉我们这个简单的事实，要重视你的仓位，不要轻易地让市场蚕食他，许多外汇交易者就是搞不明白这点，才不断地亏损后又入金，永远都是在亏损的循环，他们缺乏的不只是技术，而是对整个市场风险的不理解，以及不合理的仓位控管所导致。 2、K线图、技术分析，如果你刚踏入外汇交易，始终找不到方向学习的话，建议你一开始不用学习太多，先把最基本的K线图学好，只要随便一百度都可以找到很多K线图的讲解，包含之前杰克分享的「外汇交易中必学的K线图!」讲的都是最基本的K线，在外汇交易里，你学的技术不用多但要精，看是简单的K 线图背后藏着许多市场的交易情绪，不管是在任何的交易，K线图永远都不会过时!在学完K线图之后如果还有多的时间学习，那可以学习简单的技术分析，建议学最常用、最多人讨论的技术指标，这样方便找到更多的学习教程，同时也可以更好的借鉴别人的失败经验，千万不要想要学会所有技术指标，那对你的交易可能还有反效果，总之记住技术学的多不如学的少、学的少不如学的精。 3、市场是最好的老师，说到底，我们最好的学习对象，就是市场了!一个成熟的交易系统都是经过不断地试错形成的，要记住相同的错误绝对不可以心存侥幸犯两回，如果一再的重蹈覆彻，那将永远无法成长，自然难以在外汇交易中长期获利。很多人不愿意在交易前花时间、心力学习，那市场会以最直接的方式告诉我们，自己的交易究竟是好是坏，如果交易前不愿意下功夫，那就只能在亏损之后，自己慢慢地重复总结、深思了。 4、单一品种的基本面，如果你有更多的时间，除了技术分析之外你可以深入研究单一货币对或交易品种的基本面，当然这就属于比较进阶的层面了，比如专门交易欧美，你可以研究欧美的历史事件以及相应的走势，研究各国的政策对他的影响，这些就必须要长期投入大量的心力学习了。短线交易有个很大的优势，我们不需要预测各种品种的长时间走势，只需考虑到短时间的波动，我们甚至可以专挑震荡行情交易，而不让自己冒过多的风险，记住我们的目的是要获利，而不是成为某个品种的专家。 外汇新手投资的注意事项 第一，外汇跟股票，期货类的投资有很大的区别，外汇资金流动非常大，以万亿为单位，排除了个人或集团的幕后黑手，保障了市场的稳定性，但是交易更讲究规律性，所以对于技术分析要求更高。所以，请大家记住，炒外汇不能光靠运气，还要靠投资者自己认真学习相关的外汇知识和提高技术分析能力。
炒汇新手外汇入门知识 外汇市场，也称为“Forex”或“FX”市场，是全球最大的金融市场，日交易量3.2兆(3.2万亿)美元。“外汇交易”是买入一种货币，同时卖出另外一种货币。 每一种货币，都有国际统一的符号，如：USD(美元)、EUR(欧元)、GBP(英镑)、AUD(澳元)、JPY(日元)、CHF(瑞郎)、NZD(新西兰元) 外汇是以货币对形式交易，例如: 欧元/ 美元(EUR/USD) 或美元 / 日元 (USD/JPY) 。
对于新手而言，要理解一个外汇交易报价似乎很困难，其实只要掌握两个基本点，判读报价就会变得十分方便。 1) 前面的货币是基础货币。 2) 基础货币的价值总是以 1 为单位。例：美元 / 日元 120.01 ，在这组报价中，美元即为基础货币。美元 / 日元 120.01 ，意味着 1 美元等于120.01 日元。无论买 / 卖，都是在交易基础货币。 “点”的概念 (PIP点); 国际外汇市场上，汇率的价格共有 5 位数字，汇率价格的最后一数，称之为一点，如美金兑日圆为 114.51 中的0.01 、欧元兑美金为1.2801 中的0.0001，都称作为一点，这是汇率变动的最小基本单位。是衡量一个特定货币对的交换利率改变时的最小数，它常指交换利率的最后一个数(大多数情况下是小数点后第四位数)。 在外汇交易中，您会看到一个两边的报价，由买价与卖价组成。买价与卖价的差别为点差，交易商通过买卖的点差获利。 外汇市场，24小时的全球市场
对于汇市投资者来说，最好的机会总是交易那些交易量最大的货币，即“主要货币”。今天， 85% 的外汇交易是主要货币，包括美元，日元，欧元，英镑，瑞士法郎，加拿大元和澳大利亚元。巨大的交易量，使得任何一个机构都没有能力操纵这一市场，价格的走动有规律可循，对普通的投资者比较公平。与巨大的交易量相比，外汇市场区别于其他金融市场的另一个显著特点是，这是一个 24 小时永不停滞的全球市场，市场交易每天从悉尼开始，随着地球的转动，全球每个金融中心的营业日将依次开始。 24小时的交易市场使得外汇交易者可以根据自己的生活习惯安排交易时间，以及对每一时段发生的经济，社会和政治事件所导致的外汇波动做出反应，从而获利。 外汇市场是一个全球化的金融市场, 从东半球开始, 再到美国纽约, 然后到洛杉矶结束。 区域北京时间纽约时间(美东时间) 格林威治时间GMT 澳洲开市凌晨 4:00 下午 4:00 晚上 9:00
何为外汇 [外汇]原指货币币兑换率（EXCHANGERATE）。简单来说，是一个国家的货币兑换别国的货币称为外汇；即国家与国家之间，国贸易、投资、旅游等经济往来，引起货币间支付的关系。由于各国货币不同，在国外支付时，必须先将本国货币兑换成外国货币，或是收到外国的外币，换成本国货币才得以在国内流通，从而产生了货币兑换的关系。 而外汇市场是一个先进的电讯网路，不受时空限制，透过电子通讯设备进行买卖。汇市是一个庞大的国际化的交易市场，外汇价格会国市场对不同货币的供求而变化，不易受人为操纵，买卖时间差不多长达24小时。 投资外汇的八大优点 （一）投资目标是国家经济，而不是上市公司业绩 （二）外汇是双边买卖，可买升可买跌，可避免其中之规限 （三）保证金交易，投资成本轻 （四）成交量大，不容易为大户所操控 （五） T+0交易 （六）能够掌握亏损的幅度（设定止损），不会因为没有买家或卖家承接而招致更大的损失。 （七）二十四小时交易，买卖可随时进行 （八）利息回报率高（股票每年最多只派发四次，而外汇则是若投资者持有高息货币合约者，每天均可享有利息各种投资渠道比较
外汇市场的组成分子 A．中央银行 负责发行本国货币，制货币供给额，持有及调度外汇储备，维持本国货币之对内及对外的价值，在浮动汇率制度下，中央银行在外汇市场上，经常被迫买进或卖出外汇来干预外汇市场，以维持市场秩序。譬如：美国、日本、德国、英国、法国、加拿大、与意大利所组成的七大工业组织（G7），经常举行高峰会议，对于主要货币之汇率设有协议，限定汇率波动之幅度。由于G7经常联合干预，使汇价稳定；央行有时也会为了调节货币标准，或政策上的需要，在公开市场上进行干预，干预行动基本上是和市场大众持不同的立场，通常没有特殊的因素，中央银行是不会主动出面干预的。通常央行干预汇市只能收到暂时的效果，使汇率变化速度不致上升或下跌太快，但却无法改变长期的基本走势。 B．商业银行 在任何一个地方，不管该地是否是一个外汇兑换的主要市场，一般的小量现钞买卖，支票兑现都差不多全由银行垄断，银行外汇部门的主要业务就是将商业交易与财务交易的客户资产与负债从一种货币转换为另一种货币，这种转换可以即期交易（SPOT），或远期交易（FORWARD）方式办理，由于从事外汇交易的银行为数众多，所以外汇买卖日渐普及。 C．外汇经纪商 外汇与股票市场一样，任何活跃的市场都有不少的经纪商，在美国称为（Exchange Dealer）的角色，仅以收取佣金为目的，为客户代洽外汇买卖的汇兑商定，在买主与卖主之间，拉拢搓合，透过外汇经纪人的接洽，直接或间接买卖。外汇经纪商及经纪人，本身并不承担外汇交易的盈亏风险，其从事中介工作的代价为佣金收入（Broker Fee Or Commission），外汇经纪人因熟悉市场外汇供需情形、消息及图表的分析，以及汇率变化涨跌及买卖程序，故投资人乐于采用。 D．基金 此类机构性质上基本与经纪商大同小异，所不同的是它经常自行买卖，亦可随本身的意愿，对客户的交易作选择性的盈亏风险承担，而银行及经纪商亦经常是它的交易对象。 E．外汇供需者 由于贸易的往来，进出口商在商品输出或输入后货款的结算，以及运输、保险、旅行、留学、国外公债、证券、基金的买卖、利息的支付等而产生的外汇供给者与需求者。 F．外汇投资者 所谓外汇投资者，为预测汇率的涨跌，以现汇（SPOT）、远汇（FORWARD）或者期货外汇（FUTUERS）的交易途径，以少数的保证金从事大额外汇买卖交易，行情看涨时，先买入，后卖出，看跌时，先卖出后补回冲销，用极小的波动赚取中间的差价，获取厚利，所以外汇投资者也经常是主要外汇的供给及需求者。 外汇及外汇交易 外汇市场，也称为“Forex”或“FX”市场，是全球最大的金融市场，日交易量1.9兆美元，相当于美国证券市场的30倍，中国股票市场日交易量的600倍。 “外汇交易”是买入一种货币，同时卖出另外一种货币。