3DIC Integration with TSV –Current Progress and Future Outlook
Shan Gao, Dim-Lee Kwong
Institute of Microelectronics,
A*STAR (Agency for Science,
Technology and Research)
Singapore
9 September, 2010 https://www.doczj.com/doc/945967070.html,
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Overview
Introduction
3DIC integration and main application
Products to be commercialized
Technologies and key challenges for 3DIC with TSV Current progress in 3D TSV development
Outlook
Why 3DIC? -Pre-positioning Strategy
for More than Moore
ENABLER
Discrete 2-D Integration
High Density Memory
Low Power Logic
High Performance
Logic
High Speed Memory Radio
Photonics
Power Regulator
Sensors
Photonics
Sensors
I/O High Density
memory
High Speed
Memory High Perf.Logic Low Power Logic Power
Reg.
Radio 3-D Integration
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3D TSV Application Status
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3D TSV Market Drivers
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3D TSV Packaging Market Forecast
?Logic + memory application to drive >30% of the 3D TSV packaging
market by 2015
?CIS, MEMS, SENSOR to drive 30% of market share
?Memory + Memory stacking combined DRAM & NAND drive 20%
Substrate
?Mechanical simulation for low stress
?Thermal simulation for low chip temperature ?Electrical simulation for Signal Integrity (SI), Power Integrity (PI)
Modeling & Characterization
Micro-bumping
Wafer Level RDL
Wafer Thinning
TSV Fabrication
C2W/C2C Bonding
Cu-Cu Wafer Bonding ?Temporary bonding/debonding adhesive ?Plating chemicals for high AR (>10) TSV filling ?CMP slurries for high removal rate (5μm/min) ?Low curing temperature dielectric (< 180oC)Development of Materials
3D IC Structure
3D IC Technology Development in IME
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(TSV Interposer)
Via ‐First (TSV Interposer)(Logic, Memory)
Via ‐Middle
(Logic, Memory)(CIS, Memory)
Via ‐Last (B2T)
(CIS, Memory)TSV ETCH TSV Photo FEOL
TSV CLEAN TSV CVD TSV PVD TSV ECP TSV CMP
TSV ETCH TSV Photo TSV CLEAN TSV CVD TSV PVD TSV ECP TSV CMP
TSV ETCH BOND & THIN TSV LTCVD CONTACT ETCH TSV PHOTO TSV PVD TSV ECP DEBOND
BEOL
Si
RDL & BUMP TSV CLEAN BOND & THIN BS VIA REVEAL CHIP STACK FEOL BEOL
Si FEOL BEOL
Si 3D TSV Integration Process Flow
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Key challenges:
?Conformal dielectric step coverage and Barrier / Cu seed step coverage ?Void free electroplating, Cu Protrusion
On ‐going Research:
Description Established in IME Dielectric coverage
~10% for AR10Barrier metal and seed step coverage ~5% for AR10
Electro ‐plated via ?5um/AR10, 15um pitch Wafer / TSV thickness
50um
Via etching Barrier/Seed/Cu Filling Cu CMP
Dielectric Layer TSV Fabrication Process
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TSV Fabrication Process Challenges
?Cu protrusion (hundreds to thousands ?) may attack M1 and ILD layer ?Double CMP and Heat Treatment method have been reported for via ‐middle process –but these are typically high temperature processes ?Low temperature ILD process for Cu BEOL can minimize Cu protrusion for interposer application –process development needed
Process Challengess –Cu Protrusion
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?Need carrier wafer for chip bonding
?Lower density integration ?No need carrier wafer
?High density integration ?Work only between 1st and 2nd wafer bonding only, the 3rd wafer stack back to “Face to back”
Interconnection –Cu-Cu Wafer Bonding On‐going Research:
?Cu‐Cu W2W bonding: Temperature 300o C, Pitch 15um
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Key challenges :
?Low bonding temperature, Fine pitch and High reliability
Cu pillar + Thin solder layer
Micro ‐bump IMC based interconnection
Description Specification Bonding Temperature Micro ‐bump
180°C Cu pillar with lead free solder
260°C Bump material AuInSn, InSn Bump Pitch
25um
Si Chip
Si chip
On ‐going Research:
?Composite joint for C2C, C2W bonding, Bump Pitch: 15um
Interconnection -Fine Pitch Micro-Bump
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3M –Laser released adhesive
BSI –Thermal plastic adhesive
TMAT –Mechanically released adhesive
TOK ‐Chemical released adhesive
Thin Wafer Handling -Temporally
Bonding/Debonding
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Key challenges :
?Multiple chip stacking with low stand ‐off interconnection ?Low warpage wafer level encapsulation
On ‐going Research: ?C2W bonding : 10 chips
C2C & C2W Bonding
Wafer Level Underfilling Wafer Level Molding
Chuck
Base Wafer Base Wafer
Description
Specification
Bonding method (C2W, C2C)Thermo ‐compression Stand ‐off
Low Temperature Solder (180°C)5um Cu pillar with leadfree solder (260°C)
15um
Chip Stacking Process
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Substrate
Reliability Challenges
Stress concentration, Cracks around TSVs
IMC, fatigue failure of microbumps
Moisture induced
delamination, corrosion
Hot Spot in Chip & Thermal Management
Electromigration in Microbumps & TSVs
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110x []
00
1'
y []
10
1y []
010'x R 1
R 4
R 3R 2
Stress sensor for process
development
Comb & Triple Tracks Sensor for moisture ingress & corrosion
n-well
p substrate
N++P + implant n-well
N++P + implant
Thermal chip design Crack sensor chip design
Sensor Chip Design For Reliability
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Integrated single or two phase liquid cooling for high power chips in 3DIC
‐Chip carrier with fluidic and electrical paths by C2C bonding
‐3D electrical and fluidic interconnection using silicon interposer
Heat Exchanger
Mini Pump PCB
Silicon carrier
Fluidic adaptor TSV
Electrical I/O
Fluidic Inlet Micro Channels Seal ring
0.0
10.020.030.040.050.060.070.080.090.0100.0110.00
10
20
30
40
50
60
70
80
90
100
Chip Heat Dissipation (W/cm2)
A v g . C h i p T e m p e r a t u r e (°C )Chip with 400 Bumps ( Measured Data)Chip with 2500 Bumps ( Simulation Data)Avg Cooling Liquid Temp
Integrated Cooling Solution
On ‐going Research:
?Two Phase Boiling Cooling
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Identify & establishment –300mm line through consortium efforts
1st Year
Process & Characterization studies on 300mm wafer
2nd Year 3rd Year
Phase ‐1 (18 months)
Phase ‐2 (18 months)
Process & Reliability studies
Application: Mobile Devices
?One Logic Chip & Six Memory Chips Consortium Deliverables:
?Phase ‐1: Design Guidelines & Process Development ?Phase ‐2: Full Functional Device Demonstration
Design & Modeling Studies
Singapore 3D TSV Consortium
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3D Stacking (C2C, C2W, W2W)
Design, Simulation & Characterization
Wafer Level RDL & Micro-bumping
TSV Fabrication
Wafer Handling & Thinning
High freq. (up to 80GHz) TSV Electrical Characterization (Φ<2um, D<20um)
Thermo-Mechanical simulation
Dynamic two-phase flow simulation
Via Last Φ5um, D50um
Sub-micron Via Φ1um, D10um
Via Middle Φ2um, D20um
C2C/C2W bonding with solder (10 chips)
W2W Cu-Cu Bonding
(Pad size: 5um, pitch: 10um, Bonding temp.: <200?C)
12”50um thickness
12”20um thickness
12”10um thickness
8”50um thickness
CuInSn solder: 180?C, Size: 8um, Pitch: 15um
Line/Space: 10um/10um
Line/Space: 15um/15um
Sensor + Mixed Signal
PMIC + Memory + RFIC
Sensor + Memory + FPGA
IME 3DIC Development Roadmap
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