A Formal Semantics on Net Delay in Verilog-HDL
Hisashi Sasaki. Toshiba Corp., Semiconductor Company.
STE Building 1000-1, Kasama-cho, Sakae-ku, Yokohama 247-8585, Japan,
hisashi3.sasaki@toshiba.co.jp
Abstract
This paper presents a formal semantics for the wire data structure and behavior such as continuous assignment and inertial delay in Verilog-HDL. Its language-interoperability also clarifies the background why VHDL experts so frequently fall in the misinterpretation on the cancellation of scheduled events regarding on the wire concept in Verilog-HDL.
1. Introduction
There are many works on formal semantics for VHDL. Their primary purpose is to provide the theoretical framework to promote the understanding of the semantics. These works have been not recognized as practical tools yet. Recently a successful application of formal approach to define the analog and mixed-signal extension are known to validate the semantic consistency of the proposed standard even during its development process, and resulted in successful contribution to standardization activity [3,4,5]. Now the formal specification is becoming widely accepted in EDA community and strongly recognized as a new tool in defining languages, for example, SLDL regards it as a prerequisite technical item to be considered.
On the other hand, a few works are known for Verilog-HDL. The Berge’s book [1] gives the first comprehensive discussion to compare VHDL and Verilog-HDL. However, it is descriptive explanation not based on a formal method. Gordon’s appeal [6] is the first declaration that formal method is necessary for Verilog-HDL too. At that time, formal semantics is not explicitly established, and their work is still in progress at present. Most of today’s discussions [11,12] still remains based on non-formal method. Borrione’s work [7] is the first successful paper by formal approach. But their discussion is limited to synchronous design and their aim is to provide the synthesis semantics, not simulation one. Sasaki [8], Lasseter [10,14] and Li [13] independently developed formal simulation semantics by Abstract State Machine (ASM), operational semantics and Interval Temporal Logic (ITL) respectively. Lasseter’s and Li's works focused only on Verilog-HDL. Sasaki’s work provided the common foundation for VHDL and Verilog-HDL which admits the discussion on interoperability issues between the both. In this paper, we will enhance our semantic analysis for Verilog-HDL by adding the formal formulation on net delay mechanism.
This paper deeply enhances the discussion proposed by Stewart [9]. Our discussion not only provides the direct description of semantic behavior, but also reveals the background why VHDL experts fall in the misinterpretation mentioned in his paper.
2. Preliminary background
In the previous Sasaki’s work [8], the following item are focused to establish the clarification of delicate differences between the two languages.
(1) delay mechanism: There are not only the distinction
transport delay and inertial delay but also the delicate differences between the concept of transport delay in VHDL and modified transport delay and pure transport delay in Verilog-HDL.
(2) waveform: Only single element is admissible in
Verilog-HDL, but multiple-element is admissible in VHDL. The successive assignments of Verilog-HDL can generate the multiple waveform (equivalent counterpart supported by VHDL) effectively. (3) thread of control: It controls the flow of control to
suspend the user-defined process in VHDL and always block in Verilog-HDL, and triggers the simulation kernels. The blocking property of Verilog-HDL assignment is expressed by the semantic rule, in which the suspended flag is set to true to show the suspension, the timeout data is set by computing from the delay specification, and the activation flag of driver is set true if requested. On the other hand, non-blocking does not include such settings.
(4) overwrite property of signal driver: Verilog-HDL
does not remove the events scheduled by the previous assignment. VHDL removes all the events scheduled by the previous assignment.
In order to assure to establish the common foundation for the both languages, we intentionally ignored the delicate differences in the two simulation cycles.
(1) The stratification mechanism of Verilog-HDL is
ignored. The separated treatment of non-blocking assignments and blocking assignment is replaced by the formulation using the thread of control.
(2) non-deterministic behavior of Verilog-HDL
concurrent process. LRM explicitly requests the order preservation that the event must be scheduled in the simulation queue in accordance with the syntactic order when there are multiple assignments for the same target in the same always block (the same concurrent process).
(3) resolution: Verilog-HDL has two type of signals:
wire and register. Wires should be resolved by the signal resolution mechanism such as wired-or or wired-and. But registers should modify the driver by adding the new event. Therefor, the reuse of resolution mechanism for VHDL is applicable for wires, not for registers.(4) In the LRM for Verilog-HDL, there is no concept of
signal driver. However, the introduction of the concept is not harmful but useful. The flat (uniform) treatment of all events for signals could be organized as the driver just like as the concept VHDL has adopted.
By ignoring the above differences of the two simulation cycles, we can reuse both the semantic functions and the simulation cycle as the common foundations, which are already developed by ASM [2].
3. The problem: misunderstanding on net delay
The task to get accurate understanding on net delay is not easy from reading LRM in Verilog-HDL. For example, syntax does not always reflect the semantic classification of objects: the two delay3 options have different meanings in the following BNF rule (FIG.1): all other wire refers net delay data found in net declaration rather globally. When we generates a driver, we refers a delay data found in continuous assignment. Its reference is confined in that driver locally.
Although this fact could be read carefully from the chapter 6.1.3 LRM (FIG.2), the accurate understanding for the propagation of signal change seems not so easy.This descriptive explanation may cause the wrong interpretation about net delay. Let illustrate such semantic fault by using the following stimulus and net delay description [9] (FIG.3, FIG.4).
A wrong interpretation (FIG.5, FIG.6): At the current time Tc=30, the waveform r2=0 (called w1) is scheduled at Tc+30+10 = 70. Next, at the current time Tc=30+25=55, the waveform r1=0 (called w2) is scheduled at Tc+20+10 = 85. At the same time, the effect by r1 is directly propagated to w, the waveform w2
should overwrite the waveform w1. Therefore, the value of w is ‘0’ at the time 85, and is keeping its old value ‘1’until that time 85. That causes the cancellation of the event of r2 (the waveform w1).
This wrong interpretation suggests that we may believe that cancellation of all previous events by the new assignment removes the events more excessively than one must expect. The correct interpretation (FIG.7, FIG.8) is based on the resolution mechanism on wires. The waveform r2=0 is scheduled at the time 30+30=60, and the waveform r1=0 is schedule at the time 55+20=75.Next the waveform is resolved, and then the result is delayed by 10 cycles (net delay). Finally, w = ‘x’ at the time 60+10=70, w=”0” at the time 75+10=85.
This paper will extend my previous work [8] by augmenting the treatment for net delay mechanism for continuous assignment. The Stewart’s discussion [9] is the first proposal pointing out the insufficiency of the definition on the net delay. His solution was the introduction of the new function “combine2” (for example, see FIG.9) to explicitly describe the signal resolution.
The Stewart’s function “combine2” explains the
semantics via the syntactic rewriting of Verilog-HDL source code, and therefore it is indirect semantics. If we want to know what is the differences between the two descriptions (compare FIG.4 with FIG.10 and FIG.11) including the warning or error interpretation, the immediate answer is not found by the combine2. Anyway, it is disadvantage that he could not mention the semantics for a continuous assignment.4. Formal semantics for net delay
On the other hand, our approach will directly specify the semantic behavior by the ASM description. It is our advantage, for example, to explicitly reveal the relationship between the data specified by net delay declaration and events scheduling for signal driver. As the simulation model is common to the both languages, note that the concept of net delay is defined too in VHDL simultaneously (however, syntax is not proposed yet.). The target semantics is implemented by the equivalent always block in FIG.12.
This definition is similar to the definition for the concurrent signal assignment in VHDL, which reflects the nature of iterative (continuous) evaluation: whenever a signal changes, a new event is scheduled. In fact, this definition is not mentioned in the LRM. However, we will intentionally introduce such an artificial definition via the sequential counterpart for continuous assignment, which is called “sequential continuous assignment”. Its semantic rule is given as FIG.13.
The semantic functions and semantic objects are summarized as follows. These are almost originally formulated by [2], and a few of them are enhanced by [8].
- driver(P, S): the driver of signal S in process P. It is the sequence of
- active(d) : the flag to show whether the drive d is active or not. The simulation kernel to activate the computation process to set the driving value, the effective value and the current value refers it.
- SingleWaveform: the waveform to be newly appended to a driver. Its value part is computed from the evaluation of the expression Expr. Note that the renaming of this semantic object from "Waveform" (VHDL) to "SingleWaveform" (Verilog-HDL). This suggests that only single element is admissible as waveform in Verilog-HDL.
- d |> T : the relative future part of the driver d with respect to the time T. This is an enhanced semantic function in order to insert a SingleWaveform to driver.
- Time’ : the absolute time value summated from the specified assignment delay Time, the net delay netDelay(S) and the current simulation time Tc.
- tail (d) : the tail part of the driver d as a list.
- d |< T : the relative past part of the driver d with respect to the time T.
- first (d) : the first part of the driver d as a list.
- ^ : the concatenation operator to append waveforms. To implement a "transport delay" mechanism, it is sufficient (the reject function is not necessary.) - reject : the function to implement “inertial delay”mechanism by removing the small-width pulses such as glitch. The combination of waveform append, trimming of waveform by first, and the relative past part of the driver with this function reject will produce the final rejected waveform.
The net delay data is stored in the variable netDelay(S) whose value is set by the instance of net declaration and the data is possible to be shared globally by referring S in any other continuous assignment. This shows the explicit relation between the net declaration and the event scheduling in continuous assignment. To represent the event insertion, the two functions d | > T (future part) and d |< T (past part) are used. If the specified delay time is zero, then the drive is set “active” immediately. This is implemented by using the active flag active(driver(Process, S)). The simulation kernel provides the resolution mechanism with respect to the drivers.
We can develop a further semantic discussion. For instance, FIG.14 describes the semantic rule for VHDL transport delay. Using this rule, we can recognize precisely semantic difference between Verilog-HDL and VHDL. (1) It cancels the future part of waveform by replacing all the previous waveform by newly generated “Waveform” specified in that assignment. On the other hand, FIG.13 keeps the future part of the driver by appending it directly. (2) Here the transport delay mechanism is implemented as the concatenation of the value of driver at the time (Tc+Time1) and “Waveform”. FIG.13 uses the function "reject" which shows the inertial delay mechanism. (3) Additionally, we can also easily identify the differences from the two transport delay mechanisms of Verilog-HDL by [8]. The pure transport delay for continuos assignment copies the driver itself, not appending the waveform. The modified transport
delay for assignments (blocking/non-blocking) keeps the future parts. (4) There is no netDelay(S) part in the rule for registers. This shows the difference between nets and registers in Verilog-HDL. Thus, the precise semantic comparisons have achieved.
Finally, we should discuss the background why the misinterpretation mentioned by Stewart [9] was taken. (1) In Verilog-HDL, the cancellation of event should not be occurred for registers. On the contrary, in VHDL, an event may be cancelled by the future events scheduled by other signal assignment. At first study, we cannot determine which mechanism is chosen for wires. (2) As there is no concept for “sequential continuous assignment” in the LRM, the propagation of event is not well formulated. By these fact (1) and (2), the interaction between the propagation mechanism and the resolution mechanism is not well formulated by the descriptive explanation in the LRM.
In the meta-position of language understanding, by the above discussion, we have showed why such a misinterpretation is popular. A Verilog-HDL expert, who only has learned Verilog-HDL, cannot think about the cancellation of scheduled event. On the other hand, a VHDL expert, who only has learned VHDL, implicitly assumes the cancellation. When a VHDL expert tries to learn Verilog-HDL, as both languages seem to be very similar, the difference is not recognized. A Verilog-HDL expert may not give the immediate correction for VHDL expert's misinterpretation because the cancellation is out of reach of his think. Such a recognition gap was bridged by the interoperable property of our semantic model. 5. Summary
As a conclusion, a formal semantic analysis for Verilog-HDL and VHDL is enhanced on net delay mechanism in order to give the common simulation model especially focusing on signal scheduling mechanism. Based on this model, we have also clarified the background why the semantic misinterpretation is so popular for VHDL experts. Our semantics is expected to become a coherent first step for a future semantic interoperability analysis on multi-semantic-domain such as Verilog-AMS and VHDL-AMS.
References
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5. Semantics 5.1 What is semantics? Semantics can be simply defined as the study of meaning. This definition naturally leads to the question: what is meaning? Meaning is central to the study of communication, but the question of what meaning really is is difficult to answer. Even linguists do not agree among themselves as to what meaning is. And what makes the matter even more complicated is th at philosophers, psychologists, and sociologists all claim a deep interest in the study of meaning, although they differ in their focus of interest. The philosophers are interested in understanding the relations between linguistic expressions and what they refer to in the real world, and in evaluating the truth value of linguistic expressions. The psychologists focus their interest on understanding the workings of the human mind through language. This is why it is not surprising to find ten books all bearing the title "Semantics" but talking about different things. In our discussion, we will limit ourselves to the study of meaning from a linguistic point of view. 5.2 Some views concerning the study of meaning 5.2.1 The naming theory One of the oldest notions concerning meaning, and also the most primitive one, was the naming theory proposed by the ancient Greek scholar Plato. According to this theory, the linguistic forms or symbols, in other words, the words used in a language are simply labels of the objects they stand for. So words are just names or labels for things. The limitations of this theory are obvious. First of all, this theory seems applicable to nouns only, but verbs, adjectives, and adverbs such as "think", "hard", "slowly" are definitely not labels of objects. Besides, within the category of nouns, there are nouns which denote things that do not exist in the real world at all such as "ghost", "dragon", and "unicorn", and also nouns that do not refer to physical objects, but abstract notions such as "j o y", "im pulse ". 5.2.2 The conceptualist view A more sophisticated and seemingly more plausible view than naming is one that relates words and things through the mediation of concepts of the mind. This conceptualist view has been held by some philosophers and linguists from ancient times. This view holds that there is no direct link between a linguistic form and what it refers to (i.e. , between language and the real world); rather, in the interpretation of meaning they are linked through the mediation of concepts in the mind. This is best illustrated by the classic semantic triangle or triangle of significance suggested by Ogden and Richards: THOUGHT/REFERENCE SYMBOL/FORM-REFERENT (直线表示两者之间有直接联系，虚线表示两者之间无直接联系。) In the diagram, the SYMBOL or FORM refers to the linguistic elements (words,
1.Hyponymy________. A.is the relationship which obtains between specific and general lexical items, such that the former is included in the latter. B.is the relationship that stands between “flute” and “instrument”. C.Both A and B. D. None 2.We can call the relation between “animal” and “horse” as ______. A.Synonymy B. Polysemy C. Homonymy D. Hyponymy 3.The semantic features of the word “girl” can be expressed as _______. A.+ANIMATE, -HUMAN,+ADULT,+MALE. B.+ANIMATE, +UMAN,-ADULT,+MALE. C.+ANIMATE, -HUMAN,+ADULT,-MALE. D.+ANIMATE, -HUMAN,-ADULT,+MAL E. 4.What is the sentential relationship between “He likes skating.”and “ He likes sports.”? A.Presupposition. B.Entailment. C.Contradiction. D.Hyponymy. 5.According to the predication analysis proposed by the British linguist G. Leech, the predication of the sentence “It is raining.” is a ________. A.No-place predication.
Chapter 5 Semantics 语义学 一、定义 1. semantics语义学: Semantics can be simply defined as the study of meaning in language. 语义学可以简单地定义为对意义的将研究。 二、知识点 5.2 Different views of meaning意义研究的不同观点 5.2.1 The naming theory命名论(by希腊Scholar Plato) The naming theory命名论: Words are just names or labels for things. 词语只不过是其代表的事物的名字或标记。 Eg. desk—a piece of furniture with a flat top and four legs. The limitations of this theory局限性: 1. This theory seems applicable to nouns only.这一理论看起来仅适用于名词 (Some words are definitelynot lables of object: eg. jump, quickly, pretty, and, in, hearted, think, hard, slowly…) 2. There are nouns which denote things that do not exist in the real world: ghost, gragon, unicorn麒麟. 有些名词是指世界中根本就不存在的事物。 3. Nouns that do not refer to physical object, but abstract notions such as joy and impulse. 有些名词并不是指实物性的物体，而是指：joy, impulse刺激，这样的抽象概念。 5.2.2 The conceptualist [k?n'septj??l?st] view概念论（Ogden和Richards提出classic semantic triangle 经典语意三角） The conceptualist view: The conceptualist view: There is no direct link between language and the real world; rather, in the interpretation of meaning they are linked through the mediation of concepts in the mind..(语言和真实世界之间并没
7.1 Introduction 7.1.1 What is semantics? ?Semantics is one of the sub-branches of linguistics; it is generally defined as the study of meaning. 7.1.2 Sub-branches of semantics . John Lyons distinguishes between linguistic semantics and non-linguistic semantics , Wen Qiufang makes a distinction between l exical semantics and sentence semantics the latter of which is also termed sentential semantics by some people. 7.2 meaning 7.2.1 Uncertainty of meaning The words mean and meaning can be used in many different contexts and for different purposes in daily communication. Even as a technical term, meaning is defined and used differently according to different theoretical approaches. 7.2.2 theories of meaning John Lyons 1.The referential (or denotational theory) 指称说 2.the ideational, or mentalistic theory 意念说. 3.the behaviourist theory 行为反应说 4.the meaning-is-use theory 用法说 5.the verificationist theory验证说 6.the truth-conditional theory.真值说 Li Fuyuan Semantic triangular 语义三角理论 7.2.3 Basic concept related to meaning Reference所指is the relation between the linguistic expression and the object in extra-linguistic reality to which the expression refers. Denotation指称is a term which is intrinsically connected with reference Referent is the object or state of affairs in extra-linguistic reality or a linguistic element to which the speaker or writer is referring by using a linguistic sign. Limitations Sense意义the characteristic or quality of the object denoted by the linguistic expression. Denotes the relationship inside language.