LPC2119/LPC2129
Single-chip 16/32-bit microcontrollers; 128/256kB ISP/IAP
Flash with 10-bit ADC and CAN
Rev. 03 — 22 December 2004Product data 1.General description
The LPC2119/LPC2129are based on a16/32bit ARM7TDMI-S?CPU with real-time
emulation and embedded trace support, together with 128/256 kilobytes (kB) of
embedded high speed ?ash memory. A 128-bit wide memory interface and a unique
accelerator architecture enable 32-bit code execution at maximum clock rate. For
critical code size applications, the alternative 16-bit Thumb? Mode reduces code by
more than 30% with minimal performance penalty.
With their compact 64 pin package, low power consumption, various 32-bit timers,
4-channel10-bit ADC,2advanced CAN channels,PWM channels and46GPIO lines
with up to 9 external interrupt pins these microcontrollers are particularly suitable for
automotive and industrial control applications as well as medical systems and
fault-tolerant maintenance buses. With a wide range of additional serial
communications interfaces, they are also suited for communication gateways and
protocol converters as well as many other general-purpose applications.
2.Features
2.1Key features
s16/32-bit ARM7TDMI-S microcontroller in a tiny LQFP64 package.
s16kB on-chip Static RAM.
s128/256kB on-chip Flash Program Memory. 128-bit wide interface/accelerator
enables high speed 60MHz operation.
s In-System Programming (ISP) and In-Application Programming (IAP) via on-chip
boot-loader software. Flash programming takes 1 ms per 512 byte line. Single
sector or full chip erase takes 400ms.
s EmbeddedICE-RT interface enables breakpoints and watch points. Interrupt
service routines can continue to execute while the foreground task is debugged
with the on-chip RealMonitor? software.
s Embedded T race Macrocell enables non-intrusive high speed real-time tracing of
instruction execution.
s T wo interconnected CAN interfaces with advanced acceptance ?lters.
s Four channel 10-bit A/D converter with conversion time as low as 2.44μs.
s Multiple serial interfaces including two UARTs (16C550), Fast I2C (400 kbits/s)
and two SPIs
s60MHz maximum CPU clock available from programmable on-chip
Phase-Locked Loop with settling time of 100μs.
s Vectored Interrupt Controller with con?gurable priorities and vector addresses.
s T wo 32-bit timers (with four capture and four compare channels), PWM unit (six
outputs), Real Time Clock and Watchdog.
s Up to forty-six 5V tolerant general purpose I/O pins. Up to nine edge or level sensitive external interrupt pins available.
s On-chip crystal oscillator with an operating range of 1MHz to 30MHz.s T wo low power modes, Idle and Power-down.
s Processor wake-up from Power-down mode via external interrupt.
s Individual enable/disable of peripheral functions for power optimization.s Dual power supply:
x CPU operating voltage range of 1.65V to 1.95V (1.8V ±0.15V).
x I/O power supply range of 3.0V to 3.6V (3.3V ±10%) with 5V tolerant I/O pads.
3.Ordering information
3.1Ordering options
Table 1:
Ordering information
Type number
Package Name
Description
Version
LPC2119FBD64LQFP64plastic low pro?le quad ?at package;64leads;body 10×10×1.4mm
SOT314-2LPC2129FBD64
LQFP64
plastic low pro?le quad ?at package;64leads;body 10×10×1.4mm
SOT314-2Table 2:
Part options
Type number Flash memory RAM CAN Temperature range (°C)LPC2119FBD64128kB 16kB 2 channels ?40 to +85LPC2129FBD64
256kB
16kB
2 channels
?40 to +85
4.Block diagram
(1)When test/debug interface is used, GPIO/other function sharing these pins are not available.
Fig 1.Block diagram.
INTERNAL FLASH CONTROLLER
002aaa662
AHB BRIDGE
E M U L A T I O N T R A C E M O D U L E
TEST/DEBUG INTERFACE
AHB
DECODER
AHB TO VPB BRIDGE VPB DIVIDER
VECTORED INTERRUPT
CONTROLLER
SYSTEM FUNCTIONS
PLL
system clock
SCL*P0 (30 PINS)P1.31:16
Ain3:0*
SDA*
T R S T (1)
T M S (1)T C K (1)T D I (1)T D O (1)
R T C K
X T A L 2X T A L 1
R S T V 3V 1.8V S S SCK*MOSI*MISO*EINT0*EINT1*EINT2*EINT3*8 x CAP*8 x MAT*
PWM1..6*
RD2:1*TD2:1*
SSEL*TxD0,1*RxD0,1*
MODEM CONTROL
(6 PINS)*
SPI SERIAL INTERFACE 0 & 1
I 2C SERIAL INTERFACE
UART0/UART1
REAL TIME CLOCK
WATCHDOG TIMER
SYSTEM CONTROL
EXTERNAL INTERRUPTS
GENERAL PURPOSE I/O
CAN INTERFACE 0 & 1ACCEPTANCE FILTERS
CAPTURE/COMPARE TIMER0/TIMER1
PWM0
10-BIT
A/D CONVERTER AMBA AHB
(Advanced High-performance Bus)
128/256 kB FLASH
ARM7TDMI-S
INTERNAL SRAM CONTROLLER
16 kB SRAM
ARM7 LOCAL BUS
APB
*Shared with GPIO
5.Pinning information
5.1Pinning
Fig 2.Pinning.
handbook, full pagewidth
LPC2119/LPC2129
002aaa663
12
3
4
5
67
8
9
10
11
12
131415
16
4847464544434241403938373635343317
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
64636261605958575655545352515049P 1.27/T D 0
V 18A
X T A L 1
X T A L 2
P 1.28/T D I
V S S A
V S S A _P L L
R E S E T
P 1.29/T C K
P 0.20/M A T 1.3/S S E L 1/E I N T 3
P 0.19/M A T 1.2/M O S I 1/C A P 1.2
P 0.18/C A P 1.3/M I S O 1/M A T 1.3
P 1.30/T M S
V 3
V S S
V 18
V 18V S S P 0.0/T x D 0/P W M 1P 1.31/T R S T P 0.1/R x D 0/P W M 3/E I N T 0P 0.2/S C L /C A P 0.0V 3P 1.26/R T C K V S S P 0.3/S D A /M A T 0.0/E I N T 1P 0.4/S C K 0/C A P 0.1P 1.25/E X T I N 0P 0.5/M I S O 0/M A T 0.1P 0.6/M O S I 0/C A P 0.2P 0.7/S S E L 0/P W M 2/E I N T 2P 1.24/T R A C E C L K P0.21/PWM5/CAP1.3P0.22/CAP0.0/MAT0.0P0.23/RD2P1.19/TRACEPKT3P0.24/TD2V SS V 3A P1.18/TRACEPKT2P0.25/RD1TD1P0.27/AIN0/CAP0.1/MAT0.1P1.17/TRACEPKT1P0.28/AIN1/CAP0.2/MAT0.2P0.29/AIN2/CAP0.3/MAT0.3P0.30/AIN3/EINT3/CAP0.0P1.16/TRACEPKT0P1.20/TRACESYNC P0.17/CAP1.2/SCK1/MAT1.2P0.16/EINT0/MAT0.2/CAP0.2P0.15/RI1/EINT2P1.21/PIPESTAT0V 3V SS
P0.14/DCD1/EINT1P1.22/PIPESTAT1P0.13/DTR1/MAT1.1P0.12/DSR1/MAT1.0P0.11/CTS1/CAP1.1P1.23/PIPESTAT2P0.10/RTS1/CAP1.0P0.9/RxD1/PWM6/EINT3P0.8/TxD1/PWM4
5.2Pin description Table 3:Pin description
Symbol Pin Type Description
P0.0 to P0.3119, 21, 22,
26, 27,
29-31,33-35,
37-39, 41,
45-47,53-55,
1-3, 5, 9, 11,
13-15I/O Port 0: Port 0 is a 32-bit bi-directional I/O port with individual direction controls for each bit. The operation of port 0 pins depends upon the pin
function selected via the Pin Connect Block. Pins 26 and 31 of port 0 are not
available.
P0.019O TxD0 —Transmitter output for UART0.
O PWM1 —Pulse Width Modulator output 1.
P0.121I RxD0 —Receiver input for UART0.
O PWM3 —Pulse Width Modulator output 3.
I EINT0 —External interrupt 0 input
P0.222I/O SCL —I2C clock input/output. Open drain output (for I2C compliance).
I CAP0.0 —Capture input for Timer0, channel 0.
P0.326I/O SDA —I2C data input/output. Open drain output (for I2C compliance).
O MAT0.0 —Match output for Timer0, channel 0.
I EINT1 —External interrupt 1 input.
P0.427I/O SCK0 —Serial clock for SPI0. SPI? clock output from master or input to
slave.
I CAP0.1 —Capture input for Timer0, channel 1.
P0.529I/O MISO0 —Master In Slave OUT for SPI0. Data input to SPI master or data
output from SPI slave.
O MAT0.1 —Match output for Timer0, channel 1.
P0.630I/O MOSI0 —Master Out Slave In for SPI0.Data output from SPI master or data
input to SPI slave.
I CAP0.2 —Capture input for Timer0, channel 2.
P0.731I SSEL0 —Slave Select for SPI0. Selects the SPI interface as a slave.
O PWM2 —Pulse Width Modulator output 2.
I EINT2 —External interrupt 2 input.
P0.833O TxD1 —Transmitter output for UART1.
O PWM4 —Pulse Width Modulator output 4.
P0.934I RxD1 —Receiver input for UART1.
O PWM6 —Pulse Width Modulator output 6.
I EINT3 —External interrupt 3 input.
P0.1035O RTS1 —Request to Send output for UART1.
I CAP1.0 —Capture input for Timer1, channel 0.
Table 3:Pin description…continued
Symbol Pin Type Description
P0.1137I CTS1 —Clear to Send input for UART1.
I CAP1.1 —Capture input for Timer1, channel 1.
P0.1238I DSR1 —Data Set Ready input for UART1.
O MAT1.0 —Match output for Timer1, channel 0.
P0.1339O DTR1 —Data Terminal Ready output for UART1.
O MAT1.1 —Match output for Timer1, channel 1.
P0.1441I DCD1 —Data Carrier Detect input for UART1.
I EINT1 —External interrupt 1 input.
Note: LOW on this pin while RESET is LOW forces on-chip boot-loader to
take control of the part after reset.
P0.1545I RI1 —Ring Indicator input for UART1.
I EINT2 —External interrupt 2 input.
P0.1646I EINT0 —External interrupt 0 input.
O MAT0.2 —Match output for Timer0, channel 2.
I CAP0.2 —Capture input for Timer0, channel 2.
P0.1747I CAP1.2 —Capture input for Timer1, channel 2.
I/O SCK1 —Serial Clock for SPI1.SPI clock output from master or input to slave.
O MAT1.2 —Match output for Timer1, channel 2.
P0.1853I CAP1.3 —Capture input for Timer1, channel 3.
I/O MISO1 —Master In Slave Out for SPI1. Data input to SPI master or data
output from SPI slave.
O MAT1.3 —Match output for Timer1, channel 3.
P0.1954O MAT1.2 —Match output for Timer1, channel 2.
I/O MOSI1 —Master Out Slave In for SPI1.Data output from SPI master or data
input to SPI slave.
I CAP1.2 —Capture input for Timer1, channel 2.
P0.2055O MAT1.3 —Match output for Timer1, channel 3.
I SSEL1 —Slave Select for SPI1. Selects the SPI interface as a slave.
I EINT3 —External interrupt 3 input.
P0.211O PWM5 —Pulse Width Modulator output 5.
I CAP1.3 —Capture input for Timer1, channel 3.
P0.222I CAP0.0 —Capture input for Timer0, channel 0.
O MAT0.0 —Match output for Timer0, channel 0.
P0.233I RD2 —CAN2 receiver input.
P0.245O TD2 —CAN2 transmitter output.
P0.2539O RD1 —CAN1 receiver input.
P0.2711I AIN0 —A/D converter, input 0. This analog input is always connected to its
pin.
I CAP0.1 —Capture input for Timer0, channel 1.
O MAT0.1 —Match output for Timer0, channel 1.
P0.28
13
I AIN1 —A/D converter, input 1. This analog input is always connected to its pin.
I CAP0.2 —Capture input for Timer 0, channel 2.O
MAT0.2 —Match output for Timer 0, channel 2.
P0.2914I AIN2 —A/D converter, input 2. This analog input is always connected to its pin.
I CAP0.3 —Capture input for Timer 0, Channel 3.O
MAT0.3 —Match output for Timer 0, channel 3.
P0.3015I AIN3 —A/D converter, input 3. This analog input is always connected to its pin.
I EINT3 —External interrupt 3 input.
I
CAP0.0 —Capture input for Timer 0, channel 0.
P1.0 to P1.31
16, 12, 8, 4,48, 44, 40,36, 32, 28,24, 64, 60,56, 52, 20I/O
Port 1: Port 1 is a 32-bit bi-directional I/O port with individual direction controls for each bit. The operation of port 1 pins depends upon the pin function selected via the Pin Connect Block. Pins 0 through 15 of port 1 are not available.
P1.1616O TRACEPKT0 —Trace Packet, bit 0. Standard I/O port with internal pull-up.P1.1712O TRACEPKT1 —Trace Packet, bit 1. Standard I/O port with internal pull-up.P1.188O TRACEPKT2 —Trace Packet, bit 2. Standard I/O port with internal pull-up.P1.194O TRACEPKT3 —Trace Packet, bit 3. Standard I/O port with internal pull-up.P1.20
48
O
TRACESYNC —Trace Synchronization. Standard I/O port with internal pull-up.
Note: LOW on this pin while RESET is LOW, enables pins P1.25:16 to operate as Trace port after reset.
P1.2144O PIPESTAT0 —Pipeline Status, bit 0. Standard I/O port with internal pull-up.P1.2240O PIPESTAT1 —Pipeline Status, bit 1. Standard I/O port with internal pull-up.P1.2336O PIPESTAT2 —Pipeline Status, bit 2. Standard I/O port with internal pull-up.P1.2432O TRACECLK —Trace Clock. Standard I/O port with internal pull-up.P1.2528I EXTIN0 —External T rigger Input. Standard I/O with internal pull-up.P1.26
24
I/O
RTCK —Returned Test Clock output. Extra signal added to the JTAG port.Assists debugger synchronization when processor frequency varies.Bi-directional pin with internal pull-up.
Note: LOW on this pin while RESET is LOW, enables pins P1.31:26 to operate as Debug port after reset.
P1.2764O TDO —Test Data out for JTAG interface.P1.2860I TDI —Test Data in for JTAG interface.P1.2956I TCK —Test Clock for JTAG interface.P1.3052I TMS —Test Mode Select for JTAG interface.P1.3120I TRST —Test Reset for JT AG interface.TD110O TD1 —CAN1 transmitter output.
RESET
57
I
External Reset input:A LOW on this pin resets the device,causing I/O ports and peripherals to take on their default states, and processor execution to begin at address 0. TTL with hysteresis, 5V tolerant.
Table 3:Pin description …continued
Symbol Pin Type Description
XT AL162I Input to the oscillator circuit and internal clock generator circuits.XT AL261
O
Output from the oscillator ampli?er.V SS 6,18,25,42,50I Ground: 0V reference.
V SSA 59I Analog Ground: 0V reference. This should nominally be the same voltage as V SS , but should be isolated to minimize noise and error.
V SSA_PLL 58I PLL Analog Ground: 0V reference. This should nominally be the same voltage as V SS , but should be isolated to minimize noise and error.V 1817, 49I 1.8V Core Power Supply: This is the power supply voltage for internal circuitry.
V 18A
63
I
Analog 1.8V Core Power Supply: This is the power supply voltage for
internal circuitry.This should be nominally the same voltage as V 18but should be isolated to minimize noise and error.
V 323, 43, 51I 3.3V Pad Power Supply: This is the power supply voltage for the I/O ports.V 3A
7
I
Analog 3.3V Pad Power Supply:This should be nominally the same voltage as V 3 but should be isolated to minimize noise and error.
Table 3:Pin description …continued
Symbol Pin Type Description
6.Functional description
Details of the LPC2119/LPC2129 systems and peripheral functions are described in
the following sections.
6.1Architectural overview
The ARM7TDMI-S is a general purpose 32-bit microprocessor, which offers high
performance and very low power consumption. The ARM? architecture is based on
Reduced Instruction Set Computer (RISC) principles, and the instruction set and
related decode mechanism are much simpler than those of microprogrammed
Complex Instruction Set Computers. This simplicity results in a high instruction
throughput and impressive real-time interrupt response from a small and
cost-effective processor core.
Pipeline techniques are employed so that all parts of the processing and memory
systems can operate continuously. Typically, while one instruction is being executed,
its successor is being decoded, and a third instruction is being fetched from memory.
The ARM7TDMI-S processor also employs a unique architectural strategy known as
Thumb, which makes it ideally suited to high-volume applications with memory
restrictions, or applications where code density is an issue.
The key idea behind Thumb is that of a super-reduced instruction set.Essentially,the
ARM7TDMI-S processor has two instruction sets:
?The standard 32-bit ARM set.
?A 16-bit Thumb set.
The Thumb set’s 16-bit instruction length allows it to approach twice the density of
standard ARM code while retaining most of the ARM’s performance advantage over a
traditional 16-bit processor using 16-bit registers. This is possible because Thumb
code operates on the same 32-bit register set as ARM code.
Thumb code is able to provide up to65%of the code size of ARM,and160%of the
performance of an equivalent ARM processor connected to a 16-bit memory system.
6.2On-Chip Flash program memory
The LPC2119/LPC2129 incorporate a 128kB and 256kB Flash memory system
respectively. This memory may be used for both code and data storage.
Programming of the Flash memory may be accomplished in several ways. It may be
programmed In System via the serial port. The application program may also erase
and/or program the Flash while the application is running, allowing a great degree of
?exibility for data storage ?eld ?rmware upgrades, etc. When on-chip bootloader is
used, 120/248kB of Flash memory is available for user code.
The LPC2119/LPC2129 Flash memory provides a minimum of 100,000 erase/write
cycles and 20 years of data retention.
On-chip bootloader(as of revision1.60)provides Code Read Protection(CRP)for the
LPC2119/LPC2129 on-chip Flash memory. When the CRP is enabled, the JTAG
debug port and ISP commands accessing either the on-chip RAM or Flash memory
are disabled. However, the ISP Flash Erase command can be executed at any time (no matter whether the CRP is on or off). Removal of CRP is achieved by erasure of full on-chip user Flash. With the CRP off, full access to the chip via the JTAG and/or ISP is restored.
6.3On-Chip static RAM
On-Chip static RAM may be used for code and/or data storage. The SRAM may be accessed as 8-bits, 16-bits, and 32-bits. The LPC2119/LPC2129 provide 16kB of static RAM.
6.4Memory map
The LPC2119/LPC2129memory maps incorporate several distinct regions,as shown in the following ?gures.
In addition, the CPU interrupt vectors may be re-mapped to allow them to reside in either Flash memory(the default)or on-chip static RAM.This is described in Section
6.20 “System control”.
6.5Interrupt controller
The Vectored Interrupt Controller (VIC)accepts all of the interrupt request inputs and categorizes them as FIQ, vectored IRQ, and non-vectored IRQ as de?ned by
programmable settings.The programmable assignment scheme means that priorities of interrupts from the various peripherals can be dynamically assigned and adjusted.Fast Interrupt reQuest (FIQ) has the highest priority. If more than one request is assigned to FIQ, the VIC combines the requests to produce the FIQ signal to the ARM processor. The fastest possible FIQ latency is achieved when only one request is classi?ed as FIQ, because then the FIQ service routine can simply start dealing with that device. But if more than one request is assigned to the FIQ class, the FIQ service routine can read a word from the VIC that identi?es which FIQ source(s) is (are) requesting an interrupt.
Fig 3.LPC2119/LPC2129 memory map.
AHB PERIPHERALS
VPB PERIPHERALS
RESERVED ADDRESS SP ACE
BOOT BLOCK (RE-MAPPED FROM
ON-CHIP FLASH MEMORY
RESERVED ADDRESS SP ACE
16 KBYTE ON-CHIP ST A TIC RAM
RESERVED ADDRESS SP ACE
256 KBYTE ON-CHIP FLASH MEMORY (LPC2129)0xFFFF FFFF 0xF000 00000xEFFF FFFF 0xE000 00000xC000 0000
0xDFFF FFFF
0x8000 00000x7FFF FFFF 0x7FFF E0000x7FFF DFFF
0x4001 00000x4000 3FFF 0x4000 00000x3FFF FFFF
0x0004 00000x0003 FFFF
0x0002 00004.0 GB
3.75 GB
3.5 GB
3.0 GB
2.0 GB
1.0 GB
0.0 GB
128 KBYTE ON-CHIP FLASH MEMORY (LPC2119)
0x0001 FFFF 0x0000 0000
002aaa664
Vectored IRQs have the middle priority. Sixteen of the interrupt requests can be
assigned to this category.Any of the interrupt requests can be assigned to any of the 16vectored IRQ slots,among which slot0has the highest priority and slot15has the lowest.
Non-vectored IRQs have the lowest priority.
The VIC combines the requests from all the vectored and non-vectored IRQs to
produce the IRQ signal to the ARM processor. The IRQ service routine can start by reading a register from the VIC and jumping there. If any of the vectored IRQs are
requesting, the VIC provides the address of the highest-priority requesting IRQs
service routine,otherwise it provides the address of a default routine that is shared by all the non-vectored IRQs. The default routine can read another VIC register to see what IRQs are active.
6.5.1Interrupt sources
T able4lists the interrupt sources for each peripheral function.Each peripheral device has one interrupt line connected to the Vectored Interrupt Controller, but may have
several internal interrupt?ags.Individual interrupt?ags may also represent more than one interrupt source.
Table 4:Interrupt sources
Block Flag(s)VIC channel # WDT Watchdog Interrupt (WDINT)0
-Reserved for software interrupts only1
ARM Core Embedded ICE, DbgCommRx2
ARM Core Embedded ICE, DbgCommTx3
Timer0Match 0 - 3 (MR0, MR1, MR2, MR3)
4
Capture 0 - 3 (CR0, CR1, CR2, CR3)
5 Timer1Match 0 - 3 (MR0, MR1, MR2, MR3)
Capture 0 - 3 (CR0, CR1, CR2, CR3)
UART0Rx Line Status (RLS)
6
Transmit Holding Register empty (THRE)
Rx Data Available (RDA)
Character Time-out Indicator (CTI)
7 UART1Rx Line Status (RLS)
Transmit Holding Register empty (THRE)
Rx Data Available (RDA)
Character Time-out Indicator (CTI)
Modem Status Interrupt (MSI)
PWM0Match 0 - 6 (MR0, MR1, MR2, MR3, MR4, MR5, MR6)8
I2C SI (state change)9
SPI0SPIF, MODF10
SPI1SPIF, MODF11
PLL PLL Lock (PLOCK)12
RTC RTCCIF (Counter Increment), RTCALF (Alarm)13
Table 4:Interrupt sources…continued
Block Flag(s)VIC channel # System Control External Interrupt 0 (EINT0)14
External Interrupt 1 (EINT1)15
External Interrupt 2 (EINT2)16
External Interrupt 3 (EINT3)17 A/D A/D Converter18
CAN CAN1, CAN2 and Acceptance Filter19-23
6.6Pin connect block
The pin connect block allows selected pins of the microcontroller to have more than one function. Con?guration registers control the multiplexers to allow connection
between the pin and the on chip peripherals.Peripherals should be connected to the appropriate pins prior to being activated, and prior to any related interrupt(s) being enabled. Activity of any enabled peripheral function that is not mapped to a related pin should be considered unde?ned.
The Pin Control Module contains three registers as shown in Table5.
Table 5:
Address Name Description Access
0xE002C000PINSEL0Pin function select register 0Read/Write
0xE002C004PINSEL1Pin function select register 1Read/Write
0xE002C014PINSEL2Pin function select register 2Read/Write
6.7Pin function select register 0 (PINSEL0 - 0xE002C000)
The PINSEL0 register controls the functions of the pins as per the settings listed in T able6.The direction control bit in the IODIR register is effective only when the GPIO function is selected for a pin.For other functions,direction is controlled automatically.
Settings other than those shown in T able6 are reserved, and should not be used
Table 6:Pin function select register 0 (PINSEL0 - 0xE002C000)
PINSEL0Pin name Value Function Value after Reset
1:0P0.000GPIO Port 0.00
01TxD (UART0)
10PWM1
11Reserved
3:2P0.100GPIO Port 0.10
01RxD (UART0)
10PWM3
11EINT0
5:4P0.200GPIO Port 0.20
01SCL (I2C)
10Capture 0.0 (Timer0)
11Reserved
Table 6:Pin function select register 0 (PINSEL0 - 0xE002C000)…continued
PINSEL0Pin name Value Function Value after Reset 7:6P0.300GPIO Port 0.30
01SDA(I2C)
10Match 0.0 (Timer0)
11EINT1
9:8P0.400GPIO Port 0.40
01SCK (SPI0)
10Capture 0.1 (Timer0)
11Reserved
11:10P0.500GPIO Port 0.50
01MISO (SPI0)
10Match 0.1 (Timer0)
11Reserved
13:12P0.600GPIO Port 0.60
01MOSI (SPI0)
10Capture 0.2 (Timer0)
11Reserved
15:14P0.700GPIO Port 0.70
01SSEL (SPI0)
10PWM2
11EINT2
17:16P0.800GPIO Port 0.80
01TxD UART1
10PWM4
11Reserved
19:18P0.900GPIO Port 0.90
01RxD (UART1)
10PWM6
11EINT3
21:20P0.1000GPIO Port 0.100
01RTS (UART1)
10Capture 1.0 (Timer1)
11Reserved
23:22P0.1100GPIO Port 0.110
01CTS (UART1)
10Capture 1.1 (Timer1)
11Reserved
25:24P0.1200GPIO Port 0.120
01DSR (UART1)
10Match 1.0 (Timer1)
11Reserved
Table 6:Pin function select register 0 (PINSEL0 - 0xE002C000)…continued
PINSEL0Pin name Value Function Value after Reset
27:26P0.1300GPIO Port 0.130
01DTR (UART1)
10Match 1.1 (Timer1)
11Reserved
29:28P0.1400GPIO Port 0.140
01DCD (UART1)
10EINT1
11Reserved
31:30P0.1500GPIO Port 0.150
01RI (UART1)
10EINT2
11Reserved
6.8Pin function select register 1 (PINSEL1 - 0xE002C004)
The PINSEL1 register controls the functions of the pins as per the settings listed in T able7.The direction control bit in the IODIR register is effective only when the GPIO function is selected for a pin. For other functions direction is controlled automatically.
Settings other than those shown in the table are reserved, and should not be used.
Table 7:Pin function select register 1 (PINSEL1 - 0xE002C004)
PINSEL1Pin Name Value Function Value after
Reset 1:0P0.1600GPIO Port 0.160
01EINT0
10Match 0.2 (Timer0)
11Capture 0.2 (Timer0)
3:2P0.1700GPIO Port 0.170
01Capture 1.2 (Timer1)
10SCK (SPI1)
11Match 1.2 (Timer1)
5:4P0.1800GPIO Port 0.180
01Capture 1.3 (Timer1)
10MISO (SPI1)
11Match 1.3 (Timer1)
7:6P0.1900GPIO Port 0.190
01Match 1.2 (Timer1)
10MOSI (SPI1)
11Capture 1.2 (Timer1)
9:8P0.2000GPIO Port 0.200
01Match 1.3 (Timer1)
10SSEL (SPI1)
11EINT3
Table 7:Pin function select register 1 (PINSEL1 - 0xE002C004)…continued PINSEL1Pin Name Value Function Value after
Reset 11:10P0.2100GPIO Port 0.210
01PWM5
10Reserved
11Capture 1.3 (Timer1)
13:12P0.2200GPIO Port 0.220
01Reserved
10Capture 0.0 (Timer0)
11Match 0.0 (Timer0)
15:14P0.2300GPIO Port 0.230
01RD2 (CAN controller 2)
10Reserved
11Reserved
17:16P0.2400GPIO Port 0.240
01TD2 (CAN controller 2)
10Reserved
11Reserved
19:18P0.2500GPIO Port 0.250
01RD1 (CAN controller 1)
10Reserved
11Reserved
21:20P0.2600Reserved0
01Reserved
10Reserved
11Reserved
23:22P0.2700GPIO Port 0.271
01AIN0 (A/D input 0)
10Capture 0.1 (Timer0)
11Match 0.1 (Timer0)
25:24P0.2800GPIO Port 0.281
01AIN1 (A/D input 1)
10Capture 0.2 (Timer0)
11Match 0.2 (Timer0)
27:26P0.2900GPIO Port 0.291
01AIN2 (A/D input 2)
10Capture 0.3 (Timer0)
11Match 0.3 (Timer0)
29:28P0.3000GPIO Port 0.301
01AIN3 (A/D input 0)
10EINT3
11Capture 0.0 (Timer0)
6.9Pin function select register 2 (PINSEL2 - 0xE002C014)
The PINSEL2 register controls the functions of the pins as per the settings listed in T able 8.The direction control bit in the IODIR register is effective only when the GPIO function is selected for a pin. For other functions direction is controlled automatically.Settings other than those shown in the table are reserved, and should not be used.
6.10General purpose parallel I/O
Device pins that are not connected to a speci?c peripheral function are controlled by the GPIO registers. Pins may be dynamically con?gured as inputs or outputs.
Separate registers allow setting or clearing any number of outputs simultaneously.The value of the output register may be read back, as well as the current state of the port pins.
6.10.1
Features
?Direction control of individual bits.
?Separate control of output set and clear.?All I/O default to inputs after reset.
6.1110-bit A/D converter
The LPC2119/LPC2129 each contain single 10-bit successive approximation analog to digital converter with four multiplexed channels.
6.11.1
Features
?Measurement range of 0V to 3V .
?Capable of performing more than 400,000 10-bit samples per second.?Burst conversion mode for single or multiple inputs.
?
Optional conversion on transition on input pin or Timer Match signal.
31:30
P0.31
00Reserved 0
01Reserved 10Reserved 1
1
Reserved
Table 7:Pin function select register 1 (PINSEL1 - 0xE002C004)…continued PINSEL1Pin Name Value Function Value after Reset Table 8:Pin function select register 2 (PINSEL2 - 0xE002C014)
PINSEL2 bits
Description Reset value 1:0Reserved
-2When 0, pins P1.31:26 are GPIO pins. When 1,P1.31:26 are used as Debug port.
3When 0,pins P1.25:16are used as GPIO pins.When 1, P1.25:16 are used as T race port.031:431:30
Reserved
-
6.12CAN controllers and acceptance ?lter
The LPC2119/LPC2129 each contain two CAN controllers. The Controller Area network
(CAN) is a serial communications protocol which efficiently supports distributed real-time
control with a very high level of security. Its domain of application ranges from high speed
networks to low cost multiplex wiring.
6.12.1Features
?Data rates up to 1Mbit/s on each bus.
?32-bit register and RAM access.
?Compatible with CAN speci?cation 2.0B, ISO 11898-1.
?Global Acceptance Filter recognizes11and29-bit Rx identi?ers for all CAN buses.
?Acceptance Filter can provide FullCAN-style automatic reception for selected
Standard identi?ers.
6.13UARTs
The LPC2119/LPC2129each contain two UARTs.One UART provides a full modem control handshake interface, the other provides only transmit and receive data lines.
6.13.1Features
?16byte Receive and T ransmit FIFOs.
?Register locations conform to ‘550 industry standard.
?Receiver FIFO trigger points at 1, 4, 8, and 14bytes
?Built-in baud rate generator.
?Standard modem interface signals included on UART1.
6.14I2C serial I/O controller
I2C is a bi-directional bus for inter-IC control using only two wires: a serial clock line
(SCL), and a serial data line (SDA). Each device is recognized by a unique address
and can operate as either a receiver-only device (e.g. an LCD driver or a transmitter
with the capability to both receive and send information (such as memory).
T ransmitters and/or receivers can operate in either master or slave mode,depending on whether the chip has to initiate a data transfer or is only addressed. I2C is a
multi-master bus, it can be controlled by more than one bus master connected to it.
I2C implemented in LPC2119/LPC2129 supports bit rate up to 400kbit/s (Fast I2C).
6.14.1Features
?Standard I2C compliant bus interface.
?Easy to con?gure as Master, Slave, or Master/Slave.
?Programmable clocks allow versatile rate control.
?Bidirectional data transfer between masters and slaves.
?Multi-master bus (no central master).
?Arbitration between simultaneously transmitting masters without corruption of
serial data on the bus.
?Serial clock synchronization allows devices with different bit rates to communicate
via one serial bus.
?Serial clock synchronization can be used as a handshake mechanism to suspend
and resume serial transfer.
?The I2C bus may be used for test and diagnostic purposes.
6.15SPI serial I/O controller
The LPC2119/LPC2129 each contain two SPIs. The SPI is a full duplex serial
interface, designed to be able to handle multiple masters and slaves connected to a
given bus.Only a single master and a single slave can communicate on the interface during a given data transfer.During a data transfer the master always sends a byte of data to the slave, and the slave always sends a byte of data to the master.
6.15.1Features
?Compliant with Serial Peripheral Interface (SPI) speci?cation.
?Synchronous, Serial, Full Duplex, Communication.
?Combined SPI master and slave.
?Maximum data bit rate of one eighth of the input clock rate.
6.16General purpose timers
The Timer is designed to count cycles of the peripheral clock (PCLK) and optionally
generate interrupts or perform other actions at speci?ed timer values, based on four
match registers. It also includes four capture inputs to trap the timer value when an
input signal transitions, optionally generating an interrupt. Multiple pins can be
selected to perform a single capture or match function, providing an application with
‘or’ and ‘and’, as well as ‘broadcast’ functions among them.
6.16.1Features
?A 32-bit Timer/Counter with a programmable 32-bit Prescaler.
?Four 32-bit capture channels per timer that can take a snapshot of the timer value
when an input signal transitions. A capture event may also optionally generate an
interrupt.
?Four 32-bit match registers that allow:
–Continuous operation with optional interrupt generation on match.
–Stop timer on match with optional interrupt generation.
–Reset timer on match with optional interrupt generation.
?Four external outputs per timer corresponding to match registers,with the following
capabilities:
–Set LOW on match.
–Set HIGH on match.
–T oggle on match.
–Do nothing on match.
6.17Watchdog timer
The purpose of the Watchdog is to reset the microcontroller within a reasonable
amount of time if it enters an erroneous state. When enabled, the Watchdog will
generate a system reset if the user program fails to ‘feed’ (or reload) the Watchdog
within a predetermined amount of time.
6.1
7.1Features
?Internally resets chip if not periodically reloaded.
?Debug mode.
?Enabled by software but requires a hardware reset or a Watchdog reset/interrupt to
be disabled.
?Incorrect/Incomplete feed sequence causes reset/interrupt if enabled.
?Flag to indicate Watchdog reset.
?Programmable 32-bit timer with internal pre-scaler.
?Selectable time period from (t pclk×256×4) to (t pclk×232×4) in multiples of
t pclk×4.
6.18Real time clock
The Real Time Clock(RTC)is designed to provide a set of counters to measure time when normal or idle operating mode is selected.The RTC has been designed to use little power, making it suitable for battery powered systems where the CPU is not
running continuously (Idle mode).
6.18.1Features
?Measures the passage of time to maintain a calendar and clock.
?Ultra Low Power design to support battery powered systems.
?Provides Seconds, Minutes, Hours, Day of Month, Month, Y ear, Day of Week, and
Day of Y ear.
?Programmable Reference Clock Divider allows adjustment of the RTC to match
various crystal frequencies.
6.19Pulse width modulator
The PWM is based on the standard Timer block and inherits all of its features,although only the PWM function is pinned out on the LPC2119/LPC2129.The Timer is designed to count cycles of the peripheral clock (PCLK) and optionally generate interrupts or
perform other actions when speci?ed timer values occur, based on seven match
registers. The PWM function is also based on match register events.