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12/8/04
IRLR7807ZPbF IRLU7807ZPbF
HEXFET ?
Power MOSFET
Notes through are on page 11
Applications
Benefits
l
Very Low RDS(on) at 4.5V V GS l Ultra-Low Gate Impedance
l Fully Characterized Avalanche Voltage and Current
l High Frequency Synchronous Buck
Converters for Computer Processor Power l
Lead-Free D-Pak IRLR7807Z I-Pak IRLU7807Z
PD - 95777A
IRLR/U7807ZPbF
Static @ T = 25°C (unless otherwise specified)
DD = 15V GS = 0V e
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Fig 4. Normalized On-Resistance
vs. Temperature
Fig 2. Typical Output Characteristics
Fig 1. Typical Output Characteristics Fig 3. Typical Transfer Characteristics
0.1
1
10
V DS , Drain-to-Source Voltage (V)
0.1
1
10
100
1000
I D , D r a i n -t o -S o u r c e C u r r e n t (A )
GS -60-40-20
20406080100120140160180
T J , Junction Temperature (°C)
0.5
1.0
1.5
2.0
R D S
(o n ) , D r a i n -t o -S o u r c e O n R e s i s t a n c e (N o r m a l i z e d )
V DS , Drain-to-Source Voltage (V)I , D r a i n -t o -S o u r c e C u r r e n t (A )
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Fig 8. Maximum Safe Operating Area
Fig 6. Typical Gate Charge vs.
Gate-to-Source Voltage
Fig 5. Typical Capacitance vs.
Drain-to-Source Voltage Fig 7. Typical Source-Drain Diode
Forward Voltage
1
10
100
V DS , Drain-to-Source Voltage (V)10
100
1000
10000
C , C a p a c i t a n c e (p F )
0481216
Q G Total Gate Charge (nC)
246810
12V G S , G a t e -t o -S o u r c e V o l t a g e (V )
0.0
0.5
1.0
1.5
2.0
V SD , Source-toDrain Voltage (V)
0.1
1.0
10.0
100.0
1000.0I S D , R e v e r s e D r a i n C u r r e n t (A )
0.1
1.0
10.0
100.01000.0
V DS , Drain-toSource Voltage (V)
0.1
1
10100
1000
I D , D r a i n -t o -S o u r c e C u r r e n t (A
)
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Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
Fig 9. Maximum Drain Current vs.
Case Temperature
Fig 10. Threshold Voltage vs. Temperature
25
50
75
100
125
150
175
T C , Case Temperature (°C)
010
20
30
40
50
I D , D r a i n C u r r e n t (A )
-75-50-25
25
50
75
100125150175
T J , Temperature ( °C )
1.0
1.5
2.0
2.5
V G S (t h ) G a t e t h r e s h o l d V o l t a g e (V )
t 1 , Rectangular Pulse Duration (sec)
T h e r m a l R e s p o n s e ( Z )
IRLR/U7807ZPbF
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DS
Current Sampling Resistors
Fig 13. Gate Charge Test Circuit
Fig 12b. Unclamped Inductive Waveforms
Fig 12a. Unclamped Inductive Test Circuit
I AS
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
V DD
25
50
75
100
125
150
175
Starting T J , Junction Temperature (°C)
020
40
60
80
100
120
E A S , S i n g l
e P u l s e A v a l a n c h e E n e r g y (m J
)
Fig 14a. Switching Time Test Circuit
Fig 14b.
Switching Time Waveforms
V V DS
90%
10%
d(on)
d(off)
r
f
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Fig 15. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET ? Power MOSFETs
* V GS = 5V for Logic Level Devices
Fig 16. Gate Charge Waveform
Id
Qgs1Qgs2Qgd Qgodr
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Control FET
Special attention has been given to the power losses in the switching elements of the circuit - Q1 and Q2.Power losses in the high side switch Q1, also called the Control FET, are impacted by the R ds(on) of the MOSFET, but these conduction losses are only about one half of the total losses.
Power losses in the control switch Q1 are given by;
P loss = P conduction + P switching + P drive + P output
This can be expanded and approximated by;
P loss =I rms 2
×R ds(on )()
+I ×Q gd
i g ×V in ×
f ? ? ? ? ? ? +I ×Q gs 2
i g ×V in ×f ? ? ? ? ?
?
+Q g ×V g ×f () +
Q oss
2×V in ×f ? ? ? ?
This simplified loss equation includes the terms Q gs2
and Q oss which are new to Power MOSFET data sheets.Q gs2 is a sub element of traditional gate-source charge that is included in all MOSFET data sheets.The importance of splitting this gate-source charge into two sub elements, Q gs1 and Q gs2, can be seen from Fig 16.
Q gs2 indicates the charge that must be supplied by the gate driver between the time that the threshold voltage has been reached and the time the drain cur-rent rises to I dmax at which time the drain voltage be-gins to change. Minimizing Q gs2 is a critical factor in reducing switching losses in Q1.
Q oss is the charge that must be supplied to the out-put capacitance of the MOSFET during every switch-ing cycle. Figure A shows how Q oss is formed by the parallel combination of the voltage dependant (non-linear) capacitance s C ds and C dg when multiplied by the power supply input buss voltage.
Synchronous FET
The power loss equation for Q2 is approximated by;
P loss =P conduction +P drive +P output
*
P loss =I rms 2
×R ds(on)
(
)
+Q g ×V g ×f ()
+Q oss 2×V in ×f ? ? ? ? ?
+Q rr ×V in ×f ()*dissipated primarily in Q1.
For the synchronous MOSFET Q2, R ds(on) is an im-portant characteristic; however, once again the im-portance of gate charge must not be overlooked since it impacts three critical areas. Under light load the MOSFET must still be turned on and off by the con-trol IC so the gate drive losses become much more significant. Secondly, the output charge Q oss and re-verse recovery charge Q rr both generate losses that are transfered to Q1 and increase the dissipation in that device. Thirdly, gate charge will impact the MOSFETs’ susceptibility to Cdv/dt turn on.
The drain of Q2 is connected to the switching node of the converter and therefore sees transitions be-tween ground and V in . As Q1 turns on and off there is a rate of change of drain voltage dV/dt which is ca-pacitively coupled to the gate of Q2 and can induce a voltage spike on the gate that is sufficient to turn the MOSFET on, resulting in shoot-through current .The ratio of Q gd /Q gs1 must be minimized to reduce the potential for Cdv/dt turn on.
Power MOSFET Selection for Non-Isolated DC/DC Converters
Figure A: Q oss
Characteristic
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