D IFFERENTIAL LVPECL F REQUENCY S YNTHESIZER
G ENERAL D ESCRIPTION
The ICS84330-03 is a general purpose, dual output high frequency synthesizer and a mem-ber of the HiPerClockS? family of High Perfor-mance Clock Solutions from ICS. The VCO operates at a frequency range of 250MHz to
700MHz. The VCO and output frequency can be pro-grammed using the I 2C interface. The output can be config-ured to divide the VCO frequency by 1, 2, 3, 4, and 6.
Additionally, the device supports spread spectrum clock-ing (SSC) for minimizing Electromagnetic Interference (EMI). The low cycle-cycle jitter and broad frequency range of the ICS84330-03 make it an ideal clock gen-erator for a variety of demanding applications which require high performance.
F EATURES
?Fully integrated PLL, no external loop filter requirements ?Two differential 3.3V LVPECL output
?Crystal oscillator interface: 10MHz to 25MHz ?Output frequency range: 41.67MHz to 700MHz ?VCO range: 250MHz to 700MHz
?Parallel or I 2C interface for programming M and N dividers during power-up
?
Supports Spread Spectrum Clocking (SSC)
Center spread: selectable ±0.5%, ±1.0%, ±1.5%, ±2%Up/Down spread: selectable 0.5%, 1.0%, 1.5%, 2%,2.5%, 3%, 3.5%, 4%
?RMS Period jitter: 9ps (maximum)?Cycle-to-cycle jitter: 40ps (maximum)?3.3V supply voltage
?0°C to 70°C ambient operating temperature
?Industrial temperature information available upon request ?
Available in both standard and lead-free RoHS-compliant packages
P IN A SSIGNMENT
B LOCK D IAGRAM
XT XT ICS84330-03
32-Lead LQFP Y package
7mm x 7mm x 1.4mm
body package Top View
32 31 30 29 28 27 26 25
9 10 11 12 13 14 15 1612345678
24
232221201918
17
VCO_SEL N1N0M8M7M6M5M4
SCL SDA
ADDR_SEL
V CCA V CCA
XTAL_SEL XT AL_IN
nc
M3
M2
M1
M0
nP_LOAD
OE
XT AL_OUT
V EE
V CC
nQ1
Q1
V EE
nQ0
Q0
V CC
XT
D IFFERENTIAL LVPECL F REQUENCY S YNTHESIZER
The ICS84330-03 uses either a parallel interface or indus-try standard I 2C interface to control the programming of the internal dividers. The power on defaults are summarized as follows:
Data Byte 2
I 2C A DDRESSING
The ICS84330-03 can be set to decode one of two addresses to minimize the chance of address conflict on the I 2C bus. The
t l u a f e D 0=)3n i p (L E S _R D D A 7t i B 6t i B 5t i B 4t i B 3t i B 2t i B 1t i B 0t i B 110110
0W
/R 1=)3n i p (L E S _R D D A 7t i
B 6t i B 5t i B 4t i B 3t i B 2t i B 1
t i B 0t i B 11
0111
0W
/R M Output
Parallel Mode:
256
Q0/nQ0 output at 267MHz (using a 16.667MHz crystal)Q1/nQ1 output at 133MHz (using a 16.667MHz crystal)
SSC Mode:
Off
The programming mode is controlled by the nP_LOAD pin.When this pin is low, The M, N values are set by the logic values on the M, N pins. If nP_LOAD is HIGH, the M, N dividers can be changed using the I 2C serial programming interface.
The I 2C control registers are defined below:
Data Byte 0
address that is decoded is controlled by the setting of the
ADDR_SEL pin (pin 3).
t
i B l o r t n o C 1N 0N 8M 7M 6M 5M 4M 3M e
u l a V t l u a f e D p u -r e w o P 0
1
t
i B l o r t n o C 2M 1M 0M t o N d e s U t o N d e s U t o N d e s U t o N d e s U t o N d e s U e
u l a V t l u a f e D p u -r e w o P 0
X
X
X
X
X
Data Byte 1
t
i B l o r t n o C p U n w o D 5C S S 4C S S 3C S S 2C S S 1C S S 0C S S e
u l a V t l u a f e D p u -r e w o P 0
D IFFERENTIAL LVPECL F REQUENCY S YNTHESIZER
START (ST) – defined as high-to-low transition on SDA while holding SCL HIGH.DATA - Between START and STOP cycles, SDA is synchronous with SCL.
Data may change only when SCL is LOW and must be stable when SCL is HIGH.ACKNOWLEDGE (AK) – SDA is driven LOW before the SCL rising edge and held LOW until the SCL falling edge.
STOP (SP)
– defined as low-to-high transition on SDA while holding SCL HIGH.
Data Byte values latched into control registers here.
↑
I 2C I NTERFACE - P ROTOCOL
The ICS84330-03 is a slave-only device and uses the stan-dard I 2C protocol as shown in the below diagrams. The maxi-
A serial transfer to the ICS84330-03 always consists of an address cycle followed by 4 data bytes: 1 dummy byte fol-lowed by 3 data bytes. Any additional bytes beyond the 4 data bytes will not be acknowledged and the ICS84330-03 will leave the data bus HIGH. These extra bits will not be loaded into the serial control register. Once the 4 Data bytes are loaded I 2C I NTERFACE - A W RITE E XAMPLE
mum SCL frequency is greater than 10MHz which is more than sufficient for standard I 2C clock speeds.
and the master generates a stop condition, the values in the serial control register are latched into the M divider, N divider,and control bits and the device will smoothly slew to the new frequency and any changes to the state of the control bits will take effect.
SCL
SDA
ST ART Valid Data Acknowledge STOP
s
t i B 8:2e t y B a t a D K
A P S p U n w o D 5C S S 4C S S 3C S S 2C S S 1C S S 0C S S t
i B 1t
i B 1s t i B 8:1e t y B a t a D K
A 2M 1M 0
M t o N d e s U t o N d e s U t
o N d
e s U t o N d
e s U t o N d e s U t i B 1
D IFFERENTIAL LVPECL F REQUENCY S YNTHESIZER
S PREAD S PECTRUM O PERATION
NOTE: The functional description that follows used a 16.6667MHz crystal with an M divide value of 160.Spread Spectrum operation is controlled by I 2C Data Byte 2, Spread Spectrum Control Register. Bits SSC0 – SSC5(SS) of the register are a subtrahend to the M-divider for down-spread, and they are an addend and a subtrahend to the M-divider for center-spread. When the UP bit is HIGH,then up-spread has been selected and the M-divider value will toggle between the programmed M value, and M+SS at a 32kHz rate. When the DN bit is HIGH, then down-spread
has been selected and the M-divider value will toggle be-tween the programmed M value, and M-SS at a 32kHz rate.When both the UP and DN bits are HIGH, then center-spread has been selected and the M-divider will toggle between M+SS and M-SS at a 32kHz rate. The table below shows the desired SS value to achieve 0.5%, 1% and 1.5%spread at selected VCO frequencies. To disable Spread Spectrum operation, program both the UP and DN bits to LOW. Spread Spectrum operation will also be disabled when the nP_LOAD input is LOW.
e
u l a V S S d a e r p S -n w o D r o -p U %d a e r p S 5C S S 4C S S 3C S S 2C S S 1C S S 0C S S 00000105.000010000.100011005.100100000.200101005.200110000.300111005.30
1
0.4e
u l a V S S d a e r p S -r e t n e C %
)±(d a e r p S 5C S S 4C S S 3C S S 2C S S 1C S S 0C S S 0000010
5.000010000.100011005.10
1
0.2T ABLE 1B. U P /D OWN S PREAD C ONFIGURA TION
T ABLE 1C. C ENTER S PREAD C ONFIGURA TION
s t i B r e t s i g e R e d o M S S 7C S S 6C S S 00f
f O 01d a e r p S -n w o D 10d a e r p S -p U 1
1
d
a e r p S -r e t n e C T ABLE 1A. SS M ODE F UNCTION T ABLE
D IFFERENTIAL LVPECL F REQUENCY S YNTHESIZER
The programmable features of the ICS84330-03 support two input modes to program the M divider and N output divider. The two input operational modes are parallel and I 2C. Figure 1 shows the timing diagram for parallel mode. In parallel mode the nP_LOAD input is LOW. The data on inputs M0 through M8 and N0 through N1 is passed directly to the M divider and N output divider. On the LOW-to-HIGH transition of the nP_LOAD input, the data is latched and the M divider remains loaded until the next LOW tran-sition on nP_LOAD or until an I 2C event occurs. The rela-tionship between the VCO frequency, the crystal frequency and the M divider is defined as follows:The M value and the required values of M0 through M8 are shown in Table 3B, Programmable VCO Frequency Func-tion Table. Valid M values for which the PLL will achieve lock are defined as 120 ≤ M ≤ 336. The frequency out is defined as follows:F UNCTIONAL D ESCRIPTION
NOTE: The functional description that follows describes op-eration using a 16.6667MHz crystal. Valid PLL loop divider values for different crystal or input frequencies are defined in the Input Frequency Characteristics, Table 7, NOTE 1.The ICS84330-03 features a fully integrated PLL and therefore requires no external components for setting the loop bandwidth. A quartz crystal is used as the input to the on-chip oscillator. The output of the oscillator is divided by 16 prior to the phase detector.
The phase detector and the M divider force the VCO output frequency to be 2M times the reference frequency by adjusting the VCO control voltage. Note that for some values of M (either too high or too low), the PLL will not achieve lock. The output of the VCO is scaled by a divider prior to being sent to each of the LVPECL output buffers.The divider provides a 50% output duty cycle.
F IGURE 1. P ARALLEL L OAD O PERATIONS
16
2M
fVCO =fxtal x N fout =fVCO =16
2M
fxtal x N Time
P ARALLEL L OADING
D IFFERENTIAL LVPECL F REQUENCY S YNTHESIZER
T ABLE 3. P IN C HARACTERISTICS
T ABLE 2. P IN D ESCRIPTIONS
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n i p y l p p u s g o l a n A 6T X E _F E R F t u p n I n w o d l l u P .
s l e v e l e c a f r e t n i L T T V L /S O M C V L .t u p n i e c n e r e f e r L L P 7L E S _L A T X t u p n I p
u l l u P L L P e h t s a s t u p n i T X E _F E R F r o r o t a l l i c s o l a t s y r c e h t n e e w t e b s t c e l e S T X E _F E R F s t c e l e S .H G I H n e h w s t u p n i L A T X s t c e l e S .e c r u o s e c n e r e f e r .
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d i v i d t u p t u o N
e h t s t e s 0N :1N t a t n e s e r p a t a d n e h w d n a ,r e d i v i d M o t n i .s l e v e l e c a
f r e t n i L T T V L /S O M C V L .e u l a v ,41,31,21,81,71,5102,912M ,1M ,0M 5M ,4M ,3M 7M ,6M t u p n I n w o d l l u P D
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s l e v e l e c a f r e t n i L T T V L /S O M C V L .t u p n i 128M t u p n I p
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s n i p y l p p u s e r o C 8
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s l e v e l e c a f r e t n i L C E P V L .s t u p t u o k c o l c l a i t n e r e f f i D :E T O N p u l l u P d n a n w o d l l u P .s e u l a v l a c i p y t r o f ,s c i t s i r e t c a r a h C n i P ,3e l b a T e e S .s r o t s i s e r t u p n i l a n r e t n i o t r e f e r .
e d o m l e l l a r a p n i e v i t c a y l n o s i r o t s i s e r p u l l u P :1E T O N l o b m y S r e t e m a r a P s
n o i t i d n o C t s e T m
u m i n i M l a c i p y T m
u m i x a M s t i n U C N I e c n a t i c a p a C t u p n I 4F p R P U L L U P r o t s i s e R p u l l u P t u p n I 15k ΩR N
W O D L L U P r
o t s i s e R n w o d l l u P t u p n I 1
5k Ω
D IFFERENTIAL LVPECL F REQUENCY S YNTHESIZER
T ABLE 4A. P ROGRAMMABLE VCO F REQUENCY F UNCTION T ABLE
T ABLE 4B. P ROGRAMMABLE O UTPUT D IVIDER F UNCTION T ABLE
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D IFFERENTIAL LVPECL F REQUENCY S YNTHESIZER
T ABLE 5C. LVPECL DC C HARACTERISTICS, V
CC = V
CCA
= 3.3V±5%, T A = 0°C TO 70°C
T ABLE 5A. P OWER S UPPL Y DC C HARACTERISTICS, V
CC = V
CCA
= 3.3V±5%, T A = 0°C TO 70°C
T ABLE 5B. LVCMOS / LVTTL DC C HARACTERISTICS, V
CC = V
CCA
= 3.3V±5%, T A = 0°C TO 70°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
A BSOLUTE M AXIMUM R ATINGS
Supply Voltage, V
CC
4.6V
Inputs, V
I -0.5V to V
CC
+ 0.5 V
Outputs, I
O
Continuous Current50mA
Surge Current100mA
Package Thermal Impedance, θ
JA
47.9°C/W (0 lfpm)
Storage Temperature, T
STG
-65°C to 150°C
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D IFFERENTIAL LVPECL F REQUENCY S YNTHESIZER
T ABLE 7. I NPUT F REQUENCY C HARACTERISTICS , V CC = V CCA = 3.3V±5%, T A = 0°C TO 70°C
T ABLE 6. C RYSTAL C HARACTERISTICS
T ABLE 8. AC C HARACTERISTICS , V CC = V CCA = 3.3V±5%, T A = 0°C TO 70°C
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D IFFERENTIAL LVPECL F REQUENCY S YNTHESIZER P ARAMETER M EASUREMENT I NFORMATION
D IFFERENTIAL LVPECL F REQUENCY S YNTHESIZER
A PPLICATION I NFORMATION
As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS84330-03 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. V CC and V CCA should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance,power supply isolation is required. Figure 2 illustrates how a 10Ω resistor along with a 10μF and a .01μF bypass capacitor should be connected to each V CCA pin. The 10Ωresistor can also be replaced by a ferrite bead.
F IGURE 2. P OWER S UPPLY F
ILTERING
P OWER S UPPLY F ILTERING T ECHNIQUES
I NPUTS :
S ELECT P INS :
All select pins have internal pull-ups and pull-downs;additional resistance is not required but can be added for additional protection. A 1k Ω resistor can be used.
R ECOMMENDATIONS FOR U NUSED I NPUT AND O UTPUT P INS
C RYSTAL I NPUT I NTERFACE
The ICS84330-03 has been characterized with 18pF paral-lel resonant crystals. The capacitor values, C1 and C2,shown in Figure 3 below were determined using an 18pF parallel resonant crystal and were chosen to minimize the ppm error. These same capacitor values will tune any 18pF
parallel resonant crystal over the frequency range and other parameters specified in this data sheet. The optimum C1and C2 values can be slightly adjusted for different board layouts.
O UTPUTS :LVPECL O UTPUT
All unused LVPECL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated.
D IFFERENTIAL LVPECL F REQUENCY S YNTHESIZER
LVCMOS TO XTAL I NTERFACE
The XTAL_IN input can accept a single-ended LVCMOS signal through an AC couple capacitor. A general interface diagram is shown in Figure 4. The XTAL_OUT pin can be left floating. The input edge rate can be as slow as 10ns. F or LVCMOS inputs, it is recommended that the amplitude be reduced from full swing to half swing in order to prevent signal interference with the power rail and to reduce noise. This configuration requires that the output
ENERAL IAGRAM FOR RIVER TO NPUT NTERFACE
impedance of the driver (Ro) plus the series resistance (Rs) equals the transmission line impedance. In addition,matched termination at the crystal input will attenuate the signal in half. This can be done in one of two ways. F irst,R1 and R2 in parallel should equal the transmission line impedance. F or most 50Ω applications, R1 and R2 can be 100Ω. This can also be accomplished by removing R1 and making R2 50Ω.
IGURE YCLE TO YCLE ITTER VS (using a 16MHz XTAL)
D IFFERENTIAL LVPECL F REQUENCY S YNTHESIZER
If the FREF_EXT input is driven by a 3.3V LVCMOS driver, the jitter performance can be improved by reducing the amplitude swing and slowing down the edge rate. Figure 6A shows an amplitude reduction approach for a long trace. The swing will be approximately 0.85V for logic low and 2.5V for logic high
J ITTER R EDUCTION FOR FREF_EXT S INGLE E ND I NPUT
(instead of 0V to 3.3V). Figure 6B shows amplitude reduction approach for a short trace. The circuit shown in Figure 6C reduces amplitude swing and also slows down the edge rate by increasing the resistor value.
F IGURE 6C. E DGE R A TE R EDUCTION BY I NCREASIN
G THE R ESISTOR V ALUE
F IGURE 6A. A MPLITUDE R EDUCTION FOR A L ON
G T RACE
D IFFERENTIAL LVPECL F REQUENCY S YNTHESIZER
Spread-spectrum clocking is a frequency modulation tech-nique for EMI reduction. When spread-spectrum is enabled,a 32kHz triangle waveform is used from the nominal 333MHz clock frequency. An example of a triangle frequency modu-lation profile is shown in Figure 7A below. The ramp profile can be expressed as:
?Fnom = Nominal Clock Frequency in Spread OFF mode (333MHz with 16.6667MHz IN)
?Fm = Nominal Modulation Frequency (32kHz)?δ = Modulation Factor (0.25% down spread)(1 - δ) fnom + 2 fm x δ x fnom x t when 0 < t <,
(1 - δ) fnom - 2 fm x δ x fnom x t when < t <12 fm 12 fm 1fm
It is important to note the ICS84330-03 7dB minimum
spectral reduction is the component-specific EMI reduc-tion, and will not necessarily be the same as the system EMI reduction.
F IGURE 7B. 333MH Z C LOCK O UTPUT IN F REQUENCY D OMAIN
(A) S PREAD -S PECTRUM OFF (B) S PREAD -S PECTRUM ON
F IGURE 7A. T RIANGLE F REQUENCY M ODULA TION S PREAD S PECTRUM
Δ ? 10 dBm
B A
δ = 0.25%?
?
D IFFERENTIAL LVPECL F REQUENCY S YNTHESIZER
The clock layout topology shown below is a typical termina-tion for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, ter-minating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are
F IGURE 8B. LVPECL O UTPUT T ERMINATION
F IGURE 8A. L VPECL O UTPUT T ERMINATION designed to drive 50Ω transmission lines. Matched imped-ance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 8A and 8B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations.
T ERMINATION FOR LVPECL O UTPUTS
D IFFERENTIAL LVPECL F REQUENCY S YNTHESIZER
θJA by Velocity (Linear Feet per Minute)
200
500
Single-Layer PCB, JEDEC Standard Test Boards 67.8°C/W 55.9°C/W 50.1°C/W Multi-Layer PCB, JEDEC Standard Test Boards
47.9°C/W
42.1°C/W
39.4°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
T ABLE 9. T HERMAL R ESISTANCE θJA FOR 32-PIN LQFP , F ORCED C ONVECTION
P OWER C ONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS84330-03.Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS84330-03 is the sum of the core power plus the power dissipated in the load(s).The following is the power dissipation for V CC = 3.3V + 5% = 3.465V , which gives worst case results.NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
?Power (core)MAX = V CC_MAX * I EE_MAX = 3.465V * 180mA = 623.7mW ?
Power (outputs)MAX = 30.2mW/Loaded Output pair
If all outputs are loaded, the total power is 2 * 30mW = 60mW
Total Power _MAX (3.465V , with all outputs switching) = 623.7 + 60mW = 683.7mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockS TM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + T A Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)T A
= Ambient T emperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA
must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1°C/W per Table 9 below.Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.684W * 42.1°C/W = 98.8°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,and the type of board (single layer or multi-layer).
D IFFERENTIAL LVPECL F REQUENCY S YNTHESIZER
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.LVPECL output driver circuit and termination are shown in the Figure 9.
T o calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage of V CC
- 2V .
?
For logic high, V OUT = V OH_MAX
= V
CC_MAX
– 0.9V
(V
CC_MAX
- V
OH_MAX
) = 0.9V
?
For logic low, V OUT = V OL_MAX
= V
CC_MAX
– 1.7V
(V
CC_MAX
- V
OL_MAX
) = 1.7V
Pd_H is power dissipation when the output drives high.Pd_L is the power dissipation when the output drives low.Pd_H = [(V
OH_MAX – (V
CC_MAX - 2V))/R L
] * (V
CC_MAX
- V
OH_MAX
) = [(2V - (V
CC _MAX
- V
OH_MAX
))/R L
] * (V
CC_MAX
- V
OH_MAX
) =
[(2V - 0.9V)/50Ω] * 0.9V = 19.8mW Pd_L = [(V
OL_MAX
– (V
CC_MAX
- 2V))/R L
] * (V
CC_MAX
- V
OL_MAX
) = [(2V - (V
CC _MAX
- V
OL_MAX
))/R L
] * (V
CC_MAX
- V
OL_MAX
) =
[(2V - 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
D IFFERENTIAL LVPECL F REQUENCY S YNTHESIZER
R ELIABILITY I NFORMATION
T RANSISTOR C OUNT
The transistor count for ICS84330-03 is: 9304
θJA by Velocity (Linear Feet per Minute)
200
500
Single-Layer PCB, JEDEC Standard Test Boards 67.8°C/W 55.9°C/W 50.1°C/W Multi-Layer PCB, JEDEC Standard Test Boards
47.9°C/W
42.1°C/W
39.4°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
T ABLE 10. θJA VS . A IR F LOW 32 L EAD LQFP T ABLE
D IFFERENTIAL LVPECL F REQUENCY S YNTHESIZER
D IFFERENTIAL LVPECL F REQUENCY S YNTHESIZER
T ABLE 12. O RDERING I NFORMA TION
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments.The aforementioned trademark, HiPerClockS is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
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