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Virtex-5 Family OverviewDS100 (v5.1) August 21, 2015Product SpecificationDigitally Controlled Impedance (DCI)Active I/O Termination•Optional series or parallel termination •Temperature and voltage compensation •Makes board layout much easier−Reduces resistors −Places termination in the ideal location, at the signalsource or destination Configuration •Support for platform Flash, standard SPI Flash, or standard parallel NOR Flash configuration •Bitstream support with dedicated fallback reconfiguration logic •256-bit AES bitstream decryption provides intellectual property security and prevents design copying •Improved bitstream error detection/correction capability •Auto bus width detection capability •Partial Reconfiguration via ICAP port Advanced Flip-Chip Packaging •Pre-engineered packaging technology for proven superior signal integrity−Minimized inductive loops from signal to return −Optimal signal-to-PWR/GND ratios •Reduces SSO induced noise by up to 7x •Pb-Free and standard packages System Monitor •On-Chip temperature measurement (±4°C)•On-Chip power supply measurement (±1%)•Easy to use, self-contained −No design required for basic operation −Autonomous monitoring of all on-chip sensors −User programmable alarm thresholds for on-chip sensors•User accessible 10-bit 200kSPS ADC −Automatic calibration of offset and gain error −DNL = ±0.9 LSBs maximum •Up to 17 external analog input channels supported −0V to 1V input range −Monitor external sensors e.g., voltage, temperature −General purpose analog inputs •Full access from fabric or JT AG TAP to System Monitor •Fully operational prior to FPGA configuration and during device power down (access via JTAG T AP only)65-nm Copper CMOS Process • 1.0V Core Voltage •12-layer metal provides maximum routing capability and accommodates hard-IP immersion •Triple-oxide technology for proven reduced static power consumption System Blocks Specific to the LXT, SXT, TXT, and FXT DevicesIntegrated Endpoint Block for PCI ExpressCompliance•Works in conjunction with RocketIO GTP transceivers (LXT and SXT) and GTX transceivers (TXT and FXT)to deliver full PCI Express Endpoint functionality withminimal FPGA logic utilization.•Compliant with the PCI Express Base Specification 1.1•PCI Express Endpoint block or Legacy PCI Express Endpoint block•x8, x4, or x1 lane width •Power management support •Block RAMs used for buffering •Fully buffered transmit and receive •Management interface to access PCI Express configuration space and internal configuration•Supports the full range of maximum payload sizes •Up to 6x 32 bit or 3x 64 bit BARs (or a combination of 32 bit and 64 bit)Tri-Mode Ethernet Media Access Controller •Designed to the IEEE 802.3-2002 specification •Operates at 10, 100, and 1,000 Mb/s •Supports tri-mode auto-negotiation •Receive address filter (5 address entries)•Fully monolithic 1000Base-X solution with RocketIO GTP transceivers •Supports multiple external PHY connections (RGMII,GMII, etc.) interfaces through soft logic and SelectIO resources •Supports connection to external PHY device through SGMII using soft logic and RocketIO GTP transceivers •Receive and transmit statistics available through separate interface •Separate host and client interfaces •Support for jumbo frames •Support for VLAN •Flexible, user-configurable host interface •Supports IEEE 802.3ah-2004 unidirectional modeVirtex-5 Family OverviewDS100 (v5.1) August 21, 2015Product Specification Table 1:Virtex-5 FPGA Family Members Device Configurable Logic Blocks (CLBs)DSP48E Slices (2)Block RAM Blocks CMTs (4)PowerPC Processor Blocks Endpoint Blocks for PCI ExpressEthernet MACs (5)Max RocketIO Transceivers (6)Total I/O Banks (8)Max User I/O (7)Array (Row x Col)Virtex-5 Slices (1)Max Distributed RAM (Kb)18Kb (3)36Kb Max (Kb)GTP GTX XC5VLX3080x 304,8003203264321,1522N/A N/A N/A N/A N/A 13400XC5VLX50120x 307,2004804896481,7286N/A N/A N/A N/A N/A 17560XC5VLX85120x 5412,96084048192963,4566N/A N/A N/A N/A N/A 17560XC5VLX110160x 5417,2801,120642561284,6086N/A N/A N/A N/A N/A 23800XC5VLX155160x 7624,3201,6401283841926,9126N/A N/A N/A N/A N/A 23800XC5VLX220160x 10834,5602,2801283841926,9126N/A N/A N/A N/A N/A 23800XC5VLX330240x 10851,8403,42019257628810,3686N/A N/A N/A N/A N/A 331,200XC5VLX20T60x 263,1202102452269361N/A 124N/A 7172XC5VLX30T80x 304,8003203272361,2962N/A 148N/A 12360XC5VLX50T120x 307,20048048120602,1606N/A 1412N/A 15480XC5VLX85T120x 5412,960840482161083,8886N/A 1412N/A 15480XC5VLX110T160x 5417,2801,120642961485,3286N/A 1416N/A 20680XC5VLX155T 160x 7624,3201,6401284242127,6326N/A 1416N/A 20680XC5VLX220T 160x 10834,5602,2801284242127,6326N/A 1416N/A 20680XC5VLX330T 240x 10851,8403,42019264832411,6646N/A 1424N/A 27960XC5VSX35T 80x 345,440520192168843,0242N/A 148N/A 12360XC5VSX50T 120x 348,1607802882641324,7526N/A 1412N/A 15480XC5VSX95T 160x 4614,7201,5206404882448,7846N/A 1416N/A 19640XC5VSX240T 240x 7837,4404,2001,0561,03251618,5766N/A 1424N/A 27960XC5VTX150T 200x 5823,2001,500804562288,2086N/A 14N/A 4020680XC5VTX240T 240x 7837,4402,4009664832411,6646N/A 14N/A 4820680XC5VFX30T 80x 385,12038064136682,4482114N/A 812360XC5VFX70T 160x 3811,2008201282961485,3286134N/A 1619640XC5VFX100T 160x 5616,0001,2402564562288,2086234N/A 1620680XC5VFX130T 200x 5620,4801,58032059629810,7286236N/A 2024840XC5VFX200T 240x 6830,7202,28038491245616,4166248N/A 2427960Notes:1.Virtex-5 FPGA slices are organized differently from previous generations. Each Virtex-5 FPGA slice contains four LUTs and four flip-flops (previously it was two LUTs and two flip-flops.)2.Each DSP48E slice contains a 25x 18 multiplier, an adder, and an accumulator.3.Block RAMs are fundamentally 36Kbits in size. Each block can also be used as two independent 18-Kbit blocks.4.Each Clock Management Tile (CMT) contains two DCMs and one PLL.5.This table lists separate Ethernet MACs per device.6.RocketIO GTP transceivers are designed to run from 100Mb/s to 3.75Gb/s. RocketIO GTX transceivers are designed to run from 150Mb/s to 6.5Gb/s.7.This number does not include RocketIO transceivers.8.Includes configuration Bank 0.。
abstractroutingdatasource用法-回复AbstractRoutingDataSource是Spring框架中的一个数据源类，用于支持多数据源的动态切换。
本文将一步一步介绍AbstractRoutingDataSource的用法和原理，并提供示例代码进行演示。
第一步，引入相关依赖和配置在使用AbstractRoutingDataSource之前，需要确保项目中引入了Spring框架的相关依赖。
可以通过Maven或者Gradle等依赖管理工具进行引入。
另外，还需要对数据源进行配置，包括数据源的基本信息、连接池配置等。
第二步，创建AbstractRoutingDataSource的子类首先，需要创建一个继承自AbstractRoutingDataSource的子类，用于实现数据源的动态切换逻辑。
在子类中需要实现determineCurrentLookupKey方法，该方法通过获取当前线程绑定的数据源标识符来确定使用哪个数据源。
javapublic class DynamicDataSource extends AbstractRoutingDataSource {@Overrideprotected Object determineCurrentLookupKey() {return DataSourceContextHolder.getDataSource();}}在上述代码中，我们通过自定义的DataSourceContextHolder类来获取当前线程绑定的数据源标识符。
该类可以使用ThreadLocal来实现，确保每个线程访问的数据源都是独立的。
第三步，配置数据源与AbstractRoutingDataSource接下来，需要对数据源和AbstractRoutingDataSource进行配置。
通过读取配置文件或者编程方式创建数据源，并将数据源与AbstractRoutingDataSource进行绑定。
Java AbstractRoutingDataSource 切换数据源原理1. 引言1.1 背景在Java应用开发中，数据源的选择对系统性能和稳定性有着重要影响。
Java中的`AbstractRoutingDataSource`提供了一种动态切换数据源的机制，允许开发者根据实际需求动态选择使用的数据源，为应对多数据源的场景提供了便利。
1.2 作用`AbstractRoutingDataSource`允许在运行时动态切换数据源，使得应用程序能够根据具体业务需求来选择合适的数据源，从而更好地实现数据的分离和管理。
2. AbstractRoutingDataSource 的基本概念2.1 继承关系`AbstractRoutingDataSource`是Spring Framework中`AbstractDataSource`的子类，它本身并不直接连接数据库，而是负责动态切换实际的数据源。
2.2 数据源的抽象`AbstractRoutingDataSource`将真正的数据源抽象成`DataSource`的形式，通过继承和实现相关接口，达到在运行时选择具体数据源的目的。
2.3 动态数据源的切换通过维护一个ThreadLocal变量，`AbstractRoutingDataSource`能够在每个线程中保存和切换数据源的信息，确保线程内部的数据库操作都使用指定的数据源。
3. 实现原理3.1 ThreadLocal的使用`AbstractRoutingDataSource`通过ThreadLocal存储和获取当前线程选择的数据源。
每个线程都可以独立设置和获取自己的数据源，避免了线程安全问题。
3.2 determineCurrentLookupKey() 方法在`AbstractRoutingDataSource`中，有一个抽象方法`determineCurrentLookupKey()`，该方法用于决定使用哪个数据源。
ng.NullPointerException原因是：有空指针，有地址没赋值2.Exception in thread "main" ng.ArithmeticException: / by zero原因是除数是03.ArrayIndexOutOfBoundsException原因是：数组越界ng.NumberFormatException原因是：数字格式化有问题5.Unhandled exception type Exception原因是：没有进行异常处理6.进行国际化操作的时候遇到这样的错误：Exception in thread "main" java.util.MissingResourceException: Can't find bundle for base name Message, locale zh_CN答：因为在命令提示符中，是没有错误的解决方法是：在myeclipse中，会出现这个错误java国际化之Can't find bundle for base name1.初步学习最近在学习ResourseBundle时遇到了“Can't find bundle for base name ”这个错误搞了很久才解决了。
原因就是类路径问题要将属性文件放在类路径中！百度里很多都是教程但没有涉及到解决方法！2.中文显示：测试文件java 代码package com.lht.ResourseBundleStudy;import java.util.ResourceBundle;public class ResourseBundleDemo {public static void main(String[] args) {ResourceBundle resource = ResourceBundle.getBundle("test");System.out.print(resource.getString("msg0") + "!");System.out.println(resource.getString("msg1") + "!"); }}test.propertiesmsg0="Hello World"msg1="da jia hao"开始自己测试的时候：将属性文件放在bin/下也试过也不行无赖中就在google中搜索了一下终于在sun的java论坛(/thread.jspa?threadID=660477&messageID=4231534)中找到了线索下面是帖子的内容：I've solved the problem the best way possible. Basically what i've done is added a new class folder named config to the project home dir. Then i added this classfolder to the classpath in project properties. After doing all of this you only need to reference the properties file by "Email".Hope this helps anyone else who is having similiar problems.基本意思就是在src下建立classes(名字无所谓)文件夹将属性文件存放在下面，然后将这个文件夹加入类路径中！运行就可以了：加入类路径的方法:你的工程文件夹->properties->选择Libraries选项卡->Add Class Folder 将刚才建立的文件夹加入就可以了！结果如下："Hello World"!"da jia hao";!2.中文显示在classes目录下建立message_CH.properties内容如下:ms0="大家好"同样用上面的测试文件！结果如下："?ó????"!乱码怎么回事啊！在百度里搜索后找到了答案有以为网友写的很清楚：/3885062.html 下面引用如下:原理Property文件中，使用的编码方式根据机器本身的设置可能是GBK或者UTF-8。
abstractroutingdatasource用法摘要：1.abstractrouting 数据源概述2.abstractrouting 数据源的基本用法3.abstractrouting 数据源的高级用法4.abstractrouting 数据源的示例正文：【1.abstractrouting 数据源概述】abstractrouting 数据源是一个用于处理数据的高级数据结构，它可以帮助用户方便地管理和操作数据。
abstractrouting 数据源通常用于实现数据路由、数据分发、数据处理等功能，使得数据的流动更加高效和有序。
【2.abstractrouting 数据源的基本用法】abstractrouting 数据源的基本用法主要包括以下几个步骤：1) 定义数据源：首先需要定义一个数据源对象，这个对象包含了数据源的基本信息，如数据源的ID、名称等。
2) 配置数据源：根据实际需求，对数据源进行配置，包括数据源的类型、数据源的连接方式、数据源的读写权限等。
3) 注册数据源：将定义好的数据源对象注册到系统中，使得系统能够识别和使用这个数据源。
4) 使用数据源：在程序中使用数据源，通过数据源对象的操作方法，实现对数据的读写和处理。
【3.abstractrouting 数据源的高级用法】除了基本的用法之外，abstractrouting 数据源还提供了一些高级的用法，如：1) 数据源路由：通过配置数据源的路由规则，实现数据的自动路由和分发。
2) 数据源聚合：通过数据源的聚合操作，实现对多个数据源的合并和整合。
3) 数据源监控：通过数据源的监控功能，实时了解数据源的运行状态和性能指标。
Addendum-Page 1PACKAGING INFORMATIONOrderable Device Status(1)Package Type PackageDrawingPins Package QtyEco Plan(2)Lead/Ball FinishMSL Peak Temp (3)Samples (Requires Login)5962-8407501VEA ACTIVE CDIP J 1625TBD A42N / A for Pkg Type 5962-8407501VFAACTIVE CFP W 1625TBD A42N / A for Pkg Type 84075012A ACTIVE LCCC FK 201TBD Call TI Call TI 8407501EA ACTIVE CDIP J 161TBD Call TI Call TI 8407501FA ACTIVE CFP W 161TBD Call TI Call TIJM38510/66302BEA ACTIVE CDIP J 161TBD A42N / A for Pkg Type JM38510/66302BFA ACTIVE CFP W 161TBD A42N / A for Pkg Type M38510/66302BEA ACTIVE CDIP J 161TBD A42N / A for Pkg Type M38510/66302BFA ACTIVE CFP W 161TBD A42N / A for Pkg Type SN54HC161J ACTIVE CDIP J 161TBDA42N / A for Pkg TypeSN74HC161D ACTIVE SOIC D 1640Green (RoHS & no Sb/Br)CU NIPDAU Level-1-260C-UNLIM SN74HC161DE4ACTIVE SOIC D 1640Green (RoHS & no Sb/Br)CU NIPDAU Level-1-260C-UNLIM SN74HC161DG4ACTIVE SOIC D 1640Green (RoHS & no Sb/Br)CU NIPDAU Level-1-260C-UNLIM SN74HC161DR ACTIVE SOIC D 162500Green (RoHS & no Sb/Br)CU NIPDAU Level-1-260C-UNLIM SN74HC161DRE4ACTIVE SOIC D 162500Green (RoHS & no Sb/Br)CU NIPDAU Level-1-260C-UNLIM SN74HC161DRG4ACTIVE SOIC D 162500Green (RoHS & no Sb/Br)CU NIPDAU Level-1-260C-UNLIM SN74HC161DT ACTIVE SOIC D 16250Green (RoHS & no Sb/Br)CU NIPDAU Level-1-260C-UNLIM SN74HC161DTE4ACTIVE SOIC D 16250Green (RoHS & no Sb/Br)CU NIPDAU Level-1-260C-UNLIM SN74HC161DTG4ACTIVE SOIC D 16250Green (RoHS & no Sb/Br)CU NIPDAU Level-1-260C-UNLIM SN74HC161N ACTIVE PDIP N 1625Pb-Free (RoHS)CU NIPDAU N / A for Pkg Type SN74HC161N3OBSOLETE PDIP N 16TBD Call TICall TISN74HC161NE4ACTIVEPDIPN1625Pb-Free (RoHS)CU NIPDAU N / A for Pkg Type芯天下--/Addendum-Page 2Orderable Device Status(1)Package Type PackageDrawingPins Package QtyEco Plan(2)Lead/Ball FinishMSL Peak Temp(3)Samples (Requires Login)SN74HC161NSR ACTIVE SO NS 162000Green (RoHS & no Sb/Br)CU NIPDAU Level-1-260C-UNLIM SN74HC161NSRE4ACTIVE SO NS 162000Green (RoHS & no Sb/Br)CU NIPDAU Level-1-260C-UNLIM SN74HC161NSRG4ACTIVE SO NS 162000Green (RoHS & no Sb/Br)CU NIPDAU Level-1-260C-UNLIM SN74HC161PW ACTIVE TSSOP PW 1690Green (RoHS & no Sb/Br)CU NIPDAU Level-1-260C-UNLIM SN74HC161PWE4ACTIVE TSSOP PW 1690Green (RoHS & no Sb/Br)CU NIPDAU Level-1-260C-UNLIM SN74HC161PWG4ACTIVE TSSOP PW 1690Green (RoHS & no Sb/Br)CU NIPDAU Level-1-260C-UNLIM SN74HC161PWR ACTIVE TSSOP PW 162000Green (RoHS & no Sb/Br)CU NIPDAU Level-1-260C-UNLIM SN74HC161PWRE4ACTIVE TSSOP PW 162000Green (RoHS & no Sb/Br)CU NIPDAU Level-1-260C-UNLIM SN74HC161PWRG4ACTIVE TSSOP PW 162000Green (RoHS & no Sb/Br)CU NIPDAU Level-1-260C-UNLIM SN74HC161PWT ACTIVE TSSOP PW 16250Green (RoHS & no Sb/Br)CU NIPDAU Level-1-260C-UNLIM SN74HC161PWTE4ACTIVE TSSOP PW 16250Green (RoHS & no Sb/Br)CU NIPDAU Level-1-260C-UNLIM SN74HC161PWTG4ACTIVE TSSOP PW 16250Green (RoHS & no Sb/Br)CU NIPDAU Level-1-260C-UNLIM SNJ54HC161FK ACTIVE LCCC FK 201TBD POST-PLATE N / A for Pkg TypeSNJ54HC161J ACTIVE CDIP J 161TBD A42N / A for Pkg Type SNJ54HC161WACTIVECFPW161TBDA42N / A for Pkg Type(1)The marketing status values are defined as follows:ACTIVE: Product device recommended for new designs.LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.PREVIEW: Device has been announced but is not in production. Samples may or may not be available.OBSOLETE: TI has discontinued the production of the device.芯天下--/(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check /productcontent for the latest availability information and additional product content details.TBD: The Pb-Free/Green conversion plan has not been defined.Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.OTHER QUALIFIED VERSIONS OF SN54HC161, SN54HC161-SP, SN74HC161 :•Catalog: SN74HC161, SN54HC161•Military: SN54HC161•Space: SN54HC161-SPNOTE: Qualified Version Definitions:•Catalog - TI's standard catalog product•Military - QML certified for Military and Defense Applications•Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based applicationAddendum-Page 3芯天下--/TAPE AND REEL INFORMATION*All dimensions are nominalDevicePackage Type Package Drawing Pins SPQReel Diameter (mm)Reel Width W1(mm)A0(mm)B0(mm)K0(mm)P1(mm)W (mm)Pin1Quadrant SN74HC161DR SOIC D 162500330.016.4 6.510.3 2.18.016.0Q1SN74HC161NSR SO NS 162000330.016.48.210.5 2.512.016.0Q1SN74HC161PWR TSSOP PW 162000330.012.4 6.9 5.6 1.68.012.0Q1SN74HC161PWTTSSOPPW16250330.012.46.95.61.68.012.0Q1*All dimensions are nominalDevice Package Type Package Drawing Pins SPQ Length(mm)Width(mm)Height(mm) SN74HC161DR SOIC D162500333.2345.928.6 SN74HC161NSR SO NS162000367.0367.038.0 SN74HC161PWR TSSOP PW162000367.0367.035.0SN74HC161PWT TSSOP PW16250367.0367.035.0IMPORTANT NOTICETexas Instruments Incorporated and its subsidiaries(TI)reserve the right to make corrections,enhancements,improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B.Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.All semiconductor products(also referred to herein as“components”)are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.TI warrants performance of its components to the specifications applicable at the time of sale,in accordance with the warranty in TI’s terms and conditions of sale of semiconductor products.Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty.Except where mandated by applicable law,testing of all parameters of each component is not necessarily performed.TI assumes no liability for applications assistance or the design of Buyers’products.Buyers are responsible for their products and applications using TI components.To minimize the risks associated with Buyers’products and applications,Buyers should provide adequate design and operating safeguards.TI does not warrant or represent that any license,either express or implied,is granted under any patent right,copyright,mask work right,or other intellectual property right relating to any combination,machine,or process in which TI components or services are rmation published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or endorsement e of such information may require a license from a third party under the patents or other intellectual property of the third party,or a license from TI under the patents or other intellectual property of TI.Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties,conditions,limitations,and notices.TI is not responsible or liable for such altered rmation of third parties may be subject to additional restrictions.Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice. 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APPLICATIONTermination of fiber optic cabling via fusion splicing requires planning and coordination to successfully allow for acceptable performance, slack storage, transition from outer jacketing, grounding of armored cables and more.Leviton has several product solutions to achieve fusion splicing including Splice Trays, Splice Modules (in SDX and HDX formats) and Splice only enclosures.Each of these solutions allows fibers to be terminated from cable to cable or from cable to pigtail assemblies. This Applications Note will provide information about the preparation of bulk fiber or blunt ended, pre-terminated assemblies prior to the splicing process.TYPES OF CABLE JACKET CONSTRUCTIONAt the point of termination, fibers can be 900µm tight buffered, 250µm bare or loose tube or 250µm ribbonized. Depending on the outer jacket construction and fiber count, cables often need to exit the outer sheath or jacket and be presented to the splicing device at a sub-unitized level. This often also determines the options of where to place cable slack. Factors include:• Outer Jacket or sheath construction (OSP, Foiled, Armored, Air Blown)• Outside diameter of trunk cable or sub-unitized tubes and bend radius limitations • Fiber count and sub-unitized configuration of bulk cable • Maximum cable/tube diameter a splicing device can accept • Maximum number of fibers each splicing device can support •Amount of slack storage desired or requiredThe goal in most fiber optic installations is to maintain the protective qualities within the cable’s construction as close to the point of termination as possible. This usually includes having the overall cable enter an enclosure, patching frame or cable management feature or an open panel before individual or sub-unitized groups of fibers exit the cable jacket. Evaluating the required length to successfully terminate individual fibers is determined from this point. Attention needs to be made to allow for proper routing, bend radius control and exposure of fibers within a splice tray or module to successfully perform a fusion splice.Minimum lengths for expose sub-units in Leviton products:Leviton recommends a minimum of the following lengths required to perform terminations in Leviton SDX or HDX splicing products. Each termination scenario should be evaluated prior to cable preparation. Each measurement is from the exit point of the bulk fiber cable jacket to the end of the exposed sub-unitized tubing containing the individual fiber strands.• SDX Enclosures – minimum of 60 inches / 152 cm for Splice modules– minimum of 80 inches / 203 cm for Splice trays• HDX Enclosures – minimum of 60 inches / 152 cm • HDX Panels – minimum of 60 inches / 152 cm • HDX Frame – minimum of 50 inches / 127 cm (from exit of trunk clamp)This length does not factor in the following:▪ Removal of additional length prior to beginning the termination process to eliminate any damage or stressassociated with handling of the end of the cable during the pulling process. ▪ Required or desired overall slack storage (see references in this document)Once cabling has entered the location where splicing occurs, required lengths of exposed fiber varies. Refer to thetermination devices Instruction Sheet or User Guide for workable and exposed fiber required to successfully perform fusion Application Note ID: NS-AN-18-0030-09-28-18Date: 09-28-18Product Line: Fiber OpticsPart Numbers Affected: HDX Fiber DistributionFrameHDX Enclosures HDX Patch Panels SDX Enclosures SDX and HDX SpliceModules Splice TraysApplication Note: Planning for slack and preparation length when splicing fiberOVERALL SLACK STORAGEIt is good practice and often a project requirement to provide additionally stored fiber optic cable for re-termination or relocation. Several options are available when fiber is terminated in racks, cabinets or wall mounted devices: •Above racks or below access flooring in horizontal pathway•Attached to framework vertically in cabinets•Suspended under the top cover of a cabinet•Suspended vertically to a wall or in a ceiling spaceSTORED ABOVE OR BELOW A RACK OR CABINETSTORED WITHIN A CABINETCONSIDERATIONS WITH ARMORED CABLEArmored cables require additional consideration and labor steps prior to routing and termination•Armored cable is considerably more rigid, typically larger diameter and can be difficult to route and manage •Fiber Optic cable should exit the outer armored jacket at a point prior to slack storage•Immediately after entering a cabinet•In the horizontal pathway prior to entering a rack or cabinet•Be in proximity to a bonding sourceThe following are examples of recommended routing methods for SDX splice trays and HDX splice modules.SDX Splice ModulesSPLICE TRAYVELCRO LANCE POINTSLIDING SHELFTRUNK FIBERS 1-12PIGTAIL APIGTAIL BTRUNK FIBERS 13-24SDX SPLICE TRAY IN AN SDX ENCLOSURE*NOTE: SDX Splice Trays are accessible from the rear of a fixed or sliding tray enclosure. Sliding trays are removable from the front or rear.*NOTE: SDX Splice Modules are installed from the front side of an enclosure or panel only. SDX sliding trays can be removed rearward to perform terminations.HDX Splice ModulesPreferred splicing process and adequate, accessible slack should be verified before terminating HDX splice modules.HDX Splice Modules are installed from the front side of an enclosure, patch deck or panel only. When using HDX enclosures all trays are forward sliding only. With accessible slack, splicing can occur at the front of the enclosure or all trays can be removed to allow rearward splicing.In this scenario after termination, splice modules are passed to the front of the enclosure to be loaded by tray.When using an SDX to HDX adapter bracket (HDXAD-ACC), SDX sliding trays can be removed rearward to perform terminations.When used in an HDX Patch Panel the modules install from the front side only. Cabling is dressed on a rear cable manager, passed through to the front side of the panel and splice modules are terminated.When using an HDX patch deck, the modules are loaded from the front. The individual trays also slide rearward to perform terminations.Leviton Manufacturing Co., Inc. tech line 800 824-3005。
Minimum-Buffered Routing of Non-Critical Nets forSlew Rate and Reliability ControlCharles Alpert,†Andrew B.Kahng,Bao Liu,Ion M˘a ndoiu,and Alexander Zelikovsky‡CSE Department,UCSD,La Jolla,CA92093-0114†IBM Corporation,11400Burnet Road,Austin,TX78758‡CS Department,Georgia State University,Atlanta,GA30303alpert@,abk,bliu,mandoiu@,alexz@ AbstractIn high-speed digital VLSI design,bounding the load capacitance atgate outputs is a well-known methodology to improve coupling noiseimmunity,reduce degradation of signal transition edges,and reduce de-lay uncertainty due to coupling noise.Bounding load capacitance alsoimproves reliability with respect to hot-carrier oxide breakdown andAC self-heating in interconnects,and guarantees bounded input rise/falltimes at buffers and sinks.This paper introduces a new minimum-buffer routing problem(MBRP)formulation which requires that the capacitive load of eachbuffer,and of the source driver,be upper-bounded by a given constant.Our contributions include the following.We give linear-time algorithms for optimal buffering of a givenrouting tree with a single(inverting or non-inverting)buffer type.For simultaneous routing and buffering with a single non-invertingbuffer type,we give a factor21εapproximation algorithm andprove that no algorithm can guarantee a factor smaller than2unlessP=NP.For the case of a single inverting buffer type,we give a factor41εapproximation algorithm.We give local-improvement and clustering based MBRP heuristicswith improved practical performance,and present a comprehen-sive experimental study comparing the runtime/quality tradeoffs ofthe proposed MBRP heuristics on test cases extracted from recentindustrial designs.1IntroductionIn high-speed digital VLSI design,bounding the load capacitance at gateoutputs is a well-known part of today’s electrical correctness method-ologies.Bounds on load caps improve coupling noise immunity,reducedegradation of signal transition edges,and reduce delay uncertainty dueto coupling noise[13].According to[21],commercial EDA method-ologies and tools for signal integrity rely heavily on upper-bounding theload caps of drivers and buffers to prevent very long slew times on sig-nal transitions.Such buffer insertions for long or high-fanout nets arefor electrical–not timing optimization–reasons.1Essentially,load capbounds serve as proxies for bounds on input rise/fall times at buffersand sinks(Tellez and Sarrafzadeh[24]formally prove one such equiva-lence).Such bounds also improve reliability with respect to hot-carrieroxide breakdown(hot electrons)[9,11]and AC self-heating in intercon-nects[20],and facilitate technology migration since designs are morebalanced.1.1Previous WorkThe vast amount of research on buffer insertion can be roughly divided into three categories.Fanout optimization during logic synthesis.Works in this category (see,e.g.,[6,7,17,23])seek buffered routing topologies and focus on timing optimization.Since placement information is not available at the logic synthesis stage,the delay models used in these works mainly con-sist of gate delay and statistically inferred interconnect delay.In con-trast,our work is targeted to the early post-placement phases of the de-sign cycle.Timing-driven buffer insertion during routing.Works in this cate-gory concentrate on buffering timing-critical nets,e.g.,maximizing the required arrival time(RAT)at the source,often with no bounds on the number of buffers,power consumption,or area.The seminal work of Van Ginneken[25]proposed a dynamic programming approach to finding the optimum buffering of an already routed net,using identical buffers and at most one buffer per wire.Lillis et al.[15,16]extended the dynamic programming approach by incorporating slew effects into the delay model and performing simultaneous buffer insertion and wire sizing;they also considered formulations that seek to minimize area or power consumption subject to meeting given timing constraints.More recently,Alpert and Devgan[1]gave extensions to multiple buffers per wire,and Alpert,Devgan and Quay[2]extended the approach to simul-taneous noise and delay optimization.Okamoto and Cong[18]consid-ered simultaneous routing and buffer insertion,showing that significant delay reductions can be achieved over previous approaches which in-sert buffers into an already routed net.These techniques are appropriate for buffered routing of(relatively small)timing-critical nets,but not for upper-bounding slew rates in non-critical nets:(1)quadratic or worse runtimes reduce their applicability to large(tens of thousands of sinks) instances;(2)timing-driven objectives such as max RAT at the source, and reliance on unavailable or meaningless timing analyses and con-straints,lead to wasted resources(too many buffers inserted);and(3) minimizing area or power subject to RAT constraints as in[15,16]can-not guarantee that slew constraints will be met.Clock-tree buffering.Work on buffered clock trees has focused on de-lay[22]and skew minimization[8,19].Tellez and Sarrafzadeh[24] considered minimal buffer insertion in routed clock trees with skew and slew constraints.They argued that slew upper-bounds can be met by upper-bounding the lumped capacitive loads of the buffers,and gave a linear time algorithm for buffering a routed clock tree with a single non-inverting buffer type under these constraints.We differ from[24]in sev-eral respects.(1)We seek simultaneous routing and buffering,while[24] considers only the problem of buffering an already routed clock tree.(2) Besides non-inverting buffering,we also consider buffering with a single inverting buffer type,which requires handling additional sink polarity constraints(the number of inverting buffers on each source-to-sink path must be consistent with the given polarity of the sink).(3)Clock trees in[24]require bounded buffer skew–this constraint is not necessary in our application.1.2Our ContributionsOur contributions as as follows:We give linear-time algorithms for optimal buffering of a given routing tree with a single(inverting or non-inverting)buffer type.2 For simultaneous routing and buffering with a single non-inverting buffer type,we give a factor21εapproximation algorithm and prove that no algorithm can guarantee a factor smaller than2unless P=NP.For the case of a single inverting buffer type,we give a factor 41εapproximation algorithm.We give local-improvement and clustering based MBRP heuristics with improved practical performance,and present a comprehen-sive experimental study comparing the runtime/quality tradeoffs of the proposed MBRP heuristics on test cases extracted from recent industrial designs.cost T wire3We assume that buffers have a single input and a single output and thus are inserted only on the edges of T.Figure1:Since c T b C U,the tree T b(shaded area)must contain a buffer b in any optimum buffering B opt.B opt b b is then an optimum buffering of T containing b.cycle the wire area still cannot be estimated very accurately,since layer assignment and via information is not yet available.Therefore,we as-sume that each stage requires the same amount of routing resources and define the simplified routing cost as the number of stages in the buffered routing T,i.e.,cost T B1(2) Thus,in this paper we adopt the simplified cost measure(2): Minimum-Buffered Routing Problem(MBRP)Given a net N with source r and set of sinks S(with prescribed pari-ties),input capacitance c s for every sink s S,buffer input capacitance C b,unit-length wire capacitance C w,and load upper-bound C U,find a buffered routing tree T r V E B for N such that(a)c D b C U for every b B r,(b)(for inverting buffer type)the parity of the number of buffers oneach path from the source to any positive sink is the same,and opposite from the parity of the number of buffers on the paths from the source to any negative sink,and(c)cost T B1is minimum among all buffered routing trees sat-isfying conditions(a)and(b).3Exact Algorithms for Buffering Routed NetsIn this section we present two algorithms for optimally buffering an al-ready routed net using a single inverting or non-inverting buffer type. The running time of each algorithm is linear in the number of sinks and the number of inserted buffers.3.1Single Non-Inverting Buffer TypeOur algorithm for buffering a given routing tree with a single non-inverting buffer type is a generalization of a greedy algorithm for par-titioning node-weighted trees due to Kundu and Misra[14].Before de-scribing the algorithm we need to introduce two more definitions.Let T r V E be a routing tree.A vertex p of T is called critical if p is a bottom-most point of T such that T p cannot be driven by a single buffer.Formally,p is critical if c T p C U and c T u C U for every child u of p.A heaviest child u of p is one which accumulates more capacitance than any other child of p.Formally,u is a heaviest child of p if c T u c u p c T v c v p for every other child v of p.The algorithm(see Algorithm1)finds critical vertices by a post-order traversal of the input tree.Then,for every such critical vertexp,Figure2:When b is located on a different branch(shaded area)than that of the heaviest child u,c T u c u p c D b.Hence,B opt bb is an optimum buffering of T containing b.the algorithm repeatedly inserts buffers on the edge connecting p to its heaviest child,until p is no longer critical.Due to space limitations we only give here a simple recursive description of the algorithm;the details of an O S B time implementation can be found in[3].Algorithm1:Routed Net Buffering(RNB)1.Find a critical vertex p by a post-order traversal of T2.Find a heaviest child,u,of p.3.Insert a buffer b on the edge u p such that c u b min C U c T u c u p4.Recursivelyfind an optimum buffering B of T T b5.Return B B bTheorem1Algorithm1finds an optimum buffering of the input tree T with the given non-inverting buffer type.The proof of the theorem follows from the following two lemmas, corresponding to the two possible cases in Step3of the algorithm. Lemma1If p is a critical vertex of T and u is a child of p with C U c T u c u p,then there exists an optimum buffering of T containing a buffer b located on the edge u p such that c u b C U c T u(see Figure1).Proof.Let the optimum buffering of T consist of the set of buffers B opt. The subtree of T rooted at b must contain at least one buffer b from B opt since it has total capacitance equal to C U.The lemma follows by observing that B opt b b is a feasible buffering of T. Lemma2If p is a critical vertex of T and c u p C U c T u for the heaviest child u of p,then there exists an optimum buffering of T that contains a buffer b placed immediately below p on the edge u p(see Figure2).Proof.Let the optimum buffering of T consist of the set of buffers B opt. Since p is critical,T p must contain at least one buffer b of B opt.We claim that B opt b b is an optimum buffering of T.The claim follows as in Lemma1if b is located in T b.Otherwise,the claim follows by observing that(i)by optimality,there is no buffer of B opt on the path connecting b to p in T,and(ii)c T u c u p c D b,since u is the heaviest child of p.Notice that the capacitive load of each buffer inserted in Step3when c u p C U c T u is exactly C U,i.e.,these buffers are“fullyfilled.”Although this is not true for the buffers inserted when c u p C Uc T u,it is easy to see that in this case inserted buffers have a capacitive load of at least C U k,where k is the degree of p.In particular,when the routing tree T is binary,we obtain:Lemma3If the input to Algorithm1is a binary routing tree,then the lumped capacitive load of each inserted buffer is at least C U2.Lemma3will be used in proving the approximation guarantee for the algorithms in Section4.It also gives a way to satisfy the simulta-neous lower-and upper-bound constraints on buffer loads referred to in Footnote1,since every routing tree can be converted to a binary tree by inserting zero-length edges.3.2Single Inverting Buffer TypeOptimal buffering with a single inverting buffer type is more complex than buffering with a non-inverting buffer type.The greedy approach does not work in this case,and we must use dynamic programming. In bottom-up order,the algorithm(see Algorithm2)computes two solu-tions for each subtree of T,one for positive and one for negative topmost buffer input polarity.Then,after choosing the best output polarity for the source,it determines the position of the buffers by a top-down traversal. The running time of the algorithm is linear assuming that the degree of the routing tree T is bounded;in the rectilinear plane this assumption holds for all standard routing tree constructions,including the minimum spanning tree,the minimum-length Steiner tree,and approximations of the latter one.For simplicity,we give the algorithm for binary trees,i.e.,we assume that all vertices other than the source(which is the root of the tree)and the sinks(which are leaves)have outdegree2.Without loss of generality, we assume that sink input capacitances are all equal to0–nonzero sink capacitances can be compensated by increasing the length of the edges incident to the sinks.By scaling,we also assume that the unit wirelength capacitance,C w,is equal to1.The algorithm associates with each leaf v of the tree T two labels l v and l v such that one of them belongs to0C U and the other is0.The labels l v and l v represent the penalty capacitance incurred in assuming that the sink has the opposite polarity.Initially,for each sink s,l s0ifσsC U otherwiseand l s C U l s.For each tree leaf v,define the stem of v to be the edge connecting v to its parent.Also,define a fork of T to be a set of4vertices u v x1x2, where x1and x2are two leaves,v is the common parent of x1and x2,and u is the parent of v.The bottom-up phase of the algorithm consists of two main procedures:Reduce fork.The procedure Reducefork replaces a fork u v x1x2with the single edge u v,computes the appropriate labels for v,and modifies the number of buffers inserted on the edges v x1and v x2as needed.The labels of v depend on the labels of x1and x2and the length of the edges v x1and v x2.To guarantee optimality,Collapsefork,de-pending on whether0,1,or2buffers are inserted on each stem.In fact, since inserting2buffers in each of the two stems is always a dominated solution,we never need to check more than8cases.Theorem2Algorithm2finds an optimum buffering of the input tree T with the given inverting buffer type.Algorithm2:Routed Net Inverting Buffering(RNIB)1.T T2.For each s S do:Ifσs then l s0,else l s C Ul s C U l sReducefork u v x1x24.Insert buffers in T in top-down order:Let v be the single remaining leaf v in T,andµs.t.lµv0Insert nµv buffers on the edge r vFor each fork r v x1x2,in reverse order of collapsing,do:Insert nσx i buffers on edges v x i,i12,whereσµif nµv isodd andσµif nµv is even5.Return the set B of inserted buffersProcedure Reducefork u v x1x2//Check all feasible bufferings of the stems v x1and v x21.For each i j012012andσdo:lσi j max0l v x1lσx1i C U C bmax0l v x2lσx2j C U C bIf lσi j C U then lσi j lσi j i j C UElse,lσi j∞//i j buffers are not sufficient//Choose the topmost buffer positions2.For eachσdo:lσv min lσi j i j012iσjσargmin lσi j i j012//Find minimal label and normalize the opposite polarity label3.lµv min l v l vIf lµv lµv C U,then iµjµiµjµ,lµv lµv C U//Increment#of buffers for both stems and restore v’s labels4.For eachσdo:nσx1nσx1iσ,nσx2nσx1jσlσv lσv iσjσC u//Reduce minimal label of v to0,remove leaves x1and x2,and reduce v’s stem5.l u v l u v lµv,lµv lµv lµv,lµv06.T T x1x27.ReduceOPT I,where the supremum is taken over all instances I of the problem P,A I is the output value of the algorithm A on input I,and OPT I is the optimal value for the instance I.In this section we prove that,unless P=NP,no algorithm can guarantee a factor smaller than2for MBRP with single(inverting or non-inverting)buffer type.On the positive side,we give a factor2εapproximation al-gorithm for MBRP with single non-inverting buffer type,and a factor 4εapproximation algorithm for MBRP with single inverting buffer type.source17(b)623source71317(a)Figure 3:(a)Optimum buffered routing of a 4terminal net with non-Hanan grid edge.(b)Best buffered routing on the Hanan grid.4.1Approximation Complexity of MBRPTheorem 3For any ε0,approximating MBRP within a factor of 2εis NP-hard.Proof.The proof is by reduction from the rectilinear Steiner minimum tree (RSMT)problem,which is NP-hard [10].An RSMT instance con-sists of a set R of terminals and a number K ,and the problem is to decide if terminals in R can be interconnected via a rectilinear Steiner tree of length K or less.Let r be an arbitrary terminal in R and let S R r .Consider the MBRP instance in which all sinks have input capacitance 0,C b 0,C w 1,and C U K .Then,there exists a rectilinear Steiner tree of length at most K for the terminals in R if and only if the above MBRP instance has optimum cost equal to 1,and any 2ε-approximation al-gorithm for MBRP would find the optimum solution if this is the case.Remark.Figure 3gives an example showing that MBRP is inherentlymore difficult than the RSMT problem since,in general,the Steiner points for MBRP do not belong to the Hanan grid,i.e.,to the grid formed by the vertical and horizontal lines passing through terminals.In this ex-ample the input capacitance of each sink and of the buffers is 1,the unit wirelength capacitance C w is 1,and the buffer load upper-bound C U is 8.Any routing along the Hanan grid must use at least 3buffers,while the optimum buffered routing,which uses a non-Hanan edge,has only two buffers.4.2Approximating MBRP with Single Non-Inverting Buffer Type In this section we show that optimal buffering of an approximate rec-tilinear Steiner minimum tree over the terminals (Algorithm 3)comes within a constant factor of the MBRP optimum.Below,the output of a polynomial-time RSMT algorithm with approximation factor of αwill be referred to as an α-approximate Steiner tree .Algorithm 3:Steiner Tree Buffering (STB)1.Find an α-approximate Steiner tree T for r S2.Transform T into a binary tree in which all sinks are leaves by duplicating internal nodes of degree 3and sinks of degree 1and adding zero-length edges between duplicated nodes3.Add buffers to T using the RNB algorithm (Algorithm 1)Theorem 4Algorithm 3approximates the MBRP with single non-inverting buffer type within a factor of 2α1ε,where ε1C UC b(3)Let CAP be the capacitance before buffering of the α-approximateSteiner tree constructed by Algorithm 3.Then CAP s αCAP s ,where s ∑s S c s is the total input capacitance of the sinks.Since s C b ,this gives CAP αCAP α1s αCAP C b C b ,i.e.,CAPC bαCAP C b(4)Let A be the number of stages in the buffering produced by the algorithm.Since T is a binary tree,by Lemma 3every buffer inserted by Algorithm1has a minimum load of C U 2.Thus,CAPA 1C b A C U 2,i.e.,A CAP C b C U 2C b(5)Finally,inequalities (3-5)giveACAPC bC UC bC U C b2Since the rectilinear Steiner tree for a given set of terminals can be approximated in polynomial time to within any desired accuracy using Arora’s PTAS [5],Theorem 4gives:Corollary 1The MBRP with single non-inverting buffer type can be approximated in polynomial time within a factor of 21εfor anyε14We require that C U C b 2since otherwise buffering is impossible.In practice C U C b 2;in our benchmarks the ratio varies between 12and 200,which corresponds to a value of εbetween 0.1and 0.005.Algorithm 4:Steiner Tree Inverting Buffering (STIB)1.Find a buffered routing tree T r V E B using the STB algorithm2.For each b B r ,in the order given by a postorder traversal of T ,do:If b drives only sinks with the same polarity then Replace b by an inverter and add b ’s stage to T Else //b drives both positive and negative sinks Replace b with two inverters b and b such that -the parent of b is b ,and l b b 0-the parent of b is the parent p of b in T and l b p l b p For each σdo:Add to T a Steiner tree rooted at b σand spanning all sinks with polarity σin D bEnd for End if T T D b End for 3.Return TTheorem 5Algorithm 4approximates the MBRP with single invertingbuffer type within a factor of at most 4α1ε,where ε1C U C b 2.B y T h e o r e m 3,n o a p p r o x i m a t i o n a l g o r i t h m w i t h a f a c t o r b e t t e r t h a n2exists for MBRP with single inverting buffer type.Closing the gapbetween Corollary 2and this hardness result is an interesting open prob-lem.Here we note that a practical,if not theoretical,improvement ofAlgorithm 4is to compute the placement of inverters by a polarity-aware version of the RNB algorithm,instead of using the locations of the non-inverting buffers inserted by STB.5MBRP Heuristics with Improved Practical Performance Theorems 3and 4imply that the STB algorithm is essentially the best possible from the point of view of worst case approximation guarantee.In this section we describe two MBRP heuristics which,by changing the topology of the Steiner tree,improve upon the STB algorithm on practical instances.The first heuristic,called Cut&Connect,modifies the Steiner tree constructed by STB in a bottom-up fashion,starting from the sinks and working towards the root.When finding a buffer b whose load is smaller than C U ,the heuristic tries to fill b ’s load up to C U by cutting a subtree from some other part of the tree and re-connecting it to the closest point in T b .Input:Net N with source r and set of sinks S ,sink input capacitances c s ,upper-bound C UOutput:Buffered routing tree T r V E B for N such that c D b C U for every b r BInput:Net N with source r and set of sinks S ,sink input capacitances c s ,upper-bound C U Output:Buffered routing tree T r V E B for N such that c D bC U forevery b r B load c T v ;S T v S ;T T T vq =sink in S S closest to S ;p sink of S closest to q While subtreeload subtreeload C w from p ,towards qB B b ;S S S bT =Steiner tree for S r ,rooted at r End while4.Return T T ,with buffer set B6Experimental ResultsWe have implemented the RNB and RNIB algorithms for optimally buffering a given tree with a single non-inverting,respectively invert-ing,buffer type,as well as the Cut&Connect and Clustering heuristics for MBRP with single non-inverting buffer type.Table1gives the num-ber of buffers inserted by the four algorithms on datasets extracted from recent industrial designs.In these experiments,all algorithms start with the minimum spanning tree over given terminals.For comparison,Table 1includes the lower bound(3)on the optimum number of buffers.6 The results show that the Clustering heuristicfinds consistently bet-ter solutions than the Cut&Connect heuristic,which in turn is consis-tently better than the STB algorithm.The Clustering heuristic comes closest to the computed lower bound,especially for large values of C U, i.e,when few buffers are inserted.The seemingly larger room for im-provement for the larger nets may be caused by the inaccuracy of the lower bound.The Cut&Connect and Clustering heuristics modify the tree in order to decrease the number of buffers,this results in a small wirelength increase(1-2%)compared to the length of the initial MST.The RNIB results show that,for afixed routing tree,the number of buffers that need to be inserted in order to enforce polarity constraints is20–100%larger than the number of buffers needed without polarity constraints(the increase in buffer area depends on the relative size of inverting vs.non-inverting buffers with the same driving strength).We are currently exploring practical heuristics based on the STIB algorithm to reduce the number of inserted inverters by simultaneous routing and buffering.7Conclusions and Future ResearchIn this paper we have addressed a minimum-buffered routing problem which asks for bounded input rise/fall time for all buffers and sinks.We have analyzed the approximation complexity of this problem and given provably-good algorithms for buffering with a single inverting or non-inverting buffer type.We have also proposed local-improvement and clustering heuristics with improved practical performance;experiments conducted on industrial datasets show that our heuristics are efficient and insert a near-optimum number of buffers.Our ongoing research addresses(i)multi-source formulations,in which the buffer solution should be legal for multiple rooted orientations of the tree,and(ii)multi-constraint formulations,in which,e.g.,input capacitance and fanout must be upper-bounded simultaneously.We have already obtained encouraging preliminary results for these extensions. References[1] C.Alpert and A.Devgan.Wire segmenting for improved bufferinsertion.In ACM/IEEE Design Automation Conference,pages 588–593,1997.[2] C.Alpert,A.Devgan,and S.T.Quay.Buffer insertion for noiseand delay optimization.IEEE Transactions on Computer-Aided Design,18:1633–1645,1999.[3] C.Alpert,A.B.Kahng,B.Liu,I.M˘a ndoiu,and A.Zelikovsky.Minimum-buffered routing of non-critical nets for slew rate and reliability control.Technical Report CS2001-0681,Department of Computer Science and Engineering,University of California at San Diego,La Jolla,CA,2001.[4] C.J.Alpert,R.G.Gandham,J.L.Neves,and S.T.Quay.Bufferlibrary selection.In IEEE International Conference on Computer Design,pages221–226,2000.Benchmark MST+RNB MST+Cut&Conn.MST+Cluster MST+RNIB#terminals C U#b runtime#b runtime170.81160.9415330100080.82110.8240.8130.812330400010.8240.8300.8100.78032332.05340.97220.96160.96830100080.978 1.06630.9630.96830400010.9710.88049561.02513.2751.08261.4319001000121.3611131.016 1.1811 1.07190040002 1.0120.94162644.93741.07561.18321.4324001000151.7314171.068 1.4515 1.18240040004 1.073 1.07213410.391281471.15671.991231.25 2600100030313.02331.1431.24161.92260040008 1.157 1.3961842442.63222106.832073.05 12000100011311.54425221.25562.63553.06 1200040002813.329125.82132.63119713051172.714184.391125.165630.36220001000298257.992823304.392975.1115995.40220004000687260.33804.39591729890.018066.5937458.556967.76 340001000138171208.791916.5892147.621797.74 3400040004249.2533456.57Table1:Number of buffers inserted and runtime of the four heuristics on eight industrial datasets.For all four heuristics,the initial tree is a mini mum spanning tree over the terminals.The runtime is in CPU seconds on a SUN Ultra60and includes the time for computing the initial minimum spanning tree.The lower bound has been calculated according to(3)with RSMT length estimated using the BI1S heuristic[12].For all datasets,C w0177f Fµm and C b375f F;sink input capacitances varies between204f F and200f F.。
