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ADUM1401ARW 4通道数字隔离器

Quad-Channel Digital Isolators

ADuM1400/ADuM1401/ADuM1402 Rev.B

nformation furnished by Analog Devices is believed to be accurate and reliable.

However, no responsibility is assumed by Analog Devices for its use, nor for any

infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: https://www.doczj.com/doc/6713596259.html, Fax: 781.326.8703? 2004 Analog Devices, Inc. All rights reserved.

FEATURES

Low power operation

5 V operation

1.0 mA per channel max @ 0 Mbps to 2 Mbps

3.5 mA per channel max @ 10 Mbps

31 mA per channel max @ 90 Mbps

3 V operation

0.7 mA per channel max @ 0 Mbps to 2 Mbps

2.1 mA per channel max @ 10 Mbps

20 mA per channel max @ 90 Mbps

Bidirectional communication

3 V/5 V level translation

High temperature operation: 105°C

High data rate: dc to 90 Mbps (NRZ)

Precise timing characteristics

2 ns max pulse-width distortion

2 ns max channel-to-channel matching

High common-mode transient immunity: >25 kV/μs Output enable function

Wide body 16-lead SOIC package, Pb-free models available Safety and regulatory approvals

UL recognition: 2500 V rms for 1 minute per UL 1577 CSA component acceptance notice #5A

VDE certificate of conformity

DIN EN 60747-5-2 (VDE 0884 Part 2): 2003-01

DIN EN 60950 (VDE 0805): 2001-12; EN 60950: 2000

V IORM = 560 V peak

APPLICATIONS

General-purpose multichannel isolation

SPI? interface/data converter isolation

RS-232/RS-422/RS-485 transceiver

Industrial field bus isolation GENERAL DESCRIPTION

The ADuM140x are 4-channel digital isolators based on Analog Devices’ i Coupler? technology. Combining high speed CMOS and monolithic air core transformer technology, these isolation components provide outstanding performance characteristics superior to alternatives such as optocoupler devices.

By avoiding the use of LEDs and photodiodes, i Coupler devices remove the design difficulties commonly associated with optocouplers. The typical optocoupler concerns regarding uncertain current transfer ratios, nonlinear transfer functions, and temperature and lifetime effects are eliminated with the simple i Coupler digital interfaces and stable performance characteristics. The need for external drivers and other discretes is eliminated with these i Coupler products. Furthermore,

i Coupler devices consumes one-tenth to one-sixth the power of optocouplers at comparable signal data rates.

The ADuM140x isolators provide four independent isolation channels in a variety of channel configurations and data rates (see the Ordering Guide). All models operate with the supply voltage on either side ranging from 2.7 V to 5.5 V, providing compatibility with lower voltage systems as well as enabling a voltage translation functionality across the isolation barrier. In addition, the ADuM140x provides low pulse-width distortion (<2 ns for CRW grade) and tight channel-to-channel matching (<2 ns for CRW grade). Unlike other optocoupler alternatives, the ADuM140x isolators have a patented refresh feature that ensures dc correctness in the absence of input logic transitions and during power-up/power-down conditions.

FUNCTIONAL BLOCK DIAGRAMS

V GND

V GND V DD2 GND2

V OA

V OB

V OC

V OD

V E2

GND2

Figure 1. ADuM1400 Functional Block Diagram

GND

V DD2

GND2

V OA

V OB

V OC

V ID

V E2

GND2

Figure 2. ADuM1401 Functional Block Diagram

GND

V DD2

GND2

V OA

V OB

V IC

V ID

V E2

GND2

Figure 3. ADuM1402 Functional Block Diagram

ADuM1400/ADuM1401/ADuM1402

Rev. B | Page 2 of 24

TABLE OF CONTENTS

Specifications.....................................................................................3 Electrical Characteristics—5 V Operation................................3 Electrical Characteristics—3 V Operation................................6 Electrical Characteristics—Mixed 5 V/3 V or 3 V/5 V

Operation.......................................................................................8 Package Characteristics.............................................................12 Regulatory Information.............................................................12 Insulation and Safety-Related Specifications..........................12 DIN EN 60747-5-2 (VDE 0884 Part 2) Insulation

Characteristics............................................................................13 Recommended Operating Conditions....................................13 Absolute Maximum Ratings..........................................................14 ESD Caution................................................................................14 Pin Configurations and Pin Function Descriptions..................15 Typical Performance Characteristics...........................................17 Application Information................................................................19 PC Board Layout........................................................................19 Propagation Delay-Related Parameters...................................19 DC Correctness and Magnetic Field Immunity...........................19 Power Consumption..................................................................20 Outline Dimensions.......................................................................21 Ordering Guide.. (21)

REVISION HISTORY

6/04—Data Sheet Changed from Rev. A to Rev. B.

Changes to Format.............................................................Universal Changes to Features..........................................................................1 Changes to Electrical Characteristics—5 V Operation...............3 Changes to Electrical Characteristics—3 V Operation...............5 Changes to Electrical Characteristics—Mixed 5 V/3 V or

3 V/5 V Operation............................................................................7 Changes to DIN EN 60747-5-2 (VDE 088

4 Part 2)

Insulation Characteristics Title.....................................................11 Changes to the Ordering Guide. (19)

5/04—Data Sheet Changed from Rev. 0 to Rev. A.

Updated Format..................................................................Universal Changes to the Features...................................................................1 Changes to Table 7 and Table 8.....................................................14 Changes to Table 9..........................................................................15 Changes to the DC Correctness and Magnetic Field Immunity Section..............................................................................................20 Changes to the Power Consumption Section.............................21 Changes to the Ordering Guide....................................................22 9/03—Revision 0: Initial Version.

ADuM1400/ADuM1401/ADuM1402

Rev. B | Page 3 of 24

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS—5 V OPERATION 1

4.5 V ≤ V DD1 ≤

5.5 V , 4.5 V ≤ V DD2 ≤ 5.5 V; all min/max specifications apply over the entire recommended operation range, unless other-wise noted; all typical specifications are at T A = 25°C, V DD1 = V DD2 = 5 V . Table 1.

Parameter Symbol Min Typ Max Unit Test Conditions DC SPECIFICATIONS Input Supply Current, per Channel, Quiescent I DDI (Q) 0.50 0.53 mA Output Supply Current, per Channel, Quiescent I DDO (Q) 0.19 0.21 mA

ADuM1400, Total Supply Current, Four Channels 2

DC to 2 Mbps V DD1 Supply Current I DD1 (Q) 2.2 2.8 mA DC to 1 MHz logic signal freq. V DD2 Supply Current I DD2 (Q) 0.9 1.4 mA DC to 1 MHz logic signal freq. 10 Mbps (BRW and CRW Grades Only) V DD1 Supply Current I DD1 (10) 8.6 10.6 mA 5 MHz logic signal freq. V DD2 Supply Current I DD2 (10) 2.6 3.5 mA 5 MHz logic signal freq. 90 Mbps (CRW Grade Only) V DD1 Supply Current I DD1 (90) 76 100 mA 45 MHz logic signal freq. V DD2 Supply Current I DD2 (90) 21 25 mA 45 MHz logic signal freq. ADuM1401, Total Supply Current, Four Channels 2 DC to 2 Mbps V DD1 Supply Current I DD1 (Q) 1.8 2.4 mA DC to 1 MHz logic signal freq. V DD2 Supply Current I DD2 (Q) 1.2 1.8 mA DC to 1 MHz logic signal freq. 10 Mbps (BRW and CRW Grades Only) V DD1 Supply Current I DD1 (10) 7.1 9.0 mA 5 MHz logic signal freq. V DD2 Supply Current I DD2 (10) 4.1 5.0 mA 5 MHz logic signal freq. 90 Mbps (CRW Grade Only) V DD1 Supply Current I DD1 (90) 62 82 mA 45 MHz logic signal freq. V DD2 Supply Current I DD2 (90) 35 43 mA 45 MHz logic signal freq.

ADuM1402, Total Supply Current, Four Channels 2

DC to 2 Mbps V DD1 or V DD2 Supply Current I DD1 (Q), I DD2 (Q) 1.5 2.1 mA DC to 1 MHz logic signal freq. 10 Mbps (BRW and CRW Grades Only) V DD1 or V DD2 Supply Current I DD1 (10), I DD2 (10) 5.6 7.0 mA 5 MHz logic signal freq. 90 Mbps (CRW Grade Only) V DD1 or V DD2 Supply Current I DD1 (90), I DD2 (90) 49 62 mA 45 MHz logic signal freq. For All Models Input Currents I IA , I IB , I IC ,

I ID , I E1, I E2–10 +0.01+10 μA 0 ≤ V IA , V IB , V IC , V ID ≤ V DD1 or V DD2, 0 ≤ V E1, V E2 ≤ V DD1 or V DD2

Logic High Input Threshold

V IH , V EH 2.0 V

Logic Low Input Threshold

V IL , V EL 0.8 V V DD1, V DD2 – 0.1 5.0 V I Ox = –20 μA, V Ix = V IxH Logic High Output Voltages V OAH , V OBH ,

V OCH , V ODH

V DD1,

V DD2 – 0.4

4.8 V I Ox = –4 mA, V Ix = V IxH 0.0 0.1 V I Ox = 20 μA, V Ix = V IxL 0.04 0.1 V I Ox = 400 μA, V Ix = V IxL

Logic Low Output Voltages V OAL , V OBL ,

V OCL , V ODL 0.2 0.4 V I Ox = 4 mA, V Ix = V IxL

ADuM1400/ADuM1401/ADuM1402

Rev. B | Page 4 of 24

Parameter Symbol Min Typ Max Unit Test Conditions SWITCHING SPECIFICATIONS ADuM140xARW

Minimum Pulse Width 3

PW 1000ns C L = 15 pF, CMOS signal levels

Maximum Data Rate 4

1 Mbps C L = 15 pF, CMOS signal levels Propagation Delay 5t PHL , t PLH 50 65 100 ns C L = 15 pF, CMOS signal levels

Pulse-Width Distortion, |t PLH – t PHL |5

PWD 40 ns C L = 15 pF, CMOS signal levels Propagation Delay Skew 6t PSK 50 ns C L = 15 pF, CMOS signal levels

Channel-to-Channel Matching 7

t PSKCD/OD 50 ns C L = 15 pF, CMOS signal levels ADuM140xBRW

Minimum Pulse Width 3

PW 100 ns C L = 15 pF, CMOS signal levels

Maximum Data Rate 4

10 Mbps C L = 15 pF, CMOS signal levels Propagation Delay 5 t PHL , t PLH 20 32 50 ns C L = 15 pF, CMOS signal levels

Pulse-Width Distortion, |t PLH – t PHL |5

PWD 3 ns C L = 15 pF, CMOS signal levels Change vs. Temperature 5 ps/°C C L = 15 pF, CMOS signal levels

Propagation Delay Skew 6

t PSK 15 ns C L = 15 pF, CMOS signal levels

Channel-to-Channel Matching,

Codirectional Channels 7

t PSKCD 3 ns C L = 15 pF, CMOS signal levels Channel-to-Channel Matching,

Opposing-Directional Channels 7

t PSKOD 6 ns C L = 15 pF, CMOS signal levels ADuM140xCRW

Minimum Pulse Width 3

PW 8.3 11.1 ns C L = 15 pF, CMOS signal levels Maximum Data Rate 4 90 120 Mbps C L = 15 pF, CMOS signal levels

Propagation Delay 5

t PHL , t PLH 18 27 32 ns C L = 15 pF, CMOS signal levels Pulse-Width Distortion, |t PLH – t PHL |5 PWD 0.5 2 ns C L = 15 pF, CMOS signal levels Change vs. Temperature 3 ps/°C C L = 15 pF, CMOS signal levels

Propagation Delay Skew 6

t PSK 10 ns C L = 15 pF, CMOS signal levels

Channel-to-Channel Matching,

Codirectional Channels 7

t PSKCD 2 ns C L = 15 pF, CMOS signal levels Channel-to-Channel Matching,

Opposing-Directional Channels 7

t PSKOD 5 ns C L = 15 pF, CMOS signal levels For All Models

Output Disable Propagation Delay

(High/Low-to-High Impedance)

t PHZ , t PLH 6 8 ns C L = 15 pF, CMOS signal levels Output Enable Propagation Delay

(High Impedance to High/Low) t PZH , t PZL 6 8 ns C L = 15 pF, CMOS signal levels Output Rise/Fall Time (10% to 90%) t R /t F 2.5 ns C L = 15 pF, CMOS signal levels

Common-Mode Transient Immunity at Logic High Output 8

|CM H | 25 35 kV/μs V Ix = V DD1/V DD2, V CM = 1000 V,

transient magnitude = 800 V

Common-Mode Transient Immunity at Logic Low Output 8

|CM L | 25 35 kV/μs V Ix = 0 V, V CM = 1000 V,

transient magnitude = 800 V Refresh Rate f r 1.2 Mbps Input Dynamic Supply Current, per Channel 9I DDI (D) 0.19 mA/Mbps

Output Dynamic Supply Current, per Channel 9

I DDO (D) 0.05 mA/Mbps

See Notes on next page.

ADuM1400/ADuM1401/ADuM1402

Rev. B | Page 5 of 24

1 All voltages are relative to their respective ground.

The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load

present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section on Page 20. See through for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See through for total I Figure 8Figure 8 Figure 10Figure 10Figure 11 Figure 14DD1 and I DD2 supply currents as a function of data rate for ADuM1400/ADuM1401/ADuM1402 channel configurations. 3

The minimum pulse width is the shortest pulse width at which the specified pulse-width distortion is guaranteed. 4

The maximum data rate is the fastest data rate at which the specified pulse-width distortion is guaranteed. 5

t PHL propagation delay is measured from the 50% level of the falling edge of the V Ix signal to the 50% level of the falling edge of the V Ox signal. t PLH propagation delay is measured from the 50% level of the rising edge of the V Ix signal to the 50% level of the rising edge of the V Ox signal. 6

t PSK is the magnitude of the worst-case difference in t PHL or t PLH that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. 7

Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier. 8

CM H is the maximum common-mode voltage slew rate that can be sustained while maintaining V O > 0.8 V DD2. CM L is the maximum common-mode voltage slew rate that can be sustained while maintaining V O < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed. 9

Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See through for information on per-channel supply current for unloaded and loaded conditions. See the section on Page 20 for guidance on calculating the per-channel sup-ply current for a given data rate.

Power Consumption

ADuM1400/ADuM1401/ADuM1402

Rev. B | Page 6 of 24

ELECTRICAL CHARACTERISTICS—3 V OPERATION 1

2.7 V ≤ V DD1 ≤

3.6 V , 2.7 V ≤ V DD2 ≤ 3.6 V; all min/max specifications apply over the entire recommended operation range, unless other-wise noted; all typical specifications are at T A = 25°C, V DD1 = V DD2 = 3.0 V . Table 2.

Parameter Symbol Min Typ Max Unit Test Conditions DC SPECIFICATIONS Input Supply Current, per Channel, Quiescent I DDI (Q) 0.26 0.31 mA Output Supply Current, per Channel, Quiescent I DDO (Q) 0.11 0.14 mA

ADuM1400, Total Supply Current, Four Channels 2

DC to 2 Mbps V DD1 Supply Current I DD1 (Q) 1.2 1.9 mA DC to 1 MHz logic signal freq. V DD2 Supply Current I DD2 (Q) 0.5 0.9 mA DC to 1 MHz logic signal freq. 10 Mbps (BRW and CRW Grades Only) V DD1 Supply Current I DD1 (10) 4.5 6.5 mA 5 MHz logic signal freq. V DD2 Supply Current I DD2 (10) 1.4 2.0 mA 5 MHz logic signal freq. 90 Mbps (CRW Grade Only) V DD1 Supply Current I DD1 (90) 42 65 mA 45 MHz logic signal freq. V DD2 Supply Current I DD2 (90) 11 15 mA 45 MHz logic signal freq.

ADuM1401, Total Supply Current, Four Channels 2

DC to 2 Mbps V DD1 Supply Current I DD1 (Q) 1.0 1.6 mA DC to 1 MHz logic signal freq. V DD2 Supply Current I DD2 (Q) 0.7 1.2 mA DC to 1 MHz logic signal freq. 10 Mbps (BRW and CRW Grades Only) V DD1 Supply Current I DD1 (10) 3.7 5.4 mA 5 MHz logic signal freq. V DD2 Supply Current I DD2 (10) 2.2 3.0 mA 5 MHz logic signal freq. 90 Mbps (CRW Grade Only) V DD1 Supply Current I DD1 (90) 34 52 mA 45 MHz logic signal freq. V DD2 Supply Current I DD2 (90) 19 27 mA 45 MHz logic signal freq. ADuM1402, Total Supply Current, Four Channels 2 DC to 2 Mbps V DD1 or V DD2 Supply Current I DD1 (Q), I DD2 (Q) 0.9 1.5 mA DC to 1 MHz logic signal freq. 10 Mbps (BRW and CRW Grades Only) V DD1 or V DD2 Supply Current I DD1 (10), I DD2 (10) 3.0 4.2 mA 5 MHz logic signal freq. 90 Mbps (CRW Grade Only) V DD1 or V DD2 Supply Current I DD1 (90), I DD2 (90) 27 39 mA 45 MHz logic signal freq. For All Models Input Currents I IA , I IB , I IC, I ID , I E1, I E2–10 +0.01+10 μA 0 ≤ V IA , V IB , V IC , V ID ≤ V DD1 or

V DD2, 0 ≤ V E1,V E2 ≤ V DD1 or V DD2

Logic High Input Threshold V IH , V EH 1.6 V

Logic Low Input Threshold

V IL , V EL 0.4 V V DD1, V DD2 – 0.1 3.0 V I Ox = –20 μA, V Ix = V IxH Logic High Output Voltages V OAH , V OBH ,

V OCH , V ODH V DD1, V DD2 – 0.4 2.8 V I Ox = –4 mA, V Ix = V IxH

0.0 0.1 V I Ox = 20 μA, V Ix = V IxL 0.04 0.1 V I Ox = 400 μA, V Ix = V IxL

Logic Low Output Voltages V OAL , V OBL ,

V OCL , V ODL 0.2 0.4 V I Ox = 4 mA, V Ix = V IxL

SWITCHING SPECIFICATIONS ADuM140xARW

Minimum Pulse Width 3

PW 1000ns C L = 15 pF, CMOS signal levels Maximum Data Rate 4 1 Mbps C L = 15 pF, CMOS signal levels

Propagation Delay 5

t PHL , t PLH 50 75 100 ns C L = 15 pF, CMOS signal levels Pulse-Width Distortion, |t PLH – t PHL |5 PWD 40 ns C L = 15 pF, CMOS signal levels

Propagation Delay Skew 6

t PSK 50 ns C L = 15 pF, CMOS signal levels Channel-to-Channel Matching 7t PSKCD/OD 50 ns C L = 15 pF, CMOS signal levels

ADuM1400/ADuM1401/ADuM1402

Rev. B | Page 7 of 24

Parameter Symbol Min Typ Max Unit Test Conditions ADuM140xBRW Minimum Pulse Width 3 PW 100 ns C L = 15 pF, CMOS signal levels

Maximum Data Rate 4

10 Mbps C L = 15 pF, CMOS signal levels

Propagation Delay 5

t PHL , t PLH 20 38 50 ns C L = 15 pF, CMOS signal levels Pulse-Width Distortion, |t PLH – t PHL |5 PWD 3 ns C L = 15 pF, CMOS signal levels Change vs. Temperature 5 ps/°C C L = 15 pF, CMOS signal levels Propagation Delay Skew 6 t PSK 22 ns C L = 15 pF, CMOS signal levels

Channel-to-Channel Matching,

Codirectional Channels 7

t PSKCD 3 ns C L = 15 pF, CMOS signal levels Channel-to-Channel Matching,

Opposing-Directional Channels 7

t PSKOD 6 ns C L = 15 pF, CMOS signal levels ADuM140xCRW Minimum Pulse Width 3 PW 8.3 11.1 ns C L = 15 pF, CMOS signal levels

Maximum Data Rate 4

90 120 Mbps C L = 15 pF, CMOS signal levels Propagation Delay 5 t PHL , t PLH 20 34 45 ns C L = 15 pF, CMOS signal levels

Pulse-Width Distortion, |t PLH – t PHL |5

PWD 0.5 2 ns C L = 15 pF, CMOS signal levels Change vs. Temperature 3 ps/°C C L = 15 pF, CMOS signal levels

Propagation Delay Skew 6

t PSK 16 ns C L = 15 pF, CMOS signal levels

Channel-to-Channel Matching,

Codirectional Channels 7

t PSKCD 2 ns C L = 15 pF, CMOS signal levels Channel-to-Channel Matching,

Opposing-Directional Channels 7 t PSKOD 5 ns C L = 15 pF, CMOS signal levels For All Models

Output Disable Propagation Delay

(High/Low-to-High Impedance)

t PHZ , t PLH 6 8 ns C L = 15 pF, CMOS signal levels Output Enable Propagation Delay

(High Impedance to High/Low) t PZH , t PZL 6 8 ns C L = 15 pF, CMOS signal levels Output Rise/Fall Time (10% to 90%) t R /t F 3 ns C L = 15 pF, CMOS signal levels

Common-Mode Transient Immunity at Logic High Output 8

|CM H | 25 35 kV/μs V Ix = V DD1/V DD2, V CM = 1000 V,

transient magnitude = 800 V

Common-Mode Transient Immunity at Logic Low Output 8

|CM L | 25 35 kV/μs V Ix = 0 V, V CM = 1000 V,

transient magnitude = 800 V Refresh Rate f r 1.1 Mbps

Input Dynamic Supply Current, per Channel 9

I DDI (D) 0.10 mA/Mbps Output Dynamic Supply Current, per Channel 9 I DDO (D) 0.03 mA/Mbps

1 All voltages are relative to their respective ground.

The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load

The minimum pulse width is the shortest pulse width at which the specified pulse-width distortion is guaranteed. 4

The maximum data rate is the fastest data rate at which the specified pulse-width distortion is guaranteed. 5

Power Consumption

ADuM1400/ADuM1401/ADuM1402

Rev. B | Page 8 of 24

ELECTRICAL CHARACTERISTICS—MIXED 5 V/3 V OR 3 V/5 V OPERATION 1

5 V/3 V operation: 4.5 V ≤ V DD1 ≤ 5.5 V , 2.7 V ≤ V DD2 ≤ 3.

6 V; 3 V/5 V operation: 2.

7 V ≤ V DD1 ≤ 3.6 V , 4.5 V ≤ V DD2 ≤ 5.5 V; all min/max specifications apply over the entire recommended operation range, unless otherwise noted; all typical specifications are at T A = 25°C; V DD1 = 3.0 V , V DD2 = 5 V; or V DD1 = 5 V , V DD2 = 3.0 V . Table 3.

Parameter Symbol Min Typ Max Unit Test Conditions DC SPECIFICATIONS Input Supply Current, per Channel, Quiescent I DDI (Q) 5 V/3 V Operation 0.50 0.53 mA 3 V/5 V Operation 0.26 0.31 mA Output Supply Current, per Channel, Quiescent I DDO (Q) 5 V/3 V Operation 0.11 0.14 mA 3 V/5 V Operation 0.19 0.21 mA

ADuM1400, Total Supply Current, Four Channels 2

DC to 2 Mbps V DD1 Supply Current I DD1 (Q) 5 V/3 V Operation 2.2 2.8 mA DC to 1 MHz logic signal freq. 3 V/5 V Operation 1.2 1.9 mA DC to 1 MHz logic signal freq. V DD2 Supply Current I DD2 (Q) 5 V/3 V Operation 0.5 0.9 mA DC to 1 MHz logic signal freq. 3 V/5 V Operation 0.9 1.4 mA DC to 1 MHz logic signal freq. 10 Mbps (BRW and CRW Grades Only) V DD1 Supply Current I DD1 (10) 5 V/3 V Operation 8.6 10.6 mA 5 MHz logic signal freq. 3 V/5 V Operation 4.5 6.5 mA 5 MHz logic signal freq. V DD2 Supply Current I DD2 (10) 5 V/3 V Operation 1.4 2.0 mA 5 MHz logic signal freq. 3 V/5 V Operation 2.6 3.5 mA 5 MHz logic signal freq. 90 Mbps (CRW Grade Only) V DD1 Supply Current I DD1 (90) 5 V/3 V Operation 76 100 mA 45 MHz logic signal freq. 3 V/5 V Operation 42 65 mA 45 MHz logic signal freq. V DD2 Supply Current I DD2 (90) 5 V/3 V Operation 11 15 mA 45 MHz logic signal freq. 3 V/5 V Operation 21 25 mA 45 MHz logic signal freq. ADuM1401, Total Supply Current, Four Channels 2 DC to 2 Mbps V DD1 Supply Current I DD1 (Q) 5 V/3 V Operation 1.8 2.4 mA DC to 1 MHz logic signal freq. 3 V/5 V Operation 1.0 1.6 mA DC to 1 MHz logic signal freq. V DD2 Supply Current I DD2 (Q) 5 V/3 V Operation 0.7 1.2 mA DC to 1 MHz logic signal freq. 3 V/5 V Operation 1.2 1.8 mA DC to 1 MHz logic signal freq. 10 Mbps (BRW and CRW Grades Only) V DD1 Supply Current I DD1 (10) 5 V/3 V Operation 7.1 9.0 mA 5 MHz logic signal freq. 3 V/5 V Operation 3.7 5.4 mA 5 MHz logic signal freq. V DD2 Supply Current I DD2 (10) 5 V/3 V Operation 2.2 3.0 mA 5 MHz logic signal freq. 3 V/5 V Operation 4.1 5.0 mA 5 MHz logic signal freq.

ADuM1400/ADuM1401/ADuM1402

Rev. B | Page 9 of 24

Parameter Symbol Min Typ Max Unit Test Conditions

90 Mbps (CRW Grade Only) V DD1 Supply Current I DD1 (90) 5 V/3 V Operation 62 82 mA 45 MHz logic signal freq. 3 V/5 V Operation 34 52 mA 45 MHz logic signal freq. V DD2 Supply Current I DD2 (90) 5 V/3 V Operation 19 27 mA 45 MHz logic signal freq. 3 V/5 V Operation 35 43 mA 45 MHz logic signal freq.

ADuM1402, Total Supply Current, Four Channels 2

DC to 2 Mbps V DD1 Supply Current I DD1 (Q) 5 V/3 V Operation 1.5 2.1 mA DC to 1 MHz logic signal freq. 3 V/5 V Operation 0.9 1.5 mA DC to 1 MHz logic signal freq. V DD2 Supply Current I DD2 (Q) 5 V/3 V Operation 0.9 1.5 mA DC to 1 MHz logic signal freq. 3 V/5 V Operation 1.5 2.1 mA DC to 1 MHz logic signal freq. 10 Mbps (BRW and CRW Grades Only) V DD1 Supply Current I DD1 (10) 5 V/3 V Operation 5.6 7.0 mA 5 MHz logic signal freq. 3 V/5 V Operation 3.0 4.2 mA 5 MHz logic signal freq. V DD2 Supply Current I DD2 (10) 5 V/3 V Operation 3.0 4.2 mA 5 MHz logic signal freq. 3 V/5 V Operation 5.6 7.0 mA 5 MHz logic signal freq. 90 Mbps (CRW Grade Only) V DD1 Supply Current I DD1 (90) 5 V/3 V Operation 49 62 mA 45 MHz logic signal freq. 3 V/5 V Operation 27 39 mA 45 MHz logic signal freq. V DD2 Supply Current I DD2 (90) 5 V/3 V Operation 27 39 mA 45 MHz logic signal freq. 3 V/5 V Operation 49 62 mA 45 MHz logic signal freq. For All Models Input Currents I IA , I IB , I IC , I ID , I E1, I E2–10 +0.01 +10 μA 0 ≤ V IA ,V IB , V IC ,V ID ≤ V DD1 or

V DD2, 0 ≤ V E1,V E2 ≤ V DD1 or V DD2

Logic High Input Threshold V IH , V EH 5 V/3 V Operation 2.0 V 3 V/5 V Operation 1.6 V

Logic Low Input Threshold

V IL , V EL 5 V/3 V Operation 0.8 V 3 V/5 V Operation 0.4 V V DD1/ V DD2 – 0.1

V DD1/V DD2 V I Ox = –20 μA, V Ix = V IxH Logic High Output Voltages V OAH , V OBH ,

V OCH , V ODH V DD1/ V DD2 – 0.4 V DD1/

V DD2 – 0.2

V I Ox = –4 mA, V Ix = V IxH 0.0 0.1 V I Ox = 20 μA, V Ix = V IxL 0.04 0.1 V I Ox = 400 μA, V Ix = V IxL

Logic Low Output Voltages V OAL, V OBL,

V OCL , V ODL 0.2 0.4 V I Ox = 4 mA, V Ix = V IxL

SWITCHING SPECIFICATIONS ADuM140xARW Minimum Pulse Width 3PW 1000ns C L = 15 pF, CMOS signal levels

Maximum Data Rate 4

1 Mbps C L = 15 pF, CMOS signal levels

Propagation Delay 5

t PHL , t PLH 50 70 100 ns C L = 15 pF, CMOS signal levels Pulse-Width Distortion, |t PLH – t PHL |5 PWD 40 ns C L = 15 pF, CMOS signal levels

Propagation Delay Skew 6

t PSK 50 ns C L = 15 pF, CMOS signal levels Channel-to-Channel Matching 7t PSKCD/OD 50 ns C L = 15 pF, CMOS signal levels

ADuM1400/ADuM1401/ADuM1402

Rev. B | Page 10 of 24

Parameter Symbol Min Typ Max Unit Test Conditions ADuM140xBRW Minimum Pulse Width 3PW 100 ns C L = 15 pF,CMOS signal levels

Maximum Data Rate 4

10 Mbps C L = 15 pF, CMOS signal levels

Propagation Delay 5

t PHL , t PLH 15 35 50 ns C L = 15 pF, CMOS signal levels Pulse-Width Distortion, |t PLH – t PHL |5 PWD 3 ns C L = 15 pF, CMOS signal levels Change vs. Temperature 5 ps/°C C L = 15 pF, CMOS signal levels Propagation Delay Skew 6t PSK 22 ns C L = 15 pF, CMOS signal levels

Channel-to-Channel Matching,

Codirectional Channels 7

t PSKCD 3 ns C L = 15 pF, CMOS signal levels Channel-to-Channel Matching,

Opposing-Directional Channels 7

t PSKOD 6 ns C L = 15 pF, CMOS signal levels ADuM140xCRW Minimum Pulse Width 3 PW 8.3 11.1 ns Maximum Data Rate 4

90 120 Mbps

C L = 15 pF, CMOS signal levels

C L = 15 pF, CMOS signal levels Propagation Delay 5 t PHL , t PLH 20 30 40 ns C L = 15 pF, CMOS signal levels

Pulse-Width Distortion, |t PLH – t PHL |5

PWD 0.5 2 ns C L = 15 pF, CMOS signal levels Change vs. Temperature 3 ps/°C C L = 15 pF, CMOS signal levels

Propagation Delay Skew 6

t PSK 14 ns C L = 15 pF, CMOS signal levels

Channel-to-Channel Matching,

Codirectional Channels 7

t PSKCD 2 ns C L = 15 pF, CMOS signal levels Channel-to-Channel Matching,

Opposing-Directional Channels 7 t PSKOD 5 ns C L = 15 pF, CMOS signal levels For All Models

Output Disable Propagation Delay

(High/Low to High Impedance)

t PHZ , t PLH 6 8 ns C L = 15 pF, CMOS signal levels Output Enable Propagation Delay

(High Impedance to High/Low) t PZH , t PZL 6 8 ns C L = 15 pF, CMOS signal levels Output Rise/Fall Time (10% to 90%) t R /t f C L = 15 pF, CMOS signal levels 5 V/3 V Operation 3.0 ns 3 V/5 V Operation 2.5 ns

Common-Mode Transient Immunity at Logic High Output 8

|CM H | 25 35 kV/μs V Ix = V DD1/V DD2, V CM = 1000 V,

transient magnitude = 800 V

Common-Mode Transient Immunity at Logic Low Output 8

|CM L | 25 35 kV/μs V Ix = 0 V, V CM = 1000 V,

transient magnitude = 800 V Refresh Rate f r 5 V/3 V Operation 1.2 Mbps 3 V/5 V Operation 1.1 Mbps

Input Dynamic Supply Current, per Channel 9

I DDI (D) 5 V/3 V Operation 0.19 mA/Mbps 3 V/5 V Operation 0.10 mA/Mbps

Output Dynamic Supply Current, per Channel 9

I DDI (D) 5 V/3 V Operation 0.03 mA/Mbps 3 V/5 V Operation 0.05 mA/Mbps

See Notes on next page.

ADuM1400/ADuM1401/ADuM1402

1 All voltages are relative to their respective ground.

2 The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section on Page 20. See Figure 8 through Figure 10 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 11 through Figure 14 for total I DD1 and

I DD2 supply currents as a function of data rate for ADuM1400/ADuM1401/ADuM1402 channel configurations.

3 The minimum pulse width is the shortest pulse width at which the specified pulse-width distortion is guaranteed.

4 The maximum data rate is the fastest data rate at which the specified pulse-width distortion is guaranteed.

5 t PHL propagation delay is measured from the 50% level of the falling edge of the V Ix signal to the 50% level of the falling edge of the V Ox signal. t PLH propagation delay is measured from the 50% level of the rising edge of the V Ix signal to the 50% level of the rising edge of the V Ox signal.

6 t PSK is the magnitude of the worst-case difference in t PHL or t PLH that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions.

7 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier.

8 CM H is the maximum common-mode voltage slew rate that can be sustained while maintaining V O > 0.8 V DD2. CM L is the maximum common-mode voltage slew rate that can be sustained while maintaining V O < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed.

9 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 8 through Figure 10 for information on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section on Page 20 for guidance on calculating the per-channel supply current for a given data rate.

Rev. B | Page 11 of 24

ADuM1400/ADuM1401/ADuM1402

Rev. B | Page 12 of 24

PACKAGE CHARACTERISTICS

Table 4.

Parameter Symbol Min Typ Max Unit Test Conditions

Resistance (Input-Output)1R I-O 1012

? Capacitance (Input-Output)1 C I-O 2.2 pF f = 1 MHz

Input Capacitance 2

C I 4.0 p F IC Junction-to-Case Thermal Resistance, Side 1 θJCI 33 °C/W IC Junction-to-Case Thermal Resistance, Side 2 θJCO 28 °C/W

Thermocouple located

at center of package underside

1 Device considered a 2-terminal device; Pins 1, 2, 3, 4, 5, 6, 7, and 8 shorted together and Pins 9, 10, 11, 12, 13, 14, 15, and 16 shorted together. 2

Input capacitance is from any input data pin to ground.

REGULATORY INFORMATION

The ADuM140x have been approved by the organizations listed in Table 5. Table 5.

UL 1

CSA VDE 2Recognized under 1577

component recognition program 1

Double insulation, 2500 V rms isolation voltage

File E214100

Approved under CSA Component Acceptance Notice #5A Reinforced insulation per

CSA 60950-1-03 and IEC 60950-1, 400 V rms maximum working voltage File 205078 Certified according to DIN EN 60747-5-2 (VDE 0884 Part 2): 2003-012

Basic insulation, 560 V peak

Complies with DIN EN 60747-5-2 (VDE 0884 Part 2): 2003-01, DIN EN 60950 (VDE 0805): 2001-12; EN 60950:2000

Reinforced insulation, 560 V peak File 2471900-4880-0001

1 In accordance with UL1577, each ADuM140x is proof tested by applying an insulation test voltage ≥ 3000 V rms for 1 second (current leakage detection limit = 5 μA).

In accordance with DIN EN 60747-5-2, each ADuM140x is proof tested by applying an insulation test voltage ≥ 1050 V peak for 1 second (partial discharge detection limit = 5 pC). A “*” mark branded on the component designates DIN EN 60747-5-2 approval.

INSULATION AND SAFETY-RELATED SPECIFICATIONS

Table 6.

Parameter Symbol Value Unit Conditions Rated Dielectric Insulation Voltage 2500 V rms 1 minute duration Minimum External Air Gap (Clearance) L(I01) 8.40 min mm Measured from input terminals to output terminals,

shortest distance through air

Minimum External Tracking (Creepage) L(I02) 8.10 min mm Measured from input terminals to output terminals,

shortest distance path along body

Minimum Internal Gap (Internal Clearance) 0.017 min mm Insulation distance through insulation Tracking Resistance (Comparative Tracking Index) CTI >175 V DIN IEC 112/VDE 0303 Part 1 Isolation Group IIIa Material Group (DIN VDE 0110, 1/89, Table 1)

ADuM1400/ADuM1401/ADuM1402

Rev. B | Page 13 of 24

DIN EN 60747-5-2 (VDE 0884 PART 2) INSULATION CHARACTERISTICS

Table 7.

Description Symbol Characteristic Unit

Installation Classification per DIN VDE 0110

For Rated Mains Voltage ≤ 150 V rms

For Rated Mains Voltage ≤ 300 V rms

For Rated Mains Voltage ≤ 400 V rms

I–IV I–III I–II Climatic Classification 40/105/21 Pollution Degree (DIN VDE 0110, Table 1) 2 Maximum Working Insulation Voltage V IORM 560 V peak Input to Output Test Voltage, Method b1 V IORM × 1.875 = V PR , 100% Production Test, t m = 1 sec, Partial Discharge < 5 pC V PR

1050 V peak Input to Output Test Voltage, Method a After Environmental Tests Subgroup 1

V IORM × 1.6 = V PR , t m = 60 sec, Partial Discharge < 5 pC

After Input and/or Safety Test Subgroup 2/3 V IORM × 1.2 = V PR , t m = 60 sec, Partial Discharge < 5 pC

V PR

896

672 V peak V peak Highest Allowable Overvoltage (Transient Overvoltage, t TR = 10 sec) V TR 4000 V peak

Safety-Limiting Values (Maximum value allowed in the event of a failure; also see Thermal Derating Curve, Figure 4) Case Temperature Side 1 Current Side 2 Current T S I S1

I S2

150

265 335 °C mA mA Insulation Resistance at T S , V IO = 500 V R S >109

This isolator is suitable for basic electrical isolation only within the safety limit data. Maintenance of the safety data is ensured by protec-tive circuits.

The * marking on packages denotes DIN EN 60747-5-2 approval for 560 V peak working voltage.

CASE TEMPERATURE (°C)

S A F E T Y -L I M I T I N G C U R R E N T (m A )

350300250200150

1005050

100150

200

SIDE #1

SIDE #2

03787-0-003

Figure 4. Thermal Derating Curve, Dependence of Safety Limiting Values

with Case Temperature per DIN EN 60747-5-2

RECOMMENDED OPERATING CONDITIONS

Table 8.

Parameter Symbol Min Max Unit

Operating Temperature T A –40 +105 °C Supply Voltages 1V DD1, V DD 2 2.7 5.5 V Input Signal Rise and Fall Times 1.0 ms

All voltages are relative to their respective ground.

See the DC Correctness and Magnetic Field Immunity section on Page 19 for information on immunity to external magnetic fields.

ADuM1400/ADuM1401/ADuM1402

Rev. B | Page 14 of 24

ABSOLUTE MAXIMUM RATINGS

Ambient temperature = 25°C, unless otherwise noted. Table 9.

Parameter Symbol Min Max Unit Storage Temperature T ST –65 +150 °C Ambient Operating Temperature T A –40 +105 °C

Supply Voltages 1

V DD1, V DD2–0.5 +7.0 V Input Voltage 1, 2V IA , V IB , V IC , V ID , V E1,V E2–0.5 V DDI + 0.5 V

Output Voltage 1, 2

V OA , V OB , V OC , V OD –0.5 V DDO + 0.5 V Average Output Current, Per Pin 3 Side 1 I O1

–18 +18 mA Side 2 I O2–22 +22 mA Common-Mode Transients 4 –100 +100 kV/μs

1 All voltages are relative to their respective ground.

V DDI and V DDO refer to the supply voltages on the input and output sides of a given channel, respectively. See the section. PC Board Layout 3

See for maximum rated current values for various temperatures. Figure 44

Refers to common-mode transients across the insulation barrier. Common-mode transients exceeding the Absolute Maximum Rating may cause latch-up or perma-nent damage.

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions may affect device reliability.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Table 10. Truth Table (Positive Logic)

V IX Input 1V EX Input 2V DDI State 1 V DDO State 1 V OX Output 1 Notes H H or NC Powered Powered H L H or NC Powered Powered L X L Powered Powered Z X

H or NC

Unpowered Powered H Outputs return to the input state within 1 μs of V DDI power

restoration.

X L Unpowered Powered Z X X Powered Unpowered Indeterminate Outputs return to the input state within 1 μs of V DDO power

restoration if V EX state is H or NC. Outputs returns to high impedance state within 8 ns of V DDO power restoration if V EX state is L.

V IX and V OX refer to the input and output signals of a given channel (A, B, C, or D). V EX refers to the output enable signal on the same side as the V OX outputs. V DDI and V DDO refer to the supply voltages on the input and output sides of the given channel, respectively. 2

In noisy environments, connecting V EX to an external logic high or low is recommended.

ADuM1400/ADuM1401/ADuM1402

Rev. B | Page 15 of 24

PIN CONFIGURATIONS AND PIN FUNCTION DESCRIPTIONS

NC = NO CONNECT

03786-0-005

V DD1*GND 1V IA V IB V IC V ID NC *GND 1DD22*

OA OB

OC OD E22*

Figure 5. ADuM1400 Pin Configuration

03786-0-006

V DD1*GND 1V IA V IB V IC V OD V E1*GND 1DD22*

OA OB

OC ID E22*

Figure 6. ADuM1401 Pin Configuration

03786-0-007

V DD1*GND 1V IA V IB V OC V OD V E1*GND 1DD2

OA OB IC ID E2

Figure 7. ADuM1402 Pin Configuration

* Pins 2 and 8 are internally connected. Connecting both to GND 1 is recommended. Pins 9 and 15 are internally connected. Connecting both to GND 2 is recommended. Output enable Pin 10 on the ADuM1400 may be left disconnected if outputs are to be always enabled. Output enable Pins 7 and 10 on the ADuM1401/ADuM1402 may be left disconnected if outputs are to be always enabled. In noisy environments, connecting Pin 7 (for ADuM1401 and ADuM1402) and Pin 10 (for all models) to an external logic high or low is recommended.

Table 11. ADuM1400 Pin Function Descriptions

No. Mnemonic Function 1 V DD1Supply Voltage for Isolator Side 1, 2.7 V to 5.5 V. 2 GND 1Ground 1. Ground reference for isolator Side 1. 3 V IA Logic Input A. 4 V IB Logic Input B. 5 V IC Logic Input C. 6 V ID Logic Input D. 7 NC No Connect. 8 GND 1Ground 1. Ground reference for isolator Side 1. 9 GND 2Ground 2. Ground reference for isolator Side 2. 10 V E2Output Enable 2. Active high logic input. V OA , V OB , V OC , and V OD outputs are enabled when V E2 is high or disconnected. V OA , V OB , V OC , and

V OD outputs are disabled when V E2 is low. In noisy environments, connecting V E2 to an external logic high or low is recommended.

11 V OD Logic Output D. 12 V OC Logic Output C. 13 V OB Logic Output B. 14 V OA Logic Output A. 15 GND 2Ground 2. Ground reference for isolator Side 2. 16 V DD2Supply Voltage for Isolator Side 2, 2.7 V to 5.5 V.

ADuM1400/ADuM1401/ADuM1402

Table 12. ADuM1401 Pin Function Descriptions

No. Mnemonic Function

1 V DD1Supply Voltage for Isolator Side 1, 2.7 V to 5.5 V.

2 GND1Ground 1. Ground reference for isolator Side 1.

3 V IA Logic Input A.

4 V IB Logic Input B.

5 V IC Logic Input C.

6 V OD Logic Output D.

7 V E1Output Enable 1. Active high logic input. V OD output is enabled when V E1 is high or disconnected. V OD is disabled when V E1 is low. In

noisy environments, connecting V E1 to an external logic high or low is recommended.

8 GND1Ground 1. Ground reference for isolator Side 1.

9 GND2Ground 2. Ground reference for isolator Side 2.

10 V E2Output Enable 2. Active high logic input. V OA, V OB, and V OC outputs are enabled when V E2 is high or disconnected. V OA, V OB, and V OC

outputs are disabled when V E2 is low. In noisy environments, connecting V E2 to an external logic high or low is recommended.

11 V ID Logic Input D.

12 V OC Logic Output C.

13 V OB Logic Output B.

14 V OA Logic Output A.

15 GND2Ground 2. Ground reference for isolator Side 2.

16 V DD2Supply Voltage for Isolator Side 1, 2.7 V to 5.5 V.

Table 13. ADuM1402 Pin Function Descriptions

No. Mnemonic Function

1 V DD1Supply Voltage for Isolator Side 1, 2.7 V to 5.5 V.

2 GND1Ground 1. Ground reference for isolator Side 1.

3 V IA Logic Input A.

4 V IB Logic Input B.

5 V OC Logic Output C.

6 V OD Logic Output D.

7 V E1Output Enable 1. Active high logic input. V OC and V OD outputs are enabled when V E1 is high or disconnected. V OC and V OD outputs are

disabled when V E1 is low. In noisy environments, connecting V E1 to an external logic high or low is recommended.

8 GND1Ground 1. Ground reference for isolator Side 1.

9 GND2Ground 2. Ground reference for isolator Side 2.

10 V E2Output Enable 2. Active high logic input. V OA and V OB outputs are enabled when V E2 is high or disconnected. V OA and V OB outputs are

disabled when V E2 is low. In noisy environments, connecting V E2 to an external logic high or low is recommended.

11 V ID Logic Input D.

12 V IC Logic Input C.

13 V OB Logic Output B.

14 V OA Logic Output A.

15 GND2Ground 2. Ground Reference for Isolator Side 2.

16 V DD2Supply Voltage for Isolator Side 2, 2.7 V to 5.5 V.

Rev. B | Page 16 of 24

ADuM1400/ADuM1401/ADuM1402

Rev. B | Page 17 of 24

TYPICAL PERFORMANCE CHARACTERISTICS

04407-0-011

DATA RATE (Mbps)

C U R R E N T /C H A N N E L (m A )

010

6080

40100

Figure 8. Typical Input Supply Current per Channel vs. Data Rate

for 5 V and 3 V Operation

04407-0-012

DATA RATE (Mbps)

C U R R E N T /C H A N N E L (m A )

6080

40100

Figure 9. Typical Output Supply Current per Channel vs. Data Rate

for 5 V and 3 V Operation (No Output Load)

04407-0-013

DATA RATE (Mbps)

C U R R E N T /C H A N N E L (m A )

6080

40100

Figure 10. Typical Output Supply Current per Channel vs. Data Rate

for 5 V and 3 V Operation (15 pF Output Load) 04407-0-014DATA RATE (Mbps)

C U R R E N T (m A )

040502010

306070

8020

608040100

Figure 11. Typical ADuM1400 V DD1 Supply Current vs. Data Rate

for 5 V and 3 V Operation

04407-0-015DATA RATE (Mbps)

C U R R E N T (m A )

010

608040100

Figure 12. Typical ADuM1400 V DD2 Supply Current vs. Data Rate

for 5 V and 3 V Operation

04407-0-016

DATA RATE (Mbps)

C U R R E N T (m A )

025

2015

5020

608040100

Figure 13. Typical ADuM1401 V DD1 Supply Current vs. Data Rate

for 5 V and 3 V Operation

ADuM1400/ADuM1401/ADuM1402

Rev. B | Page 18 of 24

04407-0-017

DATA RATE (Mbps)

C U R R E N T (m A )

02015105

302535

4020

6080

40100

Figure 14. Typical ADuM1401 V DD2 Supply Current vs. Data Rate

for 5 V and 3 V Operation

04407-0-018

DATA RATE (Mbps)

C U R R E N T (m A )

02520

15105454035305020

6080

40100

Figure 15. Typical ADuM1402 V DD1 or V DD2 Supply Current vs.

Data Rate for 5 V and 3 V Operation

TEMPERATURE (°C)

P R O P A G A T I O N D E L A Y (n s )

–50

–25

2530

0507525100

03786-0-023

Figure 16. Propagation Delay vs. Temperature, C Grade

ADuM1400/ADuM1401/ADuM1402

Rev. B | Page 19 of 24

APPLICATION INFORMATION

PC BOARD LAYOUT

The ADuM140x digital isolator requires no external interface circuitry for the logic interfaces. Power supply bypassing is strongly recommended at the input and output supply pins (Figure 17). Bypass capacitors are most conveniently connected between Pins 1 and 2 for V DD1 and between Pins 15 and 16 for V DD2. The capacitor value should be between 0.01 μF and 0.1 μF. The total lead length between both ends of the capacitor and the input power supply pin should not exceed 20 mm. Bypass-ing between Pins 1 and 8 and between Pins 9 and 16 should also be considered unless the ground pair on each package side is connected close to the package.

GND V V V V V GND DD22OA OB OC/IC OD/ID E22

03786-0-01

Figure 17. Recommended Printed Circuit Board Layout

In applications involving high common-mode transients, care should be taken to ensure that board coupling across the isola-tion barrier is minimized. Furthermore, the board layout should be designed such that any coupling that does occur equally affects all pins on a given component side. Failure to ensure this could cause voltage differentials between pins exceeding the device’s Absolute Maximum Ratings, thereby leading to latch-up or permanent damage.

PROPAGATION DELAY-RELATED PARAMETERS

Propagation delay is a parameter that describes the time it takes a logic signal to propagate through a component. The propaga-tion delay to a logic low output may differ from the propagation delay to a logic high.

03786-0-020

Figure 18. Propagation Delay Parameters

Pulse-width distortion is the maximum difference between these two propagation delay values and is an indication of how accurately the input signal’s timing is preserved.

Channel-to-channel matching refers to the maximum that

amount the propagation delay differs between channels within a single ADuM140x component.

Propagation delay skew refers to the maximum that amount the propagation delay differs between multiple ADuM140x compo-nents operating under the same conditions.

DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY

Positive and negative logic transitions at the isolator input cause narrow (~1 ns) pulses to be sent to the decoder via the transformer. The decoder is bistable and is, therefore, either set or reset by the pulses, indicating input logic transitions. In the absence of logic transitions at the input for more than 2 μs, a periodic set of refresh pulses indicative of the correct input state are sent to ensure dc correctness at the output. If the decoder receives no internal pulses of more than about 5 μs, the input side is assumed to be unpowered or nonfunctional, in which case the isolator output is forced to a default state (see Table 10) by the watchdog timer circuit.

The limitation on the ADuM140x’s magnetic field immunity is set by the condition in which induced voltage in the transformer’s receiving coil is sufficiently large to either falsely set or reset the decoder. The following analysis defines the conditions under which this may occur. The 3 V operating condition of the ADuM140x is examined because it represents the most susceptible mode of operation.

The pulses at the transformer output have an amplitude greater than 1.0 V . The decoder has a sensing threshold at about 0.5 V , therefore establishing a 0.5 V margin in which induced voltages can be toler-ated. The voltage induced across the receiving coil is given by

V = (–d β/dt )∑∏r n 2; n = 1, 2,…, N where:

β is magnetic flux density (gauss).

N is the number of turns in the receiving coil.

r n is the radius of the n th turn in the receiving coil (cm). Given the geometry of the receiving coil in the ADuM140x and an imposed requirement that the induced voltage be at most 50% of the 0.5 V margin at the decoder, a maximum allowable magnetic field is calculated as shown in Figure 19.

MAGNETIC FIELD FREQUENCY (Hz)

100.000

M A X I M U M A L L O W A B L E M

A G N E T I C F L U X D E N S I T Y (k g a u s s )

0.001

1M 10.000

0.010

10k 10M 0.100

1.000

100M

100k

03786-0-021

Figure 19. Maximum Allowable External Magnetic Flux Density

ADuM1400/ADuM1401/ADuM1402

Rev. B | Page 20 of 24

For example, at a magnetic field frequency of 1 MHz, the maximum allowable magnetic field of 0.2 kgauss induces a voltage of 0.25 V at the receiving coil. This is about 50% of the sensing threshold and does not cause a faulty output transition. Similarly, if such an event were to occur during a transmitted pulse (and was of the worst-case polarity), it would reduce the received pulse from > 1.0 V to 0.75 V—still well above the 0.5 V sensing threshold of the decoder.

The preceding magnetic flux density values correspond to specific current magnitudes at given distances from the ADuM140x trans-formers. Figure 20 expresses these allowable current magnitudes as a function of frequency for selected distances. As seen, the

ADuM140x is extremely immune and can be affected only by ex-tremely large currents operated at high frequency, very close to the component. For the 1 MHz example noted, one would have to place a 0.5 kA current 5 mm away from the ADuM140x to affect the component’s operation.

MAGNETIC FIELD FREQUENCY (Hz)

M A X I M U M A L L O W A B L E C U R R E N T (k A )

1000.00100.00

10.00

1.00

0.10

0.01

1k 10k 100M

100k 1M 10M

03786-0-022

Figure 20. Maximum Allowable Current for Various Current-to-ADuM140x Spacings

Note that at combinations of strong magnetic field and high frequency, any loops formed by printed circuit board traces could induce sufficiently large error voltages to trigger the thresholds of succeeding circuitry. Care should be taken in the layout of such traces to avoid this possibility.

POWER CONSUMPTION

The supply current at a given channel of the ADuM140x isola-tor is a function of the supply voltage, the channel’s data rate, and the channel’s output load.

For each input channel, the supply current is given by

I DDI = I DDI (Q )

f ≤ 0.5f r I DDI = I DDI (D) × (2f – f r ) + I DDI (Q )

f > 0.5f r

For each output channel, the supply current is given by

I DDO = I DDO (Q )

f ≤ 0.5f r

I DDO = (I DDO (D ) + (0.5 × 10?3) × C L V DDO ) × (2f – f r ) + I DDO (Q )

f > 0.5f r where:

I DDI (D), I DDO (D) are the input and output dynamic supply currents

per channel (mA/Mbps). C L is output load capacitance (pF). V DDO is the output supply voltage (V).

f is the input logic signal frequency (MHz, half of the input data rate, NRZ signaling).

f r is the input stage refresh rate (Mbps).

I DDI (Q), I DDO (Q) are the specified input and output quiescent sup-ply currents (mA).

To calculate the total I DD1 and I DD2 supply current, the supply currents for each input and output channel corresponding to I DD1 and I DD2 are calculated and totaled. Figure 8 and Figure 9 provide per-channel supply currents as a function of data rate for an unloaded output condition. Figure 10 provides per-channel supply current as a function of data rate for a 15 pF output condition. Figure 11 through Figure 14 provide total I DD1 and I DD2 supply current as a function of data rate for

ADuM1400/ADuM1401/ADuM1402 channel configurations.

信号隔离安全栅与信号隔离器的区别

信号隔离安全栅与信号隔离器的区别一、定义 1、信号隔离器（isolator ）：一般指弱电系统中的信号隔离器，既保护下级信号系统不受上级系统影响和干扰。 2、信号隔离安全栅（safety barrier）：接在本质安全电路和非本质安全电路之间。将供给本质安全电路的电压或电流限制在一定安全范围内的装置。安全栅是一种统称，分为齐纳式安全栅和隔离式安全栅，隔离式安全栅简称隔离栅。金湖英普瑞电子设备有限公司主营产品有：隔离安全栅，信号隔离器，信号隔离配电器，直流信号隔离器,开关量信号安全栅，电流变送器。同时代理日本横河EJA变送器，横河AXF 电磁流量计，横河DY涡街流量计，罗斯蒙特3051系列变送器,罗斯蒙特248系列温度变送器，罗斯蒙特475手操器。二、工作原理 1、信号隔离器工作原理：首先将变送器或仪表的信号，通过半导体器件调制变换，然后通过光感或磁感器件进行隔离转换，然后再进行解调变换回隔离前原信号，同时对隔离后信号的供电电源进行隔离处理。保证变换后的信号、电源、地之间绝对独立。 2、齐纳式安全栅的工作原理安全栅的主要功能就是限制安全场所的危险能量进入危险场所，及限制送往危险场所的电压和电流。齐纳管Z用于限制电压。当回路电压接近安全限压值时，齐纳管导通，使齐纳管两端的电压始终保持在安全限压值以下。电阻R用于限制电流。当电压被限制后，适当选择电阻值，可将回路电流限制在安全限流值以下。保险丝F的作用是防止因齐纳管被长时间流过的大电流烧断而导致回路限压失效。当超过安全限压值的电压加在回路上时，齐纳管导通，如果没有保险丝，流经齐纳管的电流将无限上升，最终烧断齐纳管，使回路失去限压。为确保回路限压安全，保险丝的熔断速度要比齐纳管可能被烧断的速度快十倍。采用图一所示的三冗余齐纳管的安全栅基本限能电路结构，能够确保安全栅在正常工作、一个故障点和两个故障点时均能将安全栅的输出能量限制在安全参数规定的范围之内，从而满足ia级本质安全电路的要求。 3、隔离式信号隔离安全栅的工作原理与齐纳安全栅相比，隔离式安全栅除具有限压与限流的作用之外，还带有电流隔离的功能。隔离栅通常由回路限能单元、电流隔离单元和信号处理单元三部分组成，基本功能电路如图二所示。回路限能单元为安全栅的核心

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第五章过程输入输出通道技术汇总

第五章过程通道在计算机控制系统中，为了实现对生产过程的控制，要将对象的控制参数及运行状态按规定的方式送入计算机，计算机经过计算、处理后，将结果以数字量的形式输出，此时需将数字量变换为适合生产过程控制的量，因此在计算机和生产过程之间，必须设置完成信息的传递和变换装置，这个装置称为过程输入输出通道，也叫I/O通道。 5.1过程输入输出通道概述过程输入输出通道由模拟量输入输出通道和开关量输入输出通道组成。过程输入输出通道在微型计算机和工业生产过程之间起着信号传递与变换的纽带作用。 5.1.1 模拟量输入通道的一般结构过程参数由传感元件和变送器测量并转换为电压（或电流）形式后送至多路开关；在微机的控制下，由多路开关将各个过程参数依次地切换到后级，进行放大、采样和A/D转换，实现过程参数的巡回检测。 5.1.2 模拟量输出通道的基本结构多D/A结构的模拟量输出通道中的D/A转换器除承担数字信号到模拟信号转换的任务外，还兼有信号保持作用，即把微机在t=kT 时刻对执行机构的控制作用维持到下一个输出时刻t=(k+1)T。这是一种数字保持方式，送给D/A转换器的数字信号不变，其模拟输出信号便保持不变。共享D/A结构的模拟量输出通道中的D/A转换器只起数字信号到模拟信号的转换作用，信号保持功能靠采样保持器完成。这是一种模拟保持方式，微机对通路i（i=1，2，...，n）的控制信号被D/A转换器转换为模拟形式后，由采样保持器将其记忆下来，并保持到下一次控制信号的到来。多D/A形式输出速度快、工作可靠、精度高，是工业控制领域普遍

采用的形式。 5.1.3 开关量（数字量）输入通道的基本结构开关量输入通道又称为数字量输入通道，该通道的任务是把被控对象的开关状态信号（或数字信号）送给计算机、或把双值逻辑的开关量变换为计算机能够接收的数字量送给计算机，简称DI通道。典型的开关量输入通道通常由以下几部分组成： 1．信号变换器：将生产过程的非电量开关量转换为电压或电流的双值逻辑值。 2．整形变换电路：将混有毛刺之类干扰的输入双值逻辑信号或其信号前后沿不符合要求的输入信号整形为接近理想状态的方波或矩形波，然后再根据系统要求变换为相应形状的脉冲信号。 3．电平变换电路：将输入的双值逻辑电平转换为与CPU兼容的逻辑电平。 4．总线缓冲器：暂存数字量信息并实现与CPU数据总线的连接。 5．接口逻辑电路：协调各通道的同步工作，向CPU传递状态信息并控制开关量的输入、输出。 5.1.4 开关量（数字量）输出通道的基本结构开关量（数字量）输出通道的任务是把计算机输出的数字信号（或开关信号）传送给开关型的执行机构（如继电器或指示灯等），控制它们的通、断或亮、灭，简称DO通道。其典型结构中锁存输出的主要作用是锁存CPU输出的数据或控制信号，供外部设备使用；隔离部件的作用是为防止干扰；功放的作用则是为把计算机输出的微弱数字信号转换成能对生产过程进行控制的驱动信号。下面分别展开说明四种过程通道的组成及应用。

信号隔离器的工作原理及功能是什么

信号隔离器的工作原理及功能是什么？ 1.工作原理：首先将变送器或仪表的信号，通过半导体器件调制变换，然后通过光感或磁感器件进行隔离转换，然后再进行解调变换回隔离前原信号，同时对隔离后信号的供电电源进行隔离处理。保证变换后的信号、电源、地之间绝对独立。 2.功能：一：保护下级的控制回路。二：消弱环境噪声对测试电路的影响。三：抑制公共接地、变频器、电磁阀及不明脉冲对设备的干扰；同时对下级设备具有限压、额流的功能是变送器、仪表、变频器、电磁阀PLC/DCS输入输出及通讯接口的忠实防护。 DIN系列导轨结构，易于安装，可有效的隔离：输入、输出和电源及大地之间的电位。能够克服变频器噪声及各种高低频脉动干扰。信号隔离器的主要类型有哪些？ 1.隔离器：工业生产中为增加仪表负载能力并保证连接同一信号的仪表之间互不干扰，提高电气安全性能。需要将输入的电压、电流或频率、电阻等信号进行采集、放大、运算、和进行抗干扰处理后，再输出隔离的电流和电压信号，安全的送给二次仪表或plc\dcs使用。 2.配电器：工业现场一般需要采用两线制传输方式，既要为变送器等一次仪表提供24V配电电源，同时又要对输入的电流信号进行采集、放大、运算、和进行抗干扰处理后，再输出隔离的电流和电压信号，供后面的二次仪表或其它仪表使用。 3.安全栅：

一些特殊的工业现场（如燃气公司和化工厂）不但需要两线制传输，既提供配电电源又有信号隔离功能，同时还需要具有安全火花防爆的性能，可靠地遏制电源功率、防止电源、信号及地之间的点火，限流、降压双重限制信号及电源回路，把进入危险场所的能量限制在安全定额范围内。信号隔离器安装维护应注意哪些事项？由于生产厂家不同，对隔离器的生产工艺、接线定义也不都相同，但使用场合基本相同，所以对产品的防护要求及维护基本相同。 1．使用前应详细阅读说明书。 2．作为信号隔离使用时，应将输入端串入环路电路中，输出端接取样回路。 3．作为隔离配电使用时，应将输入端串入电源电路中，输出端接变送器。 4．若不正常工作应先检查接线是否正确，注意电源有无及极性反正。为什么有时PLC接收到的现场信号误差大且稳定性差？造成这种现象的原因很多，不同仪表信号参考点之间的电位差是重要因素。由于这个“电位差”造成仪表信号之间产生干扰电流，致使PLC误差大且稳定性差。所以不同设备、仪表的信号有一个共同的参考点是最佳状况。隔离器使输入/输出电气上完全隔离，在PLC模拟接口板形成共同的参考点，达到理想状况问题就解决了。设计隔离端子的原则是什么？需要为每台隔离器都配电源吗？设计要遵循两个原则。第一：外部设备与中央处理系统（例如PLC、DCS）之间要进行电气隔离。第二：外部设备信号（无论是向中央处理系统发送信号的外部设备到还是接收信号的外部设备）之间要实现相互电气隔离。例如要把PLC输出的一路

数字隔离器(磁隔离)产品常见问题解答(ADI)

FAQ: Isolation, i Coupler? Technology, and i Coupler Products Isolation What is isolation? Why is it needed? What are common applications that use isolation? How is isolation specified? What is isolation rating? What are working voltage and rated mains voltage? What is the relationship between working voltage and isolation rating? What is the difference between basic and double (or reinforced) insulation levels? What are transient immunity and common-mode rejection? What other parameters are important when considering an isolation device? Regulatory Standards What regulatory standards address isolation products? Traditional Isolation Technologies What types of technologies have been used to provide isolation? What are optocouplers? What is optical isolation? What is transformer isolation? What is capacitive isolation? i Coupler Technology What is i Coupler technology? What are the benefits of i Coupler technology? How much isolation can i Coupler products provide? With which regulatory standards do i Coupler products comply? Do i Coupler products have VDE certification for reinforced insulation? Are i Coupler products sensitive to external magnetic fields? i Coupler Products What are the different types of i Coupler products? Which i Coupler product is best for my application? What communications protocols are supported by i Coupler products? What are some of the distinguishing features of the i Coupler products? Can I replace an optocoupler with an i Coupler product in an existing design? How do i Coupler products differ from interface products? Does Analog Devices provide other products that employ i Coupler technology? Are i Coupler products Pb-free? How do I learn about new i Coupler products? iso Power? What is iso Power What are common applications of iso Power? How does iso Power work? What are the benefits of iso Power?

3数字信号处理器

Words and Expressions follow v.遵循memory n.存储器 register n.寄存器access v.访问 overlap v. 重叠pipelining n. 流水线操作multiplier n. 乘法器accumulator n. 累加器shifter n.移位器reference n. 寻址mantissa n.尾数exponent n. 指数 cycle n. 机器周期customize v.定制，用户化package v.封装 digital signal processor 数字信号处理器von Neumann architecture 冯·诺伊曼结构shared single memory 单一共享存储器program instruction 程序指令 harvard architecture 哈佛结构 fetch from 从…获取 circular buffer 循环缓冲区，环形缓冲区address generator 地址产生器 fixed point 定点 floating point 浮点 binary point 二进制小数点 available precision 可用精度 dynamic range 动态范围 scale range 量程 smallest Resolvable Difference 最小分辨率scientific notation 科学计数法assembly language 汇编语言 multi-function instructions 多功能指令parallel architecture 并行结构 looping scheme 循环机制 sampling frequency 采样频率on-chip memory 片内存储器 well-matched 非常匹配 software tools 软件开发工具 low level programming language 低级编程语言high level programming language 高级编程语言third party software 第三方软件 board level product 板级产品 data register 数据寄存器 ALU=Arithmetic Logical Unit 运算逻辑单元program sequencer 程序定序器 peripheral sections 外设 single integrated circuit 单片集成电路 cellular telephone 蜂窝电话 printed circuit board 印刷电路板 licensing agreement 专利使用权转让协定custom devices 定制器件 extra memory 附加存储器 stand alone 单机 third party developer 第三方开发商multimedia operations 多媒体操作 merged into 融合 calculation-intensive algorithm运算密集型算法

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龙源期刊网 https://www.doczj.com/doc/6713596259.html, 数字隔离器工作原理及应用实例作者：徐华来源：《电脑知识与技术·学术交流》2008年第22期摘要：讨论了隔离技术的发展，分析了数字隔离器的工作原理，给出了数字隔离器的应用实例。关键词：隔离；数字隔离器；高频通道；低频通道；传感器；接口中图分类号：TN305文献标识码：A文章编号：1009-3044(2008)22-772-02 The Working Principle and Applications of the Digital Isolator XU Hua (Xiamen Kerun Electronic Technology Co.Ltd, Xiamen 361006, China) Abstract: Discuss the development of isolation technology, analysis the working principle of the digital isolator, and also give the applications of digital isolators. Key words: isolation; digital isolators; high-frequency channel; low-frequency channel; sensor; interface 1 引言进行隔离是防止电流在两个通讯点之间流动的一种方法。一般在两种情况下采用隔离：第一种情况是，在有可能存在损坏设备或危害人员的潜在的电流浪涌时。第二种情况是必须避免存在不同地电位和分裂的接地回路的互连。两种情形都是采用隔离来避免电流流过，而允许两点之间有数据或功率传送。隔离应用涉及高电压、高速/高精度通信、或者长距离通信。普通的例子如工业I/O系统、传感器接口、电源/调节杆，发动机控制/驱动系统以及仪器仪表。 2 早期的隔离技术早期的设计除使用变压器之外，还使用各种模拟隔离放大器，将工厂地面的传感器电路与控制室内的信号处理系统进行隔离。在通道数量有限及信号带宽小的应用中，目前仍在采用这些放大器。隔离放大器虽然具有高可靠性和高精度，但受限于信号带宽50kHz。其老旧的技术要求最小±4V的电源，不支持目前的3V及以下的低电压应用。此外，其制造过程涉及输入和输出部分单独制作，异常电路匹配的激光微调，以及在两部分间安装隔离电容，使这些器件相当昂贵。 3 多通道隔离

信号隔离模块(信号隔离器)

DATA-8205 信号隔离模块主要用于对工业设备的RS232/RS485通信接口的隔离保护，通过模块内部电路的电气隔离，可有效避免地线回路电压、浪涌、感应雷击、静电、热插拔、电磁干扰等因素造成的设备损坏。设备特点： ◆工业级电磁隔离，能够提供高达2500Vrms的隔离电压。 ◆完整的保护方案能使RS-232/RS-485设备安装于任何复杂的工业环境而免除静电、雷击、电磁和浪涌对设备的干扰或损坏。 ◆用户可自主设定隔离串口类型。 ◆全透明通信，无须调试、即插即用。 ◆通信波特率自适应。 ◆体积小巧，安装方便。产品型号DATA-8205 符合标准EIA/TIA RS-232C、RS-485国际标准工作方式自定义串口类型波特率300bps ~ 57600bps自适应信号隔离2500V 电源隔离非隔离传输介质双绞线或屏蔽线工作电源9 ~ 30VDC宽压输入响应时间≤ 10nm 安装方式DIN导轨安装（35mm）适用环境即插即用工作环境-40℃到 85℃，相对湿度为5%到95% 外壳材质工程塑料外型尺寸100x25.4x74mm

DATA-8301 信号隔离模块是工业级电流信号隔离分配器，采用磁隔离技术保证隔离器的隔离功能:输入、输出、电源之间全隔离，能够屏蔽现场各种干扰信号和有害信号，同时保证输出信号不衰减，提供高精度信号。采集现场各类一次传感器或其他仪表输出的直流信号后，经隔离、抗干扰处理后输出，使得检测和控制回路信号的安全性和抗干扰能力大大增强，提高系统可靠性。设备特点： ◆采用高精度采集芯片，精度高。 ◆兼容性强，可接入各种4~20mA输出的变送器及仪表。 ◆具备两路电流输入、两路隔离电流输出，可为变送器和仪表提供DC 12V/24V供电电源。 ◆体积小巧，标准DIN35导轨安装，节省空间、安装简便。产品型号DATA-8301 工作电压：10V～30V DC 负载能力：0~250Ω 消耗功率：≤2W 工作精度：±0.2% 隔离耐压：1500VDC 绝缘电阻：>100MΩ 响应时间：200μS 电磁兼容：IEC61000-4-4：1995 环境温度：-30℃~ 85℃ 环境湿度: <90% 无结露

ISO764_数字隔离器

ISO7640 GND2GND2OUTA OUTC OUTB EN OUTD V V CC2 GND2 GND2OUTA OUTC OUTB IND EN2V V CC2ISO7641ISO7640FM ISO7641FM https://www.doczj.com/doc/6713596259.html, SLLSE89D –SEPTEMBER 2011–REVISED JULY 2012 Low Power Quad Channels Digital Isolators Check for Samples:ISO7640FM ,ISO7641FM FEATURES APPLICATIONS ?Signaling Rate:150Mbps ?Optocoupler Replacement in:?Low Power Consumption,Typical I CC per –Industrial Fieldbus Channel (3.3V Supplies): –Profibus –ISO7640FM:2mA at 25Mbps –Modbus –ISO7641FM:2.4mA at 25Mbps –DeviceNet TM Data Buses ?Low Propagation Delay:7ns Typical –Servo Control Interface ?Output Defaults to Low-state in fail-safe mode –Motor Control ?Wide Temperature Range:–40°C to 125°C –Power Supplies ?50KV/μs Transient Immunity,Typical –Battery Packs ?Long Life with SiO 2Isolation barrier SAFETY AND REGULATORY ?Operates From 2.7V,3.3V and 5V Supply and APPROVALS Logic Levels ? 6000V PK /4243V RMS for 1Minute per UL 1577?Wide Body SOIC-16Package (approved)? VDE Approval for DIN EN 60747-5-2(VDE 0884Rev.2),1414V PK Working Voltage (approved)? CSA Component Acceptance Notice 5A,IEC 60601-1Medical Standard (approved)?5KV RMS Reinforced Insulation per TUV for EN/UL/CSA 60950-1and EN/UL/CSA 61010-1 (approved) DESCRIPTION ISO7640FM and ISO7641FM provide galvanic isolation up to 6KV PK for 1minute per UL and VDE.These devices are also certified up to 5KV RMS Reinforced isolation at a working voltage of 400V RMS per end equipment standards EN/UL/CSA 60950-1and 61010-1.ISO7640F and ISO7641F are quad channel isolators;ISO7640F has four forward and ISO7641F has three forward and one reverse direction channels.Suffix F indicates that output defaults to Low-state in fail-safe conditions (see Table 1).M-Grade devices are high speed isolators capable of 150Mbps data rate with fast propagation delays Please be aware that an important notice concerning availability,standard warranty,and use in critical applications of 捷多邦，您值得信赖的PCB打样专家！

信号隔离器应用场合及使用原理

信号隔离器应用场合及使用原理 2008/3/6/09:04 1．信号隔离器的作用（1）地环流干扰在工业生产过程中实现监视和控制需要用到各种自动化仪表、控制系统和执行机构，他们之间的信号传输既有微弱到毫伏级、毫安级的小信号；又有几十伏，数千伏、数百安培的大信号；既有低频直流信号，也有高频脉冲信号等等，构成系统后往往发现在仪表和设备之间传输相互干扰，造成系统不稳定甚至误操作，出现这种情况除了每个仪器、设备本身的性能原因如抗电磁干扰影响，还有一个十分重要的原因就是各种仪器设备根据要求和目的都需要接地,例如为了安全，机壳需要接大地；为了使电路正常工作，系统需要有公共参考点；为了抑制干扰加屏蔽罩，屏蔽罩也需要接地，但是由于仪表和设备之间的参考点之间存在电势差（也就是各设备的共地点不同）因而形成“地环流”、“接地环流”问题是在系统处理信号过程中必须解决的问题。（2）自然干扰雷电是一种主要的自然干扰源，雷电产生的干扰可以传输到数千公里以外的地方。雷电干扰的时域波形是叠加在一串随机脉冲背景上的一个大尖峰脉冲。宇宙噪音是电离辐射产生的，在一天中不断变化。太阳噪音则随着太阳活动情况的剧烈变化。自然界噪声主要会对通讯产生干扰，而雷电能量尖蜂脉冲可以对很多设备造成损坏，应该加以避免或降低损坏程度，减少损失。（3）人为干扰电磁干扰产生的根本原因是导体中有电压或电流的变化，即较大dv/dt或di/dt.dv/dt或di/dt能够使导体产生电磁波辐射。一方面，人们可以利用这一特点实现特定功能，例如，无限通信、雷达或其他功能，另一方面，电子设备在工作时，由于导体中的dv/dt或di/dt会产生伴随电磁辐射。无论主观上出于什么目的，客观上对电磁环境造成了污染。还有工厂企业在生产过程中会经常有一些大型的设备（电机、变频器）频繁开关，他们也会造成一些容性、感性的干扰，也将影响仪器仪表正常显示或采集。凡是有电压电流突变的场合，肯定会有电磁干扰存在。数字脉冲电路就是一种典型的干扰源，随着电子技术的广泛应用,电磁污染情况会越来越严重. 2.解决各种干扰的方法首先干扰的三要素是干扰源、敏感源和耦合路径，这三要素缺少一个，电磁兼容问题都不会存在。因此要从这三要素入手。找出最方便的解决方法，一般干扰源和敏感源是没办法解决的，通常是从耦合路径想办法，也是最常用的方法。如加屏蔽、加滤波等手段。而处理环流最常见也最为麻烦，现在以此为探讨话题。（1）第一种方法；所有现场设备不接地，使所有过程环路只有一个接地点，不能形成回路，这种方法看似简单，但实际应用中往往很难实现，因为某些设备要求必须接地才能保证测量精度或人身安全，某些设备可能因为长期遭到腐蚀和磨损后或气候影响而形成新的接地点。

信号隔离器的原理以及分类

信号隔离器的原理以及常见分类浅谈关于隔离器的一些常见以及常用的知识：首先将变送器或仪表的信号，通过半导体器件调制变换，然后通过光感或磁感器件进行隔离转换，然后再进行解调变换回隔离前原信号，同时对隔离后信号的供电电源进行隔离处理。保证变换后的信号、电源、地之间绝对独立。功能：一：保护下级的控制回路。二：消弱环境噪声对测试电路的影响。三：抑制公共接地、变频器、电磁阀及不明脉冲对设备的干扰；同时对下级设备具有限压、额流的功能是变送器、仪表、变频器、电磁阀PLC/DCS输入输出及通讯接口的忠实防护。 KLG系列导轨结构，易于安装，可有效的隔离：输入、输出和电源及大地之间的电位。能够克服变频器噪声及各种高低频脉动干扰。隔离器：工业生产中为增加仪表负载能力并保证连接同一信号的仪表之间互不干扰，提高电气安全性能。需要将输入的电压、电流或频率、电阻等信号进行采集、放大、运算、和进行抗干扰处理后，再输出隔离的电流和电压信号，安全的送给二次仪表或plc\dcs使用。配电器：工业现场一般需要采用两线制传输方式，既要为变送器等一次仪表提供24V配电电源，同时又要对输入的电流信号进行采集、放大、运算、和进行抗干扰处理后，再输出隔离的电流和电压信号，供后面的二次仪表或其它仪表使用。安全栅：一些特殊的工业现场(如燃气公司和化工厂)不但需要两线制传输，既提供配电电源又有信号隔离功能，同时还需要具有安全火花防爆的性能，可靠地遏制电源功率、防止电源、信号及地之间的点火，限流、降压双重限制信号及电源回路，把进入危险场所的能量限制在安全定额范围内。由于生产厂家不同，对隔离器的生产工艺、接线定义也不都相同，但使用场合基本相同，所以对产品的防护要求及维护基本相同。 1．使用前应详细阅读说明书。 2．作为信号隔离使用时，应将输入端串入环路电路中，输出端接取样回路。 3．作为隔离配电使用时，应将输入端并入电源电路中，输出端接变送器。 4．若不正常工作应先检查接线是否正确，注意电源有无及极性反正。在平常的生产过程中你是否经常使用隔离器呢？你能区别有源与无源隔离器的特点么？你能做出好的决定：在哪里是使用有源的？在哪里使用无源的？现在就给大家讲解一下关于信号隔离器的问题。在工业现场，在距离较远的电气设备、仪表、PLC控制系统、DCS 系统之间进行信号传输时，往往存在干扰，造成系统不稳定甚至误操作。除系统内、外部干扰影响外，还有一个十分重要的原因就是各种仪器设备的接地处理问题。一般情况下，设备外壳需要接大地，电路系统也要有公共参考地。但是，由于各仪表设备的参考点之间存在电势差，因而形成接地环路，由于地线环流会带来共模及差模噪声及干扰，常常造成系统不能正常工作。一个理想的解决方案是，对设备进行电气隔离，这样，原本相互联接的地线网络

隔离,您选择光耦还是数字隔离器

话题大PK：隔离，您选择光耦还是数字隔离器？？？由ADIForum于2014-1-15 创建正方——支持数字隔离器：功耗低——数字隔离器在低频条件下只使用光耦合器功率的1%；在50Mbps，即光耦合器最高传送速率条件下（数字隔离器可以工作在100Mbps以上），它使用光耦合器功率的大约20%。降低功率会使其提高可靠性。设计简单方便——单个器件；标准TTL或CMOS；电源可根据预算灵活调整；无CTR，在整个温度范围内稳定工作；不像光耦缺少集成特性，完整的集成解决方案降低整体BOM成本…… 反方——支持光耦：光耦是70年代发展起来的隔离器件，产品种类繁多，价格便宜；信号单向传输，输入端与输出端完全实现了电气隔离隔离，输出信号对输入端无影响，抗干扰能力强，无触点，使用寿命长； …… 您怎么看？欢迎参与探讨（无论您持怎样的观点，尽可畅所欲言，无所谓对错）。。。硬件高手的实际设计经验分享——提高系统效率的几个误解 mu-zi 2014-1-10 下午5:52 误解一：这主频100M的CPU只能处理70%，换200M主频的就没事了点评：系统的处理能力牵涉到多种多样的因素，在通信业务中其瓶颈一般都在存储器上，CPU 再快，外部访问快不起来也是徒劳。误解二：CPU用大一点的CACHE，就应该快了点评：CACHE的增大，并不一定就导致系统性能的提高，在某些情况下关闭CACHE反而比使用CACHE还快。原因是搬到CACHE中的数据必须得到多次重复使用才会提高系统效率。所以在通信系统中一般只打开指令CACHE，数据CACHE即使打开也只局限在部分存储空间，如堆栈部分。同时也要求程序设计要兼顾CACHE的容量及块大小，这涉及到关键代码循环体的长度及跳转范围，如果一个循环刚好比CACHE大那么一点点，又在反复循环的话，那就惨了。误解三：这么多任务到底是用中断还是用查询呢？还是中断快些吧点评：中断的实时性强，但不一定快。如果中断任务特别多的话，这个没退出来，后面又接踵而至，一会儿系统就将崩溃了。如果任务数量多但很频繁的话，CPU的很大精力都用在进出中断的开销上，系统效率极为低下，如果改用查询方式反而可极大提高效率，但查询有时不能满足实时性要求，所以最好的办法是在中断中查询，即进一次中断就把积累的所有任务都处理完再退出。

信号隔离器的作用

信号隔离器的作用（1）地环流干扰在工业生产过程中实现监视和控制需要用到各种自动化仪表、控制系统和执行机构，他们之间的信号传输既有微弱到毫伏级、毫安级的小信号；又有几十伏，数千伏、数百安培的大信号；既有低频直流信号，也有高频脉冲信号等等，构成系统后往往发现在仪表和设备之间传输相互干扰，造成系统不稳定甚至误操作，出现这种情况除了每个仪器、设备本身的性能原因如抗电磁干扰影响，还有一个十分重要的原因就是各种仪器设备根据要求和目的都需要接地,例如为了安全，机壳需要接大地；为了使电路正常工作，系统需要有公共参考点；为了抑制干扰加屏蔽罩，屏蔽罩也需要接地，但是由于仪表和设备之间的参考点之间存在电势差（也就是各设备的共地点不同）因而形成“地环流”、“接地环流”问题是在系统处理信号过程中必须解决的问题。（2）自然干扰雷电是一种主要的自然干扰源，雷电产生的干扰可以传输到数千公里以外的地方。雷电干扰的时域波形是叠加在一串随机脉冲背景上的一个大尖峰脉冲。宇宙噪音是电离辐射产生的，在一天中不断变化。太阳噪音则随着太阳活动情况的剧烈变化。自然界噪声主要会对通讯产生干扰，而雷电能量尖蜂脉冲可以对很多设备造成损坏，应该加以避免或降低损坏程度，减少损失。（2）人为干扰电磁干扰产生的根本原因是导体中有电压或电流的变化，即较大dv/dt 或di/dt.dv/dt 或di/dt 能够使导体产生电磁波辐射。一方面，人们可以利用这一特点实现特定功能，例如，无限通信、雷达或其他功能，另一方面，电子设备在工作时，由于导体中的dv/dt 或di/dt 会产生伴随电磁辐射。无论主观上出于什么目的，客观上对电磁环境造成了污染。还有工厂企业在生产过程中会经常有一些大型的设备（电机、变频器）频繁开关，他们也会造成一些容性、感性的干扰，也将影响仪器仪表正常显示或采集。凡是有电压电流突变的场合，肯定会有电磁干扰存在。数字脉冲电路就是一种典型的干扰源，随着电子技术的广泛应用,电磁污染情况会越来越严重. 2.解决各种干扰的方法首先干扰的三要素是干扰源、敏感源和耦合路径，这三要素缺少一个，电磁兼容问题都不会存在。因此要从这三要素入手。找出最方便的解决方法，一般干扰源和敏感源是没办法解决的，通常是从耦合路径想办法，也是最常用的方法。如加屏蔽、加滤波等手段。而处理环流最常见也最为麻烦，现在以此为探讨话题。（1）第一种方法；所有现场设备不接地，使所有过程环路只有一个接地点，不能形成回路，这种方法看似简单，但实际应用中往往很难实现，因为某些设备要求必须接地才能保证测量精度或人身安全，某些设备可能因为长期遭到腐蚀和磨损后或气候影响而形成新的接地点。（2）第二种方法：使两接地点的电势相同，但由于接地的电阻受地质条件及气候变化众多因素的影响，这种方法在其实在实际中也无法完全能做到。（3）第三种方法：在各个过程环节中使用信号隔离器，断开过程环路，同时又不影响过程信号的正常传输，从而彻底解决地环路的问题。 3.采用信号隔离器的优越性在各个过程环路中使用信号隔离器办法可以用DCS 或PLC 等隔离卡件或者现场带的隔离的变送器（部分设备可以做到），也可以用信号隔离器来实现。比较起来，用信号隔离器有以下优点： ·绝大部分情况，采用信号隔离器+非隔离卡件比采用隔离卡件便宜 ·信号隔离器比隔离卡件在隔离能力、抗电磁干扰等方面性能更加优越 ·信号隔离器应用灵活，而且它还有信号转换和信号分配及接口转换等功能，使用起来更加方便 ·信号隔离器通常有单通道、双通道、通道间相互完全独立、构成系统的配置、日常维护更加方便。 1.隔离作用： w w w . c a 18 .n e t

数字信号处理与数字信号处理器

物理学与信息科学技术专题第十讲　数字信号处理与数字信号处理器(D SP) 1) 李昌立 1, 董永宏 2 (1　中国科学院声学研究所　北京　100080)(2　闻亭数字系统(北京)有限公司　北京　100085) 摘　要文章简要介绍了“数字信号处理”与“数字信号处理器(DSP )”的发展历史.在数字信号处理的应用中,实时实现是非常重要的,而DSP 在实时处理中,扮演了一个重要的角色.文章中还介绍了DSP 在实际应用中的一些关键技术,例如DSP 的种类和选型,DSP 的开发工具,实时软件的开发过程等.最后,还介绍了一些DSP 的应用实例,如语音编码器,视频电话和视频会议系统,用于雷达和声纳的DSP 并行处理系统关键词数字信号处理器(DSP ),实时信号处理,DSP 开发工具,DSP 并行处理系统. D i g it a l si gna l processi n g and processors L I Chang 2L i 1, DONG Yong 2Hong 2 (1Institute of Acoustics ,Chinese A cade m y of Sciences,B eijing 100080,China ) (2W intech D igitalsyste m s Technology corp,B eijing 100085,China ) Abstract The history of digital signal p r ocessing and the digital signal p r ocess or (DSP )is reviewed .A s is well known,real -ti me i mp lementation is crucial in the app licati ons of digital signal p rocessing in which the DSP p lays an i m portant role .Certain key techniques,such as the types and type selecti on of DSPs,their devel 2opment equipment,real -ti me s oft ware development and s o on are then described .Finally,s ome p ractical ap 2p licati ons such as s peech coding hardware,video telephone and video conference system s,DSP parallel p ro 2cessing system s for s onar and radar are als o described Keywords digital signal p r ocess or,real -ti me signal p r ocessing .development equi pment,parallel p r ocess 2ing system 1)　该专题的第一至第九讲分别发表于2005年第1—8期,第12期《物理》———编者注 2005-09-27收到初稿,2006-03-14修回　通讯联系人.Email:li_chang_li_cn@hot m ail .com 1　数字信号处理与数字信号处理器(DSP )发展史的简要回顾[1—3] DSP 既是D igital Signal Pr ocessing 的缩写,也是D igital Signal Pr ocess or 的缩写,前者是指数字信号处理的理论和方法,后者则是指用于数字信号处理的可编程微处理器.我们所说的DSP 技术,一般是指将DSP 处理器用于完成数字信号处理的方法和技术. 自从1965年库利(Cooley )和图基(Tukey )在《计算数学》(《Mathe matic of Computati on 》 )上发表了《用机器计算复序列傅里叶级数的一种方法》一文以后,接着又有人发表了在计算机上用差分方程实现滤波器的算法,以及用计算机设计数字滤波器的各种方法.此后,“数字信号处理”这一分支学科迅速发展,逐渐形成了一整套较为完整的学科领域和理论体系.到今天,“数字技术”已经渗透到各行各业,成为了高新技术的代名词.很多传统产业采用

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