Proprietary & Confidential C
65nm Signoff
? 2009 TSMC, Ltd Design and Technology Platform
? 2009 TSMC, Ltd.
Contents
z Signal EM Flow z Power Grid Sign-off z Timing Closure & Sign-off z Dummy filling flow & Timing fixing z Others
Proprietary & Confidential C
? 2009 TSMC, Ltd
DTP/ P. 2
? 2009 TSMC, Ltd.
Signal EM Analysis
z Peak/Avg./RMS current z AstroRail or TSMC utility (Ref. Flow 4.0/5.0)
Proprietary & Confidential C
? 2009 TSMC, Ltd
DTP/ P. 3
? 2009 TSMC, Ltd.
Proprietary & Confidential C
Signal EM Analysis Procedure
1. The temperature for the signal EM analysis: 125C. 2. The RC corner for the RC extraction: Cworst in 125C. 3. The power consumption is calculated in the LT corner, or the ML corner. 4. Set the reasonable switching activity in the signal EM analysis.
? 2009 TSMC, Ltd
DTP/ P. 4
? 2009 TSMC, Ltd.
Power Integrity
z Power grid signed-off in three modes
? ?
Proprietary & Confidential C
Static IR drop
? ?
Average power IR drop < 5% VDD+VSS (wire-bond) 3% ( Flip chip)
Dynamic IR drop
4-5X Static IR < 15% VDD + VSS ? Dcap insertion
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Scan Peak IR around clock-edge < 30% VDD
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Peak power usually around clock-edge ? Seen many chips failing even in scan-mode ? Analyzing IR drop during small timing window when flops are switching
z Power reductions
? ? ?
? 2009 TSMC, Ltd
Leakage: Multi-Vt by default Dynamic: RTL clock gating is highly recommended Comprehensive power approaches for portable device
DTP/ P. 5
? 2009 TSMC, Ltd.
Proprietary & Confidential C
Power Integrity Procedure
1. The temperature for the power EM analysis: 125C. 2. The RC corner for the RC extraction: CWorst in 125C. 3. The power consumption is calculated in the LT corner, -40C/110% VDD/FF, or the ML corner. 4. Set the reasonable toggle rate to calculate the average power consumption. 5. The EM spec is tight in 125C, the current is large in the LT or ML corner, and the power EM criterion in such condition should be most robust.
? 2009 TSMC, Ltd
DTP/ P. 6
? 2009 TSMC, Ltd.
Scan Peak Power
Proprietary & Confidential C
z The most of flops are switching at almost the same Current time CLK Many flops switching Timing window (t)
? 2009 TSMC, Ltd
Clock skew + Average CK-Q delay + Average Transition/2
DTP/ P. 7
? 2009 TSMC, Ltd.
Scan Power Analysis
ATPG Test Patterns Peak Switching Cycle Search IR Sensitivity of Each Flop Flop Transition at Peak Switching Cycle
Proprietary & Confidential C
Peak Power Calculation
SDF & SDC
Dynamic IR Analysis
Peak IR Report & Hot Spot Colormap
? 2009 TSMC, Ltd
DTP/ P. 8
? 2009 TSMC, Ltd.
Static vs. Dynamic IR-drop
Proprietary & Confidential C
Current envelope Average current
Peak current
nT
(n+1)T
(n+2)T
? ?
Wire sizing can be used to control static IR-drop Critical de-cap provides immediate spike filtering
? 2009 TSMC, Ltd
DTP/ P. 9
? 2009 TSMC, Ltd.
65nm PI sign off criteria
Technology node: 65nm PI sign off criteria recommended
Package Wirebond w/o pkg Static 5% w/ pkg 5% w/o pkg 3% Flipchip w/ pkg 3%
Proprietary & Confidential C
Corner
FF/SS VDD: TT FF/SS VDD: TT FF/SS VDD: TT FF, TT VDD: TT FF, TT VDD: TT
VCD Function Vectorless Dynamic VCD Scan Vectorless
10%
15-18%
8-10%
13-15%
10%
15-18%
8-10%
13-15%
10%
15-18%
8-10%
13-15%
10%
15-18%
15-18%
13-15%
? 2009 TSMC, Ltd
IR limit : VDD+GND
DTP/ P. 10
? 2009 TSMC, Ltd.
Timing Closure
(By customer with 10% (By customer with 10% setup time margin && setup time margin CWLM) CWLM)
Proprietary & Confidential C
Synthesis Synthesis
(Double width ++ spacing (Double width spacing ++ via) via)
CTS/CTO CTS/CTO
Signal SignalEM EM Fixing Fixing Decap Decap Insertion Insertion Double DoubleVia Via
TD TDPlacement Placement
(Netlist w/ hold aware (Netlist w/ hold aware buffer insertion +setup buffer insertion +setup time driven) time driven)
(Decap pre-insert, Xtalk (Decap pre-insert, Xtalk prevention, Ant. fixing) prevention, Ant. fixing)
Detail Detailrouting routing
(Derive setup time (Derive setup time requirement for ICG) requirement for ICG)
Trial TrialCTS CTS
RC RCExtraction Extraction Setup/Hold Setup/Hold fixing fixing
(setup/hold fixing) (setup/hold fixing)
Setup Setuptime timeOpt. Opt.
Dummy DummyFill Fill
(setup/hold fixing) (setup/hold fixing)
(All sign-off modes) (All sign-off modes)
Power PowerOpt. Opt.
(Multi-Vt swap) (Multi-Vt swap)
? 2009 TSMC, Ltd
(Glitch && setup/hold (Glitch setup/hold fixing) fixing)
Xtalk XtalkFixing Fixing
STA STASign-off Sign-off
DTP/ P. 11
? 2009 TSMC, Ltd.
Proprietary & Confidential C
Timing Sign-off
z Timing closure taking all kinds of following effects into account
?
Multi-mode STA ? Multiple Device & RC Corners
WC, WCL, BC or LT (-40C) ? Cworst, Cbest (RCworst, RCbest, RCtypical)
?
?
OCV, Hold margin ? Crosstalk ? DFM – Dummy metals, Dummy Vias
? 2009 TSMC, Ltd
DTP/ P. 12
? 2009 TSMC, Ltd.
Proprietary & Confidential C
OCV
z OCV – On Chip Variation
? 2009 TSMC, Ltd
DTP/ P. 13
? 2009 TSMC, Ltd.
Proprietary & Confidential C
Timing Sign-off Recommendation
z Clock jitter is not included
WC + Cworst 65nm Setup/ hold WCL + Cworst Setup/ hold BC or LT + Cbest/Cworst hold Max. transition 0.6ns* Setup margin 0 Hold margin 50ps
OCV WC: 5% BC:10%
*Max transition applied at WC corner. *Over constraint is recommended at APR stage. **Typical number showed here: - OCV and Hold margin design dependant: transition, cell types, IR-drop **Corner shown here: - It is the basis. Customer should add more corners based on product application. ? 2009 TSMC, Ltd
DTP/ P. 14
? 2009 TSMC, Ltd.
Proprietary & Confidential C
Dummy filling flow & Timing Fixing
APR APR
Add Exclusive layer Add Exclusive layer at clock nets at clock nets
RC RCextraction extraction
STA STA
GDS Timing violations
Calibre Calibre
Dummy GDS
? 2009 TSMC, Ltd
ECO ECO
DTP/ P. 15
? 2009 TSMC, Ltd.
(Fi i
Proprietary & Confidential C
Dummy Fill Guidelines
z In a cell-based design area, it’s recommended to use filler cell with DPO/DOD for empty area (please refer TSMC N90 standard cell library). z It’s recommended to use TSMC fill utility for macro block and chip top level for final GDSII to guarantee global uniformity. z If using TSMC fill utility for DM and DOD, low densities violations could be waived by TSMC PE. Otherwise, all densities rules should be met. z Do dummy fill in a bottom-up approach.
?
Macro block meet rules and timing first, then chip level.
? 2009 TSMC, Ltd
DTP/ P. 16
? 2009 TSMC, Ltd.
Macro IP Dummy Fill Timing Flow
N90 Dummy Mx utility DMx GDSII GDS Merge N90 Dummy PO,OD utility DPO, DOD GDSII Dummy GDSII
Proprietary & Confidential C
Make dummy top cell name the same as IP top cell for StarRC-XT
Original IP GDSII Milkyway Database LVS/LPE by Hercules LPE Netlist (device) RCX by Star-RCXT RCX Netlist (device+RC)
GDS Merge
Final IP GDSII
Post-layout Simulation
*mky.gds.map OD 6 1 poly 17 1 metal1 31 1 metal2 32 1 … metal1 31 7 metal2 32 7 …
* Star-RCXT command file METAL_FILL_GDS_FILE: dummy.gds GDS_LAYER_MAP_FILE: mky.gds.map METAL_FILL_POLYGON_HANDLING: FLOAT
? 2009 TSMC, Ltd
DTP/ P. 17
? 2009 TSMC, Ltd.
Top (Digital) Dummy Fill Timing Flow
N90 Dummy Mx utility Chip GDSII N90 Dummy PO,OD utility DPO, DOD GDSII DMx GDSII GDS Merge Dummy GDSII
Proprietary & Confidential C
Make dummy top cell name the same as chip top cell for StarRC-XT
GDS Merge
Final chip GDSII
P&R Milkyway Database
RCX by Star-RCXT
SPEF w/ dummy impact
Sign-off STA
*mky.gds.map
ECO
* Star-RCXT command file METAL_FILL_GDS_FILE: dummy.gds GDS_LAYER_MAP_FILE: mky.gds.map METAL_FILL_POLYGON_HANDLING: FLOAT
? 2009 TSMC, Ltd
OD 6 1 poly 17 1 metal1 31 1 metal2 32 1 … metal1 31 7 metal2 32 7 …
DTP/ P. 18
? 2009 TSMC, Ltd.
Others: High-Speed Clocks
Top-view
M3/M5
Proprietary & Confidential C
M4
M2/M4
End-view
Clock net
Clock Net
VIA34
M3
M3
? 2009 TSMC, Ltd
DTP/ P. 19
? 2009 TSMC, Ltd.
Shielding Net
Signoff Task vs. EDA Tool
Task
ATPG Floor plan Placement/CTS/Route
EDA Tool
Tmax/fastscan Astro/SOC encounter Astro/SOC encounter Celtic StarRC
Major Role
Floor plan environment Placement/CTS/Route tool Xtalk analysis RC extraction
Proprietary & Confidential C
Vector generation/simulation
Design tool
SI RC extraction
Netlist Handoff LEC ( Verplex ) Static IR Dynamic IR Power EM
Spyglass & Prime Time LEC Voltage Storm RedHawk Voltage Storm Astro/CISD utility Prime Time Calibre/Laker/Virtuoso Calibre/Laker/Virtuoso Calibre/Hermcules Calibre/Hercules
Sanity Check formal validation Static IR drop analysis Dynamic IR drop analysis Power Ring reliability issue Signal wire reliability issue Static timing analysis Yield improvement Yield improvement Antenna effect check TSMC design rule checks
Signoff
Signal EM STA w/ Incr. SDF Redundant via insertion Dummy metal insertion Antenna
? 2009 TSMC, Ltd
DRC/LVS/ERC
DTP/ P. 20
? 2009 TSMC, Ltd.