//ASK调制模块
module ASK(clk,reset,x,y);
input clk;
input reset;
input x;
output y;
//cnt是分频计数器
reg [1:0]cnt;
//carriers是要调制的载波信号，将输入信号clk经过4分频后得到
reg carriers;
always @(posedge clk)begin
if(!reset)begin
cnt <= 2'b00;
carriers <= 0;
end
else begin
if(cnt == 2'b11)begin
cnt <= 2'b00;
carriers <= ~carriers;
end
else begin
carriers <= carriers;
cnt <= cnt+1;
end
end
end
assign y = x&carriers;
endmodule
//ASK的解调模块
module DE_ASK(clk,reset,x,y);
input clk;
input reset;
input x;
output y;
reg y;
reg [2:0] cnt;
reg [2:0] m;
always @(posedge clk)begin
if(!reset) begin
cnt <= 3'b000;
end
else if(cnt == 3'b111)
cnt <= 3'b000;
else
cnt <= cnt+1;
end
always @(posedge x)begin
if(!reset) begin
m <= 3'b000;
end
else begin
if(cnt == 3'b110)begin
if(m == 3'b010)
y <= 1'b0;
else
y <= 1'b1;
m <= 3'b000;
end
else
m <= m+1;
end
end
endmodule