2K x 8 Dual-Port Static RAM
CY7C142/CY7C146
Features
?True Dual-Ported memory cells which allow simulta-neous reads of the same memory location ?2K x 8 organization
?0.65-micron CMOS for optimum speed/power ?High-speed access: 15 ns
?Low operating power: I CC = 110 mA (max.)?Fully asynchronous operation ?Automatic power-down
?Master CY7C132/CY7C136 easily expands data bus width to 16 or more bits using slave CY7C142/CY7C146?BUSY output flag on CY7C132/CY7C136; BUSY input on CY7C142/CY7C146
?INT flag for port-to-port communication (52-pin PLCC/PQFP versions)
?Available in 48-pin DIP (CY7C132/142), 52-pin PLCC and 52-pin TQFP (CY7C136/146)?Pb-Free packages available
Functional Description
The CY7C132/CY7C136/CY7C142 and CY7C146 are high-speed CMOS 2K by 8 dual-port static RAMs. Two ports are provided to permit independent access to any location in memory. The CY7C132/ CY7C136 can be utilized as either a standalone 8-bit dual-port static RAM or as a MASTER dual-port RAM in conjunction with the CY7C142/CY7C146SLAVE dual-port device in systems requiring 16-bit or greater word widths. It is the solution to applications requiring shared or buffered data such as cache memory for DSP , bit-slice, or multiprocessor designs.
Each port has independent control pins; chip enable (CE),write enable (R/W), and output enable (OE). BUSY flags are provided on each port. In addition, an interrupt flag (INT) is provided on each port of the 52-pin PLCC version. BUSY signals that the port is trying to access the same location currently being accessed by the other port. On the PLCC version, INT is an interrupt flag indicating that data has been placed in a unique location (7FF for the left port and 7FE for the right port).
An automatic power-down feature is controlled independently on each port by the chip enable (CE) pins.
The CY7C132/CY7C142 are available in 48-pin DIP . The CY7C136/CY7C146 are available in 52-pin PLCC and PQFP .
Notes:
1.CY7C132/CY7C136 (Master): BUSY is open drain output and requires pull-up resistor. CY7C142/CY7C146 (Slave): BUSY is input.
2.Open drain outputs; pull-up resistor required.
Logic Block Diagram
Pin Configuration
1314151617181920212223262728323130293336353424
25
GND
R/W L BUSY L
CE L OE L
A 10L A 0L
A 0R
A 10R R/W R CE R OE R
CE R OE R CE L OE L R/W L
R/W R
I/O 7L I/O 0L
I/O 7R I/O 0R
BUSY R INT L INT R
ARBITRA TION
LOGIC
(7C132/7C136ONLY)
AND
INTERRUPTLOGIC (7C136/7C146ONLY)
CONTROL I/O CONTROL
I/O MEMORY ARRAY
ADDRESS DECODER
ADDRESS
DECODER
1234567891011
38394044434241454847461237R/W L CE L BUSY L A 10L OE L A 0L A 1L A 2L A 3L A 4L A 5L A 6L A 7L A 8L A 9L I/O 0L I/O 1L I/O 2L I/O 3L I/O 4L I/O 5L I/O 6L I/O 7L CE R R/W R BUSY R A 10R OE R A 0R A 1R A 2R A 3R A 4R A 5R A 6R A 7R A 8R A 9R I/O 7R I/O 6R I/O 5R I/O 4R I/O 3R I/O 2R I/O 1R I/O 0R
V CC DIP Top View
7C1327C142[1][2]
[2]
[1]
Pin Configurations
Selection Guide
7C136-15[3]7C146-157C132-25[3]7C136-25
7C142-257C146-25
7C132-307C136-307C142-307C146-30
7C132-357C136-357C142-357C146-35
7C132-457C136-457C142-457C146-45
7C132-557C136-557C142-557C146-55
Unit Maximum Access Time
152530354555ns Maximum Operating Current Com’l/Ind 190170170120120110mA Maximum Operating Current Military 170170120mA Maximum Standby Current
Com’l/Ind 75
65
65
454535mA
Military
65
65
45
Shaded areas contain preliminary information.
Note:
3.15 and 25-ns version available in PQFP and PLCC packages only.
1V C C
Top View
PLCC R A 0R 891011121314151617181920
464544434241
40393837363534
21222324252627282930313233
765432525150494847
A 1R A 2R A 3R A 4R A 5R A 6R A 7R A 8R A 9R NC I/O 7R
A 1L
A 2L A 3L A 4L A 5L A 6L A 7L A 8L A 9L I/O 0L I/O 1L I/O 2L I/O 3L
I /O I /O I /O I /O I /O I /O I /O I /O I /O I /O I /O 4L 5L
6L 7L
0R 1R
2R 3R 4R
5R 6R
N C G N D
O E B U S Y I N T A R /W C E R /W B U S Y I N T 0L
L L L
L L C E R R R R
7C136
7C146
4612345678910111213
39383736353433323130292827
14151617181920212223242526
5251 50494847454443424140
Top View
PQFP
V C C
O E B U S Y I N T A R /W C E R /W B U S Y I N T 0L
L L L
L L C E R R R R
OE R A 0R A 1R A 2R A 3R A 4R A 5R A 6R A 7R A 8R A 9R NC I/O 7R
A 1L A 2L A 3L A 4L A 5L A 6L A 7L A 8L A 9L I/O 0L I/O 1L I/O 2L I/O 3L
I /O I /O I /O I /O I /O I /O I /O I /O I /O I /O I /O 4L 5L
6L 7L
0R 1R
2R 3R 4R
5R 6R
N C G N D 7C1367C146
A 10L
A 10R
A 10L
A 10R
Maximum Ratings
(Above which the useful life may be impaired. For user guide-lines, not tested.)
Storage Temperature .....................................?65°C to +150°C Ambient Temperature with
Power Applied..................................................?55°C to +125°C Supply Voltage to Ground Potential
(Pin 48 to Pin 24).................................................?0.5V to +7.0V DC Voltage Applied to Outputs
in High-Z State.....................................................?0.5V to +7.0V DC Input Voltage.................................................?3.5V to +7.0V Output Current into Outputs (LOW).............................20 mA Static Discharge Voltage.......................................... > 2001V (per MIL-STD-883, Method 3015)
Latch-up Current.................................................... > 200 mA Operating Range
Range Ambient Temperature V CC Commercial0°C to +70°C 5V ± 10% Industrial–40°C to +85–C 5V ± 10% Military[4]–55°C to +125°C 5V ± 10%
Electrical Characteristics Over the Operating Range[5]
Parameter Description Test Conditions 7C136-15[3]
7C146-15
7C132-30[3]
7C136-25,30
7C142-30
7C146-25,30
7C132-35,45
7C136-35,45
7C142-35,45
7C146-35,45
7C132-55
7C136-55
7C142-55
7C146-55
Unit Min.Max.Min.Max.Min.Max.Min.Max.
V OH Output HIGH voltage V CC = Min., I OH = –4.0 mA 2.4 2.4 2.4 2.4V V OL Output LOW voltage I OL = 4.0 mA0.40.40.40.4V
I OL = 16.0 mA[6]0.50.50.50.5
V IH Input HIGH voltage 2.2 2.2 2.2 2.2V V IL Input LOW voltage0.80.80.80.8V I IX Input load current GND < V I < V CC–5+5?5+5?5+5?5+5μA I OZ Output leakage
current
GND < V O < V CC, Output Disabled–5+5?5+5?5+5?5+5μA
I OS Output short circuit
current[7]
V CC = Max., V OUT = GND–350?350?350?350mA
I CC V CC Operating
Supply Current CE = V IL, Outputs Open, f =
f MAX[8]
Com’l190170120110mA
Mil170120
I SB1Standby current both
ports, TTL Inputs CE L and CE R > V IH,
f = f MAX[8]
Com’l75654535mA
Mil6545
I SB2Standby Current
One Port,
TTL Inputs CE L or CE R > V IH,
Active Port Outputs Open,
f = f MAX[8]
Com’l1351159075mA
Mil11590
I SB3Standby Current
Both Ports,
CMOS Inputs Both Ports CE L and
CE R > V CC – 0.2V,
V IN > V CC – 0.2V or
V IN < 0.2V, f = 0
Com’l15151515mA
Mil1515
I SB4Standby Current
One Port,
CMOS Inputs One Port CE L or CE R > V CC –
0.2V, V IN > V CC – 0.2V or V IN <
0.2V, Active Port Outputs Open,
f = f MAX[8]
Com’l1251058570mA
Mil10585
Capacitance[9]
Parameter Description Test Conditions Max.Unit
C IN Input Capacitance T A = 25°C, f = 1 MHz,
V CC = 5.0V 15pF
C OUT Output Capacitance10pF Shaded areas contain preliminary information.
Notes:
4.T A is the “instant on” case temperature.
5.See the last page of this specification for Group A subgroup testing information.
6.
7.Duration of the short circuit should not exceed 30 seconds.
8.At f = f MAX, address and data inputs are cycling at the maximum frequency of read cycle of 1/t rc and using AC Test Waveforms input levels of GND to 3V.
9.This parameter is guaranteed but not tested.
AC Test Loads and Waveforms
Switching Characteristics Over the Operating Range (Speeds -15, -25, -30)[5, 10]
Parameter Description
7C136-15[3]7C146-15
7C132-25[3]7C136-257C142-257C146-257C132-307C136-307C142-307C146-30Unit
Min.
Max.
Min.
Max.
Min.
Max.
Read Cycle t RC Read Cycle Time 15
25
30
ns t AA Address to Data Valid [11]
15
25
30
ns t OHA Data Hold from Address Change 0
ns t ACE CE LOW to Data Valid [11]152530ns t DOE OE LOW to Data Valid [11]10
15
20
ns t LZOE OE LOW to Low Z [9, 12]3
3
3
ns t HZOE OE HIGH to High Z [9, 12, 13]10
15
15
ns t LZCE CE LOW to Low Z [9, 12]3
5
5
ns t HZCE CE HIGH to High Z [9, 12, 13]10
15
15
ns t PU CE LOW to Power-Up [9]0
ns t PD
CE HIGH to Power-Down [9]
15
25
25
ns
Write Cycle [14]t WC Write Cycle Time 152530ns t SCE CE LOW to Write End 122025ns t AW Address Set-up to Write End 122025ns t HA Address Hold from Write End 222ns t SA Address Set-up to Write Start 000ns t PWE R/W Pulse Width 121525ns t SD Data Set-up to Write End 101515ns t HD Data Hold from Write End 0
ns t HZWE R/W LOW to High Z [9]10
15
15
ns t LZWE
R/W HIGH to Low Z [9]
000ns
Shaded areas contain preliminary information.Notes:
10.Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading of the specified
I OL /I OH, and 30-pF load capacitance.
11.AC test conditions use V OH = 1.6V and V OL = 1.4V.
12.At any given temperature and voltage condition for any given device, t HZCE is less than t LZCE and t HZOE is less than t LZOE .
13.t LZCE , t LZWE , t HZOE , t LZOE, t HZCE, and t HZWE are tested with C L = 5pF as in (b) of AC Test Loads . Transition is measured ±500 mV from steady-state voltage.14.The internal write time of the memory is defined by the overlap of CE LOW and R/W LOW. Both signals must be LOW to initiate a write and either signal can
terminate a write by going HIGH. The data input setup and hold timing should be referenced to the rising edge of the signal that terminates the write.
3.0V 5V OUTPUT
R1 893?
R2347?
30pF INCLUDING JIG AND SCOPE GND
90%
90%10%
<5ns
<5ns
5V OUTPUT
R1 893?
R2347?
5pF
INCLUDING JIG AND SCOPE
(a)
(b)
OUTPUT
1.4V
Equivalent to:
TH éVENIN EQUIVALENT
5V 281?
30 pF
BUSY OR INT
(CY7C132/CY7C136 Only)
10%
ALL INPUT PULSES 250?
Busy/Interrupt Timing t BLA BUSY LOW from Address Match 152020ns t BHA BUSY HIGH from Address Mismatch [15]152020ns t BLC BUSY LOW from CE LOW 152020ns t BHC BUSY HIGH from CE HIGH [15]15
20
20
ns t PS Port Set Up for Priority 555ns t WB R/W LOW after BUSY LOW [16]000ns t WH R/W HIGH after BUSY HIGH 13
20
30
ns t BDD BUSY HIGH to Valid Data
152530ns t DDD Write Data Valid to Read Data Valid Note 17Note 17Note 17ns t WDD Write Pulse to Data Delay Note 17Note 17Note 17ns Interrupt Timing [18]
t WINS R/W to INTERRUPT Set Time 152525ns t EINS CE to INTERRUPT Set Time 152525ns t INS Address to INTERRUPT Set Time 152525ns t OINR OE to INTERRUPT Reset Time [15]152525ns t EINR CE to INTERRUPT Reset Time [15]152525ns t INR
Address to INTERRUPT Reset Time [15]
152525ns
Switching Characteristics Over the Operating Range (Speeds -35, -45, -55)[5, 10]
Parameter Description
7C132-357C136-357C142-357C146-35
7C132-457C136-457C142-457C146-457C132-557C136-557C142-557C146-55Unit
Min.
Max.
Min.
Max.
Min.
Max.
Read Cycle t RC Read Cycle Time 35
45
55
ns t AA Address to Data Valid [11]
35
45
55
ns t OHA Data Hold from Address Change 0
ns t ACE CE LOW to Data Valid [11]354555ns t DOE OE LOW to Data Valid [11]20
25
25
ns t LZOE OE LOW to Low Z [9, 12]3
3
3
ns t HZOE OE HIGH to High Z [9, 12, 13]20
20
25
ns t LZCE CE LOW to Low Z [9, 12]5
5
5
ns t HZCE CE HIGH to High Z [9, 12, 13]20
20
25
ns t PU CE LOW to Power-Up [9]0
ns t PD
CE HIGH to Power-Down [9]
35
35
35
ns
Notes:
15.These parameters are measured from the input signal changing, until the output pin goes to a high-impedance state.16.CY7C142/CY7C146 only.
17.A write operation on Port A, where Port A has priority, leaves the data on Port B’s outputs undisturbed until one access time after one of the following:
BUSY on Port B goes HIGH.Port B’s address toggled.CE for Port B is toggled.
18.52-pin PLCC and PQFP versions only.
Switching Characteristics Over the Operating Range (Speeds -15, -25, -30) (continued)[5, 10]
Parameter
Description
7C136-15[3]7C146-15
7C132-25[3]7C136-257C142-257C146-257C132-307C136-307C142-307C146-30Unit
Min.
Max.
Min.
Max.
Min.
Max.
Write Cycle [14]t WC Write Cycle Time 354555ns t SCE CE LOW to Write End 303540ns t AW Address Set-up to Write End 303540ns t HA Address Hold from Write End 222ns t SA Address Set-up to Write Start 000ns t PWE R/W Pulse Width 253030ns t SD Data Set-up to Write End 152020ns t HD Data Hold from Write End
ns
t HZWE R/W LOW to High Z [9]20
20
25
ns t LZWE R/W HIGH to Low Z [9]
ns
Busy/Interrupt Timing
t BLA
BUSY LOW from Address Match
202530ns t BHA
BUSY HIGH from Address Mismatch [15]202530ns t BLC
BUSY LOW from CE LOW 202530ns t BHC BUSY HIGH from CE HIGH [15]20
25
30
ns t PS Port Set Up for Priority 555ns t WB R/W LOW after BUSY LOW [16]000ns t WH R/W HIGH after BUSY HIGH 30
3535
ns
t BDD BUSY HIGH to Valid Data
354545ns t DDD Write Data Valid to Read Data Valid Note 17Note 17Note 17ns t WDD Write Pulse to Data Delay Note 17Note 17Note 17ns Interrupt Timing [18]
t WINS R/W to INTERRUPT Set Time 253545ns t EINS CE to INTERRUPT Set Time 253545ns t INS Address to INTERRUPT Set Time 253545ns t OINR OE to INTERRUPT Reset Time [15]253545ns t EINR CE to INTERRUPT Reset Time [15]253545ns t INR
Address to INTERRUPT Reset Time [15]
25
35
45
ns
Switching Characteristics Over the Operating Range (Speeds -35, -45, -55) (continued)[5, 10]
Parameter Description
7C132-357C136-357C142-357C146-35
7C132-457C136-457C142-457C146-457C132-557C136-557C142-557C146-55Unit Min.Max.
Min.Max.
Min.Max.
Switching Waveforms
Read Cycle No. 1 (Either Port-Address Access)[19, 20]
Read Cycle No. 2 (Either Port-CE/OE)[19, 21]
Read Cycle No. 3 (Read with BUSY Master: CY7C132 and CY7C136)
Notes:
19.20.Device is continuously selected, CE = V IL and OE = V IL .21.t RC
t AA
t OHA
DATA VALID
PREVIOUS DATA VALID
DATA OUT
ADDRESS
t ACE
t LZOE
t DOE
t HZOE
t HZCE
DATA VALID
DATA OUT
CE OE
t LZCE
t PU
I CC I SB
t PD
t BHA
t BDD
VALID
t DDD
t WDD
ADDRESS MATCH
ADDRESS MATCH
R/W R ADDRESS R
D INR
ADDRESS L
BUSY L
DOUT L
t PS
t BLA
t RC
t PWE
VALID
Write Cycle No.1 (OE Three-States Data I/Os—Either Port)[14, 22]
Write Cycle No. 2 (R/W Three-States Data I/Os—Either Port)[14, 23]
Notes:
22.PWE or t HZWE + t SD to allow the data I/O pins to enter high impedance
and for data to be placed on the bus for the required t SD .
23.If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in a high-impedance state.
Switching Waveforms (continued)
t AW
t WC
DATA VALID
HIGH IMPEDANCE
t SCE
t SA
t PWE
t HD
t SD
t HA
t HZOE
CE
R/W
ADDRESS
OE
D OUT
DATA IN
t AW
t WC
t SCE
t SA
t PWE
t HD
t SD
t HZWE
t HA
HIGH IMPEDANCE
CE
R/W
ADDRESS
D OUT
DATA IN
t LZWE
DATA VALID
Busy Timing Diagram No. 1 (CE Arbitration)Busy Timing Diagram No. 2 (Address Arbitration)Switching Waveforms (continued)
ADDRESS MATCH
t PS
CE L Valid First:
t BLC
t BHC
ADDRESS MATCH
t PS
t BLC
t BHC
BUSY L
CE R
CE L
ADDRESS L,R
BUSY R
CE L
CE R
ADDRESS L,R
CE R Valid First:
Left Address Valid First:
ADDRESS MATCH t PS
ADDRESS L
BUSY R
ADDRESS MISMATCH
t RC or t WC
t BLA
t BHA
ADDRESS R
ADDRESS MATCH ADDRESS MISMATCH
t PS
ADDRESS L
BUSY L
t RC or t WC
t BLA
t BHA
ADDRESS R
Right Address Valid First:
Busy Timing Diagram No. 3 (Write with BUSY, Slave: CY7C142/CY7C146)
Interrupt Timing Diagrams [18]
Left Side Sets INT R :
Right Side Clears INT R :
Right Side Sets INT L :
Switching Waveforms (continued)
t PWE
t WB
t WH
BUSY
R/W
CE
WRITE 7FF
t INS
ADDRESS L
R/W L
t WC
t EINS CE L t HA
t SA
t WINS
INT R
READ 7FF t RC
t EINR
t HA
t INR
t OINR
ADDRESS R
CE R
R/W R INT R
OE R WRITE 7FE
t INS
ADDRESS R
R/W R t WC
t EINS CE R t HA
t SA
t WINS
INT L
Right Side Clears INT L :
Interrupt Timing Diagrams [18] (continued)
READ 7FE t EINR
t HA
t INR
t OINR
ADDRESS L
CE L
R/W L INT L
OE L
t RC
Typical DC and AC Characteristics
1.41.00.44.0
4.5
5.0
5.5
6.0
–55
25
125
1.21.0120100806040200
1.0
2.0
3.0
4.0
O U T P U T S O U R C E C U R R E N T (m A )
SUPPLY VOLTAGE (V)NORMALIZED SUPPLY CURRENT vs. SUPPLY VOLTAGE
NORMALIZED SUPPLY CURRENT vs. AMBIENT TEMPERATURE AMBIENT TEMPERATURE (°C)OUTPUT VOLTAGE (V)
OUTPUT SOURCE CURRENT vs. OUTPUT VOLTAGE 0.00.80.80.60.6N O R M A L I Z E D I C C , I S B
V CC = 5.0V V IN = 5.0V T A = 25°C
0I CC
I CC
1.61.41.21.0
0.8–55
125
N O R M A L I Z E D t A A
NORMALIZED ACCESS TIME vs. AMBIENT TEMPERATURE AMBIENT TEMPERATURE (°C)1.41.31.21.00.94.0
4.5
5.0
5.5
6.0
N O R M A L I Z E D t A A
SUPPLY VOLTAGE (V)
NORMALIZED ACCESS TIME vs. SUPPLY VOLTAGE 120140*********
0.0
1.0
2.0
3.0
4.0
O U T P U T S I N K C U R R E N T (m A )
080OUTPUT VOLTAGE (V)OUTPUT SINK CURRENT vs. OUTPUT VOLTAGE
0.60.8 1.251.0
0.75
10
40
N O R M A L I Z E D I C C
0.50
NORMALIZED I CC vs. CYCLE TIME CYCLE FREQUENCY (MHz)
3.02.52.01.50.50
1.0
2.0
3.0
5.0
N O R M A L I Z E D t P C
25.030.020.010.05.00
200400600800D E L T A t A A (n s )015.00.0
SUPPLY VOLTAGE (V)
TYPICAL POWER-ON CURRENT vs. SUPPLY VOLTAGE CAPACITANCE (pF)
TYPICAL ACCESS TIME CHANGE vs. OUTPUT LOADING
4.0
10001.020
30
0.20.61.2I SB3
0.20.4I SB3
251.1V IN = 0.5V N O R M A L I Z E D I C C , I S B
V CC = 5.0V T A = 25°C
V CC = 5.0V
V CC = 5.0V T A = 25°C
T A = 25°C
V CC = 4.5V V CC = 5.0V T A = 25°C
Ordering Information
Speed
(ns)Ordering Code Package
Name Package Type
Operating
Range
30CY7C132-30PC P2548-Lead (600-Mil) Molded DIP Commercial CY7C132-30PI P2548-Lead (600-Mil) Molded DIP Industrial 35CY7C132-35PC P2548-Lead (600-Mil) Molded DIP Commercial CY7C132-35PI P2548-Lead (600-Mil) Molded DIP Industrial CY7C132-35DMB D2648-Lead (600-Mil) Sidebraze DIP Military
45CY7C132-45PC P2548-Lead (600-Mil) Molded DIP Commercial CY7C132-45PI P2548-Lead (600-Mil) Molded DIP Industrial CY7C132-45DMB D2648-Lead (600-Mil) Sidebraze DIP Military
55CY7C132-55PC P2548-Lead (600-Mil) Molded DIP Commercial CY7C132-55PI P2548-Lead (600-Mil) Molded DIP Industrial CY7C132-55DMB D2648-Lead (600-Mil) Sidebraze DIP Military
15CY7C136-15JC J6952-Lead Plastic Leaded Chip Carrier Commercial CY7C136-15NC N5252-Pin Plastic Quad Flatpack
25CY7C136-25JC J6952-Lead Plastic Leaded Chip Carrier Commercial CY7C136-25JXC J6952-Lead Pb-Free Plastic Leaded Chip Carrier
CY7C136-25NC N5252-Pin Plastic Quad Flatpack
CY7C136-25NXC N5252-Pin Pb-Free Plastic Quad Flatpack
30CY7C136-30JC J6952-Lead Plastic Leaded Chip Carrier Commercial CY7C136-30NC N5252-Pin Plastic Quad Flatpack
CY7C136-30JI J6952-Lead Plastic Leaded Chip Carrier Industrial 35CY7C136-35JC J6952-Lead Plastic Leaded Chip Carrier Commercial CY7C136-35NC N5252-Pin Plastic Quad Flatpack
CY7C136-35JI J6952-Lead Plastic Leaded Chip Carrier Industrial CY7C136-35LMB L6952-Square Leadless Chip Carrier Military
45CY7C136-45JC J6952-Lead Plastic Leaded Chip Carrier Commercial CY7C136-45NC N5252-Pin Plastic Quad Flatpack
CY7C136-45JI J6952-Lead Plastic Leaded Chip Carrier Industrial CY7C136-45LMB L6952-Square Leadless Chip Carrier Military
55CY7C136-55JC J6952-Lead Plastic Leaded Chip Carrier Commercial CY7C136-55JXC J6952-Lead Pb-Free Plastic Leaded Chip Carrier
CY7C136-55NC N5252-Pin Plastic Quad Flatpack
CY7C136-55NXC N5252-Pin Pb-Free Plastic Quad Flatpack
CY7C136-55JI J6952-Lead Plastic Leaded Chip Carrier Industrial CY7C136-55JXI J6952-Lead Pb-Free Plastic Leaded Chip Carrier
CY7C136-55NI N5252-Pin Plastic Quad Flatpack
CY7C136-55NXI N5252-Pin Pb-Free Plastic Quad Flatpack
CY7C136-55LMB L6952-Square Leadless Chip Carrier Military
30CY7C142-30PC P2548-Lead (600-Mil) Molded DIP Commercial CY7C142-30PI P2548-Lead (600-Mil) Molded DIP Industrial 35CY7C142-35PC P2548-Lead (600-Mil) Molded DIP Commercial CY7C142-35PI P2548-Lead (600-Mil) Molded DIP Industrial CY7C142-35DMB D2648-Lead (600-Mil) Sidebraze DIP Military
45
CY7C142-45PC P2548-Lead (600-Mil) Molded DIP Commercial CY7C142-45PI P2548-Lead (600-Mil) Molded DIP Industrial CY7C142-45DMB
D2648-Lead (600-Mil) Sidebraze DIP Military 55
CY7C142-55PC P2548-Lead (600-Mil) Molded DIP Commercial CY7C142-55PI P2548-Lead (600-Mil) Molded DIP Industrial CY7C142-55DMB
D2648-Lead (600-Mil) Sidebraze DIP Military 15CY7C146-15JC J6952-Lead Plastic Leaded Chip Carrier Commercial
CY7C146-15NC N5252-Pin Plastic Quad Flatpack 25
CY7C146-25JC J6952-Lead Plastic Leaded Chip Carrier Commercial CY7C146-25JXC J6952-Lead Pb-Free Plastic Leaded Chip Carrier CY7C146-25NC
N5252-Pin Plastic Quad Flatpack 30
CY7C146-30JC J6952-Lead Plastic Leaded Chip Carrier Commercial CY7C146-30NC N5252-Pin Plastic Quad Flatpack CY7C146-30JI
J6952-Lead Plastic Leaded Chip Carrier Industrial 35
CY7C146-35JC J6952-Lead Plastic Leaded Chip Carrier Commercial CY7C146-35NC N5252-Pin Plastic Quad Flatpack CY7C146-35JI J6952-Lead Plastic Leaded Chip Carrier Industrial CY7C146-35LMB
L6952-Square Leadless Chip Carrier Military 45
CY7C146-45JC J6952-Lead Plastic Leaded Chip Carrier Commercial CY7C146-45NC N5252-Pin Plastic Quad Flatpack CY7C146-45JI J6952-Lead Plastic Leaded Chip Carrier Industrial CY7C146-45LMB
L6952-Square Leadless Chip Carrier Military 55
CY7C146-55JC J6952-Lead Plastic Leaded Chip Carrier Commercial CY7C146-55JXC J6952-Lead Pb-Free Plastic Leaded Chip Carrier CY7C146-55NC N5252-Pin Plastic Quad Flatpack CY7C146-55JI J6952-Lead Plastic Leaded Chip Carrier Industrial CY7C146-55LMB
L69
52-Square Leadless Chip Carrier
Military Ordering Information (continued)
Speed (ns)Ordering Code Package Name Package Type
Operating Range
MILITARY SPECIFICATIONS
Group A Subgroup Testing—DC Characteristics Parameter Subgroups
V OH1, 2, 3
V OL1, 2, 3
V IH1, 2, 3
V IL Max.1, 2, 3
I IX1, 2, 3
I OZ1, 2, 3
I CC1, 2, 3
I SB11, 2, 3
I SB21, 2, 3
I SB31, 2, 3
I SB41, 2, 3Switching Characteristics
Parameter Subgroups Read Cycle
t RC7, 8, 9, 10, 11
t AA7, 8, 9, 10, 11
t ACE7, 8, 9, 10, 11
t DOE7, 8, 9, 10, 11 Write Cycle
t WC7, 8, 9, 10, 11
t SCE7, 8, 9, 10, 11
t AW7, 8, 9, 10, 11
t HA7, 8, 9, 10, 11
t SA7, 8, 9, 10, 11
t PWE7, 8, 9, 10, 11
t SD7, 8, 9, 10, 11
t HD7, 8, 9, 10, 11 Busy/Interrupt Timing
t BLA7, 8, 9, 10, 11
t BHA7, 8, 9, 10, 11
t BLC7, 8, 9, 10, 11
t BHC7, 8, 9, 10, 11
t PS7, 8, 9, 10, 11
t WINS7, 8, 9, 10, 11
t EINS7, 8, 9, 10, 11
t INS7, 8, 9, 10, 11
t OINR7, 8, 9, 10, 11
t EINR7, 8, 9, 10, 11
t INR7, 8, 9, 10, 11 BUSY TIMING
t WB[24]7, 8, 9, 10, 11
t WH7, 8, 9, 10, 11
t BDD7, 8, 9, 10, 11 Note:
24.CY7C142/CY7C146 only.
Package Diagrams
48-Lead (600-Mil) Sidebraze DIP D26
MIL-STD-1835 D-14 Config. C
51-80044-**
51-85004-*A
52-Lead Pb-Free Plastic Leaded Chip Carrier J69
52-Lead Plastic Leaded Chip Carrier J69
Package Diagrams (continued)
52-Square Leadless Chip Carrier L69
51-80054-**
52-Lead Plastic Quad Flatpack N52
52-Lead Pb-Free Plastic Quad Flatpack N52
51-85042-**
Package Diagrams (continued)
48-Lead (600-Mil) Molded DIP P25
51-85020-*A
All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-06031 Rev. *C Page 17 of 18
Document History Page
Document Title: CY7C132/CY7C136/CY7C142/CY7C146 2K x 8 Dual Port Static RAM Document Number: 38-06031
REV.ECN NO.Issue Date Orig. of
Change Description of Change
**11017110/21/01SZV Change from Spec number: 38-06031
*A12895909/03/03JFU Added CY7C136-55NI to Order Information
*B236748See ECN YDT Removed cross information from features section
*C393184See ECN YIM Added Pb-Free Logo
Added Pb-Free parts to ordering information:
CY7C136-25JXC, CY7C136-25NXC, CY7C136-55JXC, CY7C136-55NXC,
CY7C136-55JXI, CY7C136-55NXI, CY7C146-25JXC, CY7C146-55JXC