JOURNAL OF ELECTRONIC TESTING:Theory and Applications11,197–209(1997)
c 1997Kluwer Academic Publishers.Manufacture
d in Th
e Netherlands.
Testability Properties of Divergent Trees?
R.D.(SHAWN)BLANTON
Center for Electronic Design Automation,ECE Department,Carnegie Mellon University,
Pittsburgh,PA15213-3890
blanton@https://www.doczj.com/doc/4d15045368.html,
JOHN P.HAYES
Advanced Computer Architecture Laboratory,EECS Department,University of Michigan,
Ann Arbor,MI48109-2122
jhayes@https://www.doczj.com/doc/4d15045368.html,
Received March20,1996;Revised June6,1997
Editor:A.Paschalis
Abstract.The testability of a class of regular circuits called divergent trees is investigated under a functional fault model.Divergent trees include such practical circuits as decoders and demultiplexers.We prove that uncontrolled divergent trees are testable with a?xed number of test patterns(C-testable)if and only if the module function is surjective.Testable controlled trees are also surjective but require sensitizing vectors for error propagation.We derive the conditions for testing controlled divergent trees with a test set whose size is proportional to the number of levels p found in the tree(L-testability).By viewing a tree as overlapping arrays of various types,we also derive conditions for a controlled divergent tree to be C-testable.Typical decoders/demultiplexers are shown to only partially satisfy L-and C-testability conditions but a design modi?cation that ensures L-testability is demonstrated. Keywords:fault detection,fault modeling,regular circuits,interactive logic arrays,structured circuits,test gen-eration
1.Introduction
It has long been recognized that regular logic cir-cuits,which are constructed from identical modules that are interconnected in a uniform fashion,are easier to test than irregular circuits.For example,the circuit of Fig.1(a)is an8-bit ripple-carry adder composed of eight identical modules(full adders)connected as a one-dimensional array.This adder is testable for all sin-gle stuck-line faults[1]with eight test patterns.These eight tests also detect any fault that alters the function of any single module in the circuit.This testing prop-?This research was supported by the National Science Foundation under Grant No.MIP–9503463.erty is true for an n-bit adder as well,that is,eight tests are required for a ripple-carry adder regardless of the number of modules in the array,a property known as C-testability[2].
The one-dimensional array adder of Fig.1(a)is a special case of a type of regular circuit called a tree.In general,trees are combinational logic circuits that have at most one path between any two input/output ports.
A path can contain single or multiple lines(buses). The modules or cells used to construct a tree circuit can have internal reconvergent fanout,but fanout is not allowed among the modules.Figure1(b)illustrates an 8-bit parity tree constructed from2-bit EXCLUSIVE-OR modules.For this tree,the size of the buses that interconnect the modules is one,and between any two
198Blanton and
Hayes
(a)
(b)
Fig.1.Examples of regular tree circuits:(a)an 8-bit ripple-carry adder and (b)an 8-bit parity circuit.
module ports there is only one path.One can easily see how the one-dimensional array structure of the adder results if the parity tree is restricted to a single module per level.
It is useful to extend the notion of a tree to make a distinction between data and control inputs.A tree with both data and control lines is called a controlled tree .The 3-to-8decoder circuit constructed from 1-to-2decoder (Dcd)modules and the demultiplexer circuit constructed from 1-to-2demultiplexer (Dmx)modules of Fig.2are examples of such a circuit.Tree circuits can be convergent,divergent,or neither,that is,
the
(a)
(b)
Fig.2.
Examples of divergent tree circuits:(a)a 1-to-8demultiplexer and (b)a 1-to-8decoder.
number of signal lines can increase,decrease or re-main the same as one moves from the primary inputs to outputs.The parity tree is an example of a tree that converges,while the decoder and demultiplexer trees are examples of divergent trees.The ripple-carry adder is a tree that neither diverges or converges.
In general,regular circuits are easy to test because the testing requirements for the circuit’s modules are identical and the regular interconnections allow tests for one module to be used on other modules.They also have other advantages.For example,because regular circuits are made by connecting identical modules in
Testability Properties of Divergent Trees 199
a regular fashion,large circuits are easy to build and have fewer design errors.The interconnection structure of regular circuits is also ideal for layout in a VLSI environment.As a result,they are used a great deal in large designs.For example,two-dimensional arrays and trees in the form of storage arrays,decoders,and multiplexers can be found in all memory designs.The testing properties of one-dimensional arrays have been studied extensively [2–4].In [2],the con-cept of C-testability was introduced,and conditions required for arrays without vertical outputs to be C-testable are presented.In [3],necessary and suf?cient conditions for the C-testability of unilateral and bilat-eral one-dimensional arrays with vertical outputs are presented.The authors of [4]present similar testing conditions to those in [3]along with conditions for lo-cating faulty modules within the array.The testability of two-dimensional arrays has been similarly investi-gated.For example,various sets of suf?cient condi-tions for the C-testability of two-dimensional arrays are presented in [5–7].In [8]and [9],C-testable two-dimensional array designs for multiplier and divider circuits respectively,are discussed.In [10],an auto-matic test pattern generator called NCUBE for two-dimensional arrays is described.The testing character-istics of systolic arrays have also been investigated in [11,12].Systolic arrays are one-and two-dimensional arrays and trees with buffer memory added to the cir-cuit’s modules.
Some research has addressed the testability of con-vergent trees [13–18],but there appears to be no work on divergent trees.In this paper,we examine the test-ing properties of divergent tree circuits like the de-coder and demultiplexers of Fig.2.The rest of this paper is organized as follows.Section 2presents our notation for describing the function and structure of divergent trees.The IP fault model adopted is then
(a)
Z l X i ,l ?X 1i ,l ?X 2i ,l 00000110100011
1
(b)
Fig.3.
(a)A 1-to-2demultiplexer module M i ,l and (b)the truth table for M i ,l .
de?ned and illustrated.The testability of uncontrolled and controlled divergent trees is analyzed under this fault model in Section 3.Section 4presents conditions for testing divergent trees with very few test patterns,while Section 5describes design methods for ensuring that these conditions are satis?ed.Finally,Section 6summarizes our results.2.
Function and Structure
An n -ary p -level divergent tree D (n ,p )is constructed from a set of identical modules arranged in p levels.Each module M i ,l has a single state input bus X ,an optional level-control input bus Z l ,and n state output
buses denoted ?X
1i ,l ,?X 2i ,l ,...,?X n i ,l ;see Fig.3(a).(The subscripts i ,l will only be used when the correspond-ing module name is ambiguous.)The word size for
X and each ?X
j is n x and the word size of Z l is n z .Thus,the set of values that can be assigned to X is I X ={0,1,...,2n x ?1},where each n x -bit value is denoted by a decimal number.Similarly,the set of val-ues assignable to Z l is I Z ={0,1,...,2n z ?1}.The set of possible output values that can be produced at
each state output ?X
j is also I X .The n state output functions ?X
j for 1≤j ≤n of the divergent tree module can be described by a com-posite truth table containing n output columns labeled
?X
1,?X 2,...,?X n .Each row r k and column ?X j entry speci?es an input pattern ip k =(v 0,v 1)and an out-put value v k .Here ip k denotes a control value v 0and a state input value v 1,while v k denotes the state out-put value produced at ?X
j when ip k is applied.Row k of the truth table thus de?nes the fault-free mapping
denoted ip k →v k at state output ?X
j or,equivalently,?X
j (i p k )=v k .A controlled n -ary p -level divergent tree CD (n ,p )has a control input bus Z l for each M i ,l in level l ,where
200Blanton and Hayes
1≤l ≤p .A controlled divergent tree is globally controlled if all Z l are connected together.A diver-gent tree is uncontrolled if no Z l is present.If a di-vergent tree has n p ?l modules on every level l ,then the tree is complete ,otherwise it is incomplete .Here,we only consider complete trees,but our results ap-ply to incomplete trees as well.Figure 3illustrates our notation for a module that represents a 1-to-2demulti-plexer.
We employ a special case of the input pattern (IP)fault model [19].The IP fault model assumes only a single module in the circuit can be faulty.All modules are assumed to be combinational,and the function of a faulty module is assumed to remain combinational,that is,no sequential behavior is allowed.No restriction is placed on the type or size of the module,making it possible to apply the IP model to circuits described at different design levels.
A fault f i that affects output ?X
k can change the re-sponse to an input pattern ip j from v j to v j ;we denote this change by ip j →(v j ,v j )k and refer to it as a sin-gle input pattern fault,or simply as an IP fault.The
pair of distinct state values (v k ,v
k
)denoting the good and faulty output values is the error corresponding to the IP fault.The IP fault model allows a single module to be affected by a single IP fault or a set of such faults (a multiple IP fault )F ={f 1,f 2,...,f q }.It is impor-tant to note that a multiple IP fault is not restricted to a
single state output ?X
k .The IP fault model can be customized for the testing application of concern.For example,in the special case where all single and multiple IP faults are assumed possible,the IP model becomes equivalent to the well-known cell fault model [20],where all modules are required to be tested pseudo-exhaustively.This special case of the IP fault model is advantageous in situations where the implementation details of the circuit modules are unknown.
The characteristics of the IP fault model are il-lustrated by the following example.Figure 4shows truth tables for all 16possible Boolean functions of Input Output columns (?X 1,?X 2)X 01234567891011121314150
00000000010101
0110101010111111111
0001
10
11
00
01
10
11
00
01
10
11
00
01
10
11
Fig.4.
The 16possible Boolean functions of a 1-bit uncontrolled divergent tree module.
an uncontrolled divergent tree module M i ,l with n =2
and n x =1.Assume both the ?X
1and ?X 2outputs of M i ,l implement the NOT function,which is de?ned by column 12of Fig.4.The remaining columns repre-sent all the possible faulty functions allowed by the IP fault model.For example,the faulty function of col-umn 11is easily described by the multiple IP fault F ={1→(0,1)1,0→(1,0)2,1→(0,1)2}.Notice that columns 0,4,8,13,14,and 15are the only faulty functions possible under the single stuck-line (SSL)fault model.(Under the SSL fault model [1],a sin-gle signal line in the circuit can either become perma-nently ?xed (stuck)at a logical 1or 0value.)Thus,the IP fault model is more general than the widely-used SSL model because it allows for many more faulty behaviors.
In this paper,we assume that a tree module can be affected by any single or multiple IP fault (i.e.,the cell fault model).This means a faulty divergent tree module can produce an erroneous output value at one or more of its n state outputs for one or more input patterns.Since error masking is not possible in a divergent tree (due to the absence of reconvergence),the set of (single and multiple)IP faults that affect a single state output X j for 1≤j ≤n are dominated by the set of all possible IP faults.Thus,we need only to explicitly consider IP
faults that affect a single output ?X
j for 1≤j ≤n .Moreover,the set of all multiple IP faults that affect a
single state output ?X
j dominate the set of all single IP faults that affect the same output ?X
j .Thus,adoption of the cell fault model only requires us to consider the set of all possible single IP faults that affect each state output.
The number of possible single IP faults for an n -output divergent tree module is nK (W ?1),where K =2n x +n z and W =2n x .Note that this number of faults is much smaller than the 2K nn x ?1possible faulty module functions.For example,the demulti-plexer module of Fig.3has 28?1=255different func-tional faults.The set of eight single IP faults for the
two state outputs ?X
1and ?X 2are shown in Fig.5.
Testability Properties of Divergent Trees201
?X1IP faults?X2IP faults
Z l X→(v k,v k)j Z l X→(v k,v k)j
00→(0,1)100→(0,1)2
01→(1,0)101→(0,1)2
10→(0,1)110→(0,1)2
11→(0,1)111→(1,0)2
Fig.5.The eight IP faults for the?X1and
?X2state outputs of the1-to-2demultiplexer
module of Fig.3.
3.Tree Testability
We now examine the testing properties of tree circuits.
A tree is testable for all single IP faults(and,therefore testable under the cell fault model)if each module in the tree can have every possible module input pattern applied to its inputs,and any resulting error can be propagated to the tree’s output.For uncontrolled trees, we derive both necessary and suf?cient conditions for testability.We then extend our fault model to controlled tree circuits and derive the necessary and suf?cient con-ditions for controlled divergent tree testability.
Uncontrolled Trees.We begin by de?ning the sur-jective property for a divergent tree module and then show how this property is both necessary and suf?cient for an uncontrolled divergent tree to be testable.
De?nition1.A divergent tree module is surjective if the set of output values produced at each?X j is I X,for 1≤j≤n.In other words,there is at least one occur-rence of every possible state output value in each output column of the module’s truth table.
Figure6shows two examples of binary(n=2)di-vergent tree modules.The module of Fig.6(a)is not surjective because state value3is absent from the?X2 output column.The second module of Fig.6(b)is sur-jective because both the?X1and?X2output columns con-tain all members of the set I X={0,1,2,3}.Notice that surjectivity in an uncontrolled divergent module implies that the state output functions are information lossless.This means that the output values produced by a module uniquely determines the input value ap-plied.This is true for the uncontrolled divergent tree module since it has the same number of signal lines for the state input X and each state output?X j.
Module D1
X?X1?X2
030
111
222
300
Module D2
X?X1?X2
002
110
223
331
(a)(b)
Fig.6.Truth tables for two uncontrolled di-
vergent modules:(a)D1which is not surjec-
tive and(b)D2which is surjective.
Theorem1.An n-ary p-level uncontrolled divergent tree D(n,p)is testable if and only if M i,l is surjective.
Proof:First,we show that the surjective property is necessary.Assume D(n,p)is testable but M i,l is not surjective.Then there is a state value v j∈I X that cannot be generated as an output value at some state output?X j. As a result,v j cannot be applied to the internal module M j,1connected to?X j1,1.Hence,D(n,p)cannot be fully tested unless M i,l is surjective.
Now we show that the surjective property is suf?-cient for testability.Assume the divergent tree module is surjective.Then every state output function is surjec-tive,so error propagation from the state input X to each state output?X is guaranteed.We now use induction on the number of levels p to show that each module input pattern ip j can be applied to all modules in D(n,p) using2n x test patterns.Obviously,all2n x input pat-terns can be applied to the1-level tree D(n,1)with 2n x tests.By the inductive hypothesis,assume2n x tests are suf?cient for a(p?1)-level tree D(n,p?1).A p-level tree can be viewed as a(p?1)-level tree with an additional level of modules connected to the outputs of D(n,p?1).D(n,p)is testable with the same2n x tests used for D(n,p?1)because the level-1surjective modules of D(n,p?1)produce all2n x input patterns for the new level-1modules of D(n,p).Thus by the principle of induction,all uncontrolled divergent trees D(n,p)with p≥1can have all module input patterns applied to every module with2n x tests.P
Example1.Reconsider the truth tables for the diver-gent tree modules of Fig.6.Module D1is not sur-jective and therefore does not satisfy the conditions of Theorem1.Figure7(a)shows how the state out-put value3,which is missing from?X2in Fig.6(a), prevents testability of a3-level uncontrolled divergent
202Blanton and Hayes
(a)(b)
Fig.7.Three-level uncontrolled divergent trees constructed from the modules de?ned in Fig.6:(a)D1and(b)D2.
tree.Module D2is surjective and therefore satis?es Theorem1.Figure7(b)shows the2n x=22=4test patterns that completely test a3-level uncontrolled di-vergent tree constructed from D2modules.These four test patterns also test an arbitrarily large tree of p levels.
Controlled Trees.The testing of a controlled tree is complicated by faults affecting the control input buses Z1,Z2,...,Z p.We assume that each control input bus Z l,1≤l≤p,can be affected by a set of“stuck-bus”faults,each of which is denoted Z l/v z,where v z∈I Z is some control input value.A control input fault Z l/v z causes the control input bus Z l of all modules M i,l in level l to be permanently?xed at v z.Because it af-fects more than one module,the fault Z l/v z is not cov-ered by our fault model.The inclusion of control input faults also subsumes SSL faults on the lines making up Z l.Thus,we de?ne a controlled divergent tree to be completely testable if each module M i,l in the tree can be tested for all its IP faults,and each level l can be tested for all its control input faults of the form Z l/v z.
A single-fault assumption is still made,in that only a single functional fault affecting a module or a single control input fault can occur.
We now turn our attention to the testability of controlled divergent trees.We de?ne the sensitizing property for these trees and then present conditions for testability.
De?nition2.A sensitizing vector for an error(v a,v b) on state input X of a divergent tree module is a control input value v0∈I Z such that?X j(v0,v a)=?X k(v0,v b) for some j=k.In other words,v0is a control value that causes at least two state outputs to produce different values when the error(v a,v b)is present on the state input.
Theorem2.An n-ary p-level controlled divergent tree C D(n,p)is testable if and only if M i,l is surjective and there exists a sensitizing vector for every possible error(v a,v b).
Here,we sketch the proof of Theorem2.The sur-jective condition,similar to Theorem1,is necessary and suf?cient for applying every input pattern to ev-ery module in an arbitrarily large tree.The sensitizing vector condition is required for propagating all possible errors to an output from any module within the tree. Figure8shows a truth table for a1-to-2decoder mod-ule function.A controlled divergent tree constructed from these modules is indeed testable because the errors(1,0)and(0,1)both have the sensitizing vec-tors Z l=1and Z l=0,and each?X j is surjective,that is,the values I X={0,1}appear in the output columns ?X1and?X2.Also note that any1-bit,1-to-n decoder will always be testable under the functional fault model since,by de?nition,each module output will be surjec-tive and the required sensitizing vectors must exist.
Z l X?X1?X2
0001
0111
1010
1111
Fig.8.Truth table
for the1-to-2decoder
module.
Testability Properties of Divergent Trees 203
4.Ef?cient Testing
We next examine two special properties called level-testability and C-testability that greatly reduce the num-ber of tests for a controlled divergent tree.
L-testability.Consider the problem of testing a tree for all IP faults using the smallest possible test set.The size of the required test set can be exponential in the number of levels in the tree.For example,consider the demultiplexer module de?ned in Fig.3.A p -level demultiplexer constructed from these modules requires 2p ?1different test patterns just for the set of SSL faults [15].
A tree is level-testable (L-testable)if all l -level mod-ules M i ,l can be simultaneously tested for any IP fault
ip k →(v k ,v k
)j
.Trees that are L-testable have a test set whose size is bounded by W ·p ,where W is a con-stant typically equal to the number of possible input patterns.
Theorem 3.An n-ary p-level controlled divergent tree CD (n ,p )is L-testable if and only if (1)there is a sensitizing vector for every error (v a ,v b );(2)for each v k ∈I X there is an input pattern ip k that produces
v k at each state output ?X
j ,for 1≤j ≤n ;and (3)for each control value v 1∈I Z there is a v 2∈I Z such
that subfunctions ?X
j (Z l =v 1)=?X k (Z l =v 2),for some 1≤j ,k ≤n.
The proof of Theorem 3is similar to that of Theorem 1.The sensitizing condition of Theorem 3insures error propagation while condition (2)is re-quired for simultaneously applying any given input pattern ip k to all modules on any single level.This ca-pability accompanied by the sensitizing condition (1)allows all level-l (for any l )modules to tested simul-taneously for all n (2n x ?1)possible single IP faults.Condition (3)is both necessary and suf?cient for test-ing control input faults.
Example 2.A truth table for a 1-to-2decoder func-tion different from Fig.8is shown in Fig.9.This de-coder module partially satis?es the conditions of The-orem 3.Condition (1)is satis?ed in that sensitizing vectors exist for the errors (0,1)and (1,0).Condi-tion (3)is satis?ed as well in that the subfunctions
?X
1(Z l =0)and ?X 2(Z l =1)are not equal,that is,?X
1(Z l =0)=?X 2(Z l =1).But condition (2)is only partially satis?ed.This condition states that for each v k ∈I X ={0,1}there must be an input pattern ip k that
Z l X ?X 1?X 200100111100111
1
1
Fig.9.Truth table for a 1-to-2decoder mod-ule.
IP faults
IP faults
Are the faults affecting ?X 1affecting ?X 2L-testable?
01→(1,0)1
01→(1,0)2
yes 11→(1,0)111→(1,0)2yes 00→(1,0)100→(0,1)2no 10→(0,1)1
10→(1,0)2
no
Fig.10.L-testability of the IP faults of the 1-to-2decoder function de?ned in Fig.9.
produces v k at ?X
1and ?X 2.This is true for v k =1but not for v k =0,that is,we have two input patterns,namely (Z l ,X )=(0,0)and (0,1),that produce 1at both state outputs but no input pattern that produces 0at both state outputs.
Since the testability of control faults only depends on conditions (1)and (3)of Theorem 3,we can con-clude that a decoder of any size composed of the 1-to-2decoder modules is testable for all control faults.We can also state that all IP faults involving the state input value 1are L-testable,but the IP faults requiring the state input value 0are not.Figure 10summarizes the L-testability of IP faults in this case.
Example 3.RTRAM is a RAM architecture designed to improve both testability and performance [21].It utilizes a complex decoder that has additional modes of operation beyond the normal decode function.Figure 11shows the gate-level implementation of a de-coder used in RTRAM.In [21],the authors show that the decoder is stuck-fault testable with a test set whose size is exponential in the number of levels.Analysis of the decoder implementation indicates that its func-tion completely meets the L-testability conditions of Theorem 3.The decode function provides the sensitiz-ing vectors and there exist many input patterns that produce a 0and a 1at both outputs;for example,000000→00and 110111→11.This means that the
204Blanton and
Hayes
Fig.11.Gate-level implementation of the RTRAM decoder module[21].
27=128IP faults of each l-level decoder module are testable with64patterns.
C-testability.A closer examination of the divergent tree structure illustrated in Fig.2shows that it can be viewed as n p?1arrays of n different types.For each array type j,the module input X i,l serves as the ar-ray’s state input while the control input Z l serves as the array’s vertical input;the output?X j i,l is the array’s state output.Figure12shows a covering of the de-multiplexer circuit of Fig.2(a)with four arrays of two different types.Obviously a binary(n=2)divergent tree module has two array types while an n-ary output module has n array types.Viewing trees as overlapping arrays allows the testing properties of array circuits to be generalized to divergent trees.
Fig.12.A covering of a3-level demulti-
plexer tree by four arrays of two different
types.
An IP fault is C-testable in an array of arbitrary
size if it can be tested with k test patterns,where k
is some constant.Friedman[2]showed that an IP fault
ip1→(v1,v 1)is C-testable in a one-dimensional array if there is a sequence of module input patterns that re-
generates ip1at an arbitrarily large number of modules
and can propagate the error(v1,v 1)from each of those modules.The following lemma gives a bound on test set size when faults are C-testable in the arrays within the divergent tree.
Lemma1.An n-ary p-level controlled divergent tree
CD(n,p)can be tested with at most kn p?1test patterns
if each type-j array is C-testable,where1≤j≤n. Proof:If the conditions of the lemma are satis?ed then the module is surjective.Hence,any module in CD(n,p)can have any input pattern ip k applied,and therefore CD(n,p)can be tested by testing each ar-ray within the tree separately.Since each array type is C-testable,the bound on the number of test patterns is kn p?1,where is k is some constant.Also note that any control-input fault is covered by testing the arrays contained in the tree.P Because an error at the input of a divergent tree mod-ule can be propagated to one or more of the module’s n state outputs,the conditions for C-testability of ar-rays within a controlled divergent tree are less restric-tive than the single array case.Thus,determining array C-testability for divergent trees should consider all n state outputs.This point is illustrated in the following example.
Example4.Reconsider the demultiplexer module.
Its truth table and IP faults are shown again in
Testability Properties of Divergent Trees205
Z l X?X1?X2 0000 0110 1000 1101
?X1IP faults?X2IP faults Z l X→(v k,v k)j Z l X→(v k,v k)j 00→(0,1)100→(0,1)2 01→(1,0)101→(0,1)2 10→(0,1)110→(0,1)2 11→(0,1)111→(1,0)2
(a)(b)
Fig.13.(a)Truth table for the1-to-2demultiplexer module and(b)IP faults for the1-to-2demultiplexer module.
Figs.13(a)and(b),respectively.Inspection of the truth table indicates that any control value applied to Z l will propagate any error to either?X1or?X2.Thus,an IP fault ip i→(v i,v i)j is C-testable for a type-j array if
ip i can be repetitively applied along an array of type j. The truth table reveals that all but two of the eight IP faults are C-testable in their corresponding array types; the two exceptions are11→(0,1)1and01→(0,1)2. But note that all internal tree modules(all modules not on the output level p)are tested for these two faults when the other six faults are tested.For example, testing the?X2-type arrays for11→(1,0)2,also tests each internal module for the fault11→(0,1)1.The number of p-level modules not tested for this fault is equal to the number of modules not contained in an array of type?X2,that is,2p?2.Thus,an additional 2p?2tests are needed to cover these modules.Simi-larly,any internal module fault01→(0,1)2is detected by test patterns for the fault01→(1,0)1.Hence, an additional2p?2separate tests are required for the p-level modules and the fault01→(0,1)2.Thus, a test set for a p-level demultiplexer is bounded by 2·2p?2+6·2p?1=7·2p?1.For the3-level demulti-plexer of Fig.12,the bound is7·4=28tests.
In Section3,we found that an uncontrolled diver-gent tree that is testable is also C-testable.This is in contrast to a controlled divergent tree which can easily be testable without being C-testable.But under cer-tain conditions a controlled divergent tree is C-testable. First,the arrays within a divergent tree must all be C-testable if the divergent tree is to be C-testable.Sec-ond,all l-level modules(for1≤l≤p)must have the same control value applied when the divergent tree is being tested.These conditions are formally stated in the following theorem.
Theorem4.An n-ary p-level controlled divergent tree CD(n,p)is C-testable if and only if each type-j array is C-testable for1≤j≤n and all input patterns
simultaneously applied to a given level l have identical
control values.
The proof of Theorem4is very similar to the con-
vergent tree case proven in[18]and is therefore not
presented here.
Example5.In Example4,we found that any pattern
of control values will propagate errors to the demulti-
plexer tree outputs.Thus any set of input patterns that
can be repetitively applied along each of the two ar-
ray types that have identical control values will be
C-testable.Input patterns10and00are two patterns
that satisfy these conditions.Thus four of the possible
eight IP faults associated with the demultiplexer mod-
ule(also any of the decoder modules)are C-testable.
The two test patterns that test for the faults{00→(0,1)1,00→(0,1)2,10→(0,1)1,10→(0,1)2}are shown in Fig.14.The second test pattern shown in
Fig.14illustrates error propagation for a faulty mod-
ule(shaded)affected by the IP fault00→(0,1)2. 5.Design for Testability
The conditions of Theorem3suggest how to introduce
L-testability into divergent tree circuits.Theorem3
states that a controlled divergent tree is L-testable if
the required sensitizing vectors exist,and for each state
value v k∈I X there is an input pattern ip i that produces v k at each state output?X j.By adding a single control line or utilizing an unused control value v z∈I Z,the conditions of Theorem3can be easily satis?ed. Example6.Consider testing a1-to-1024decoder im-plemented as a9-level controlled divergent tree of1-to-2decoder modules;large decoders of this sort are commonly found in memory chips.The decoder has to be exhaustively tested to detect all SSL faults[15],
206Blanton and Hayes
Fig.14.Test patterns for the C-testable IP faults of the demultiplexer module. hence a1-to-1024decoder requires210=1024test pat-
terns.The1-to-2decoder module does have the re-
quired sensitizing vectors for L-testability,but is not
L-testable because the state value1can only be ap-
plied to one module at a time in any level.This implies
that only one module per level can be tested for a fault
that requires the state value1for fault sensitization. Adding a single control line Test to the1-to-2de-coder module allows its function to be altered so that a1can be simultaneously generated at both the?X1 and?X2state outputs.This modi?cation results in the
state table shown in Fig.15.Notice that the input pat-tern(Test,Z l,X)=(1,1,1)produces1at both state outputs.A decoder built from these L-testable decoder modules requires Wp tests,where W=8is the num-ber of test patterns required by a single module.Hence, a1-to-1024decoder composed of L-testable modules requires9·8=72test patterns,a reduction of nearly 93%.The delay associated with a9-level decoder may be unacceptable for some applications.This delay can be reduced while preserving testability by using larger decoder modules,which can be made L-testable in the same way.
A gate-level implementation of the unmodi?ed de-coder function is shown in Fig.16(a).A gate-level
Test Z l
00011011
X000100001
1dd dd dd11
Fig.15.Truth table of the L-
testable1-to-2decoder.
(a)
(b)
Fig.16.Gate-level implementa-
tions of(a)the unmodi?ed and(b)
L-testable decoder modules. implementation of the L-testable decoder function is shown in Fig.16(b).Notice,that L-testability is achieved by simply replacing the NOT gate of Fig.16(a)with an EXCLUSIVE-NOR gate.The L-testable decoder design presented here is similar to the ad hoc design presented in[15].Here,a gate in the original decoder implementation is replaced with an EXCLUSIVE-NOR gate,introducing somewhat less overhead then the additional EXCLUSIVE-OR gate used in[15].
We show next how our DFT approach can enhance the testability of a practical circuit.A set of registers called a register?le is often used in processor datapaths
Testability Properties of Divergent Trees
207
Fig.17.A register ?le containing eight registers.
for data storage.It is typically implemented by arrays of D-type latches,with one or more I/O access ports connected to uni-or bidirectional lines [22].The ex-ample in Fig.17contains eight registers,and uses mul-tiplexer and demultiplexer trees to implement separate input and output ports.The register R i with address i =A read can be read out through the multiplexer tree while,at the same time,the register R j with address j =A write can be written into using the demultiplexer tree.
Using a similar DFT technique described in [18,23],the multiplexer part of Fig.17can be made L-testable.To address the testability of the registers,we must again extend our fault model to sequential array circuits.In general,a sequential module is a ?nite-state machine whose memory outputs are all primary or serve as in-puts to a neighboring module.To extend our functional fault model,we assume a sequential module can change its next-state (transition)function to any other,as long as the number of memory states does not increase.Thus testing a sequential array requires that the next-state function of each module be veri?ed.
We will only consider the simplest case where the sequential modules are D latches [3].Testing a
register Fig.18.An N -bit register viewed as a one-dimensional array of D-type latches.
with this fault model is easy since each module only has two states.Its next-state function can be tested by verifying that a 0and 1can be written into each latch with present states of either 0or 1.Since the data values applied to each latch are independent,the next-state function of all latches can be tested in parallel.Thus,registers are C-testable for this extension of our fault model.
When the multiplexer,demultiplexer,and registers are combined to form a register ?le as shown in Fig.17,the testability of these circuits under the functional fault model is preserved,but testing is limited to a single reg-ister at a time.Suppose we use an L-testable demulti-plexer and multiplexer circuit in Fig.17.The demul-tiplexer cannot be “L-tested”because its data outputs cannot be simultaneously observed,that is,each data output must be written into a single register at a time.Similarly for the multiplexer,applying a single L-test requires eight separate writes into the register ?le.The L-testability characteristics of these modi?ed trees can be preserved when combined to form a register ?le if all registers can be written into simultaneously,that is,all can be clocked at the same time.Figure 18
208Blanton and Hayes
shows a signal called Broadcast which is used to by-
pass the gated enable(Enable)signal of the register.
If connected to registers R0,R1,...,R7,Broadcast al-lows the simultaneous writing of all registers.With this
feature,the registers simply act as transparent buffers
between the divergent and convergent tree structures,
hence they do not affect fault sensitization or error prop-
agation.Furthermore,since all registers can be written
into simultaneously,they can all be tested in parallel.
If each register has the same test pattern applied,than
any single error resulting from a faulty register module
will be propagated to the multiplexer outputs since the
multiplexer is L-testable.Thus,the modi?ed register
?le is L-testable.
6.Conclusion
We have investigated a class of regular circuits called
divergent trees which include such practical circuits as
decoders and demultiplexers.Because of their regular
structure,the testability of divergent tree circuits of ar-
bitrary size can be determined solely from the tree mod-
ule’s function.Uncontrolled divergent trees are testable
with a?xed number of test patterns(C-testable)if and
only if the module function is surjective.Testable con-
trolled trees also have to be surjective but sensitizing
vectors are required for error propagation.Controlled
divergent trees can also be L-testable or C-testable
if other conditions are satis?ed.We found that de-
coders/demultiplexers only partially satisfy the re-
quirements for L-and C-testability but can be modi?ed
to enhance their https://www.doczj.com/doc/4d15045368.html,plete L-testability of
a demultiplexer was achieved using gate replacement
in the original gate-level design.The utility of the
L-testable demultiplexer was further illustrated in the
design of a small register?le.
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Shawn Blanton is an assistant professor in the Department of Electri-cal and Computer Engineering at Carnegie Mellon University where he is a member of the Center for Electronic Design Automation and principal investigator of the SEMATECH Design for Testability
Testability Properties of Divergent Trees209
Cost Model Project.He received the Bachelor’s degree in engineer-ing from Calvin College in1987,a Master’s degree in Electrical Engineering in1989from the University of Arizona,and a Ph.D. degree in Computer Science and Engineering from the University of Michigan,Ann Arbor in1994.His research interests include the computer-aided design of VLSI circuits and systems;fault-tolerant computing and diagnosis;veri?cation and testing;and computer ar-chitecture.He has worked on the design and test of complex digital systems with General Motors Research Laboratories,AT&T Bell Laboratories,and Intel.Dr.Blanton is the recipient of National Sci-ence Foundation Career Award and is a member of IEEE and ACM. John P.Hayes is Professor of Electrical Engineering and Com-puter Science at the University of Michigan,Ann Arbor,where he teaches and does research in the areas of computer architecture; computer-aided design,veri?cation and testing;VLSI design;and fault-tolerant embedded systems.He received the B.E.degree from the National University of Ireland,Dublin,in1965,and the M.S.and Ph.D.degrees from the University of Illinois,Urbana-Champaign, in1967and1970,respectively,all in Electrical Engineering.While at the University of Illinois,he participated in the design of the ILLIAC III computer.In1970he joined the Operations Research Group at the Shell Benelux Computing Center in The Hague,where he worked on mathematical programming.From1972to1982 Dr.Hayes was a faculty member of the Departments of Electrical Engineering-Systems and Computer Science of the University of Southern California,Los Angeles.He joined the University of Michi-gan in1982.He was the founding director of the University of Michi-gan’s Advanced Computer Architecture Laboratory.He was Tech-nical Program Chairman of the1977International Conference on Fault-Tolerant Computing,Los Angeles,and the1991International Computer Architecture Symposium,Toronto.Dr.Hayes is the author of numerous technical papers and?ve books,including Hierarchical Modeling for VLSI Circuit Testing,(Kluwer,1990;coauthored with D.Bhattacharya),Introduction to Digital Logic Design,(Addison-Wesley,1993),and Computer Architecture and Organization(3rd ed.,McGraw-Hill,1998).He has served as editor of various techni-cal journals,including the IEEE Transactions on Parallel and Dis-tributed Systems and the Journal of Electronic Testing.Dr.Hayes is a Fellow of IEEE and a member of ACM and Sigma Xi.
2000 第一段 Governments throughout the world act on the assumption that the welfare of their people depends largely on the economic strength and wealth of the community. 71) Under modern conditions, this requires varying measures of centralized control and hence the help of specialized scientists such as economists and operational research experts. 72) Furthermore, it is obvious that the strength of a country’s economy is directly bound up with the efficiency of its agriculture and industry, and that this in turn rests upon the efforts of scientists and technologists of all kinds. It also means that governments are increasingly compelled to interfere in these sectors in order to step up production and ensure that it is utilized to the best advantage. For example, the may encourage research in various ways, including the setting up of their own research centers; they may alter the structure of education, or interfere in order to reduce the wastage of natural resources or tap resources hitherto unexploited; or they may cooperate directly in the growing number of international projects related to science, economics and industry. In any case, all such interventions are heavily dependent on scientific advice and also scientific and technological manpower of all kinds.
财教创办北大、人大、中、北外授 训营对视频集、一一保分、、小班 2010年中山大学翻译硕士英语真题答案 育明教育梁老师提醒广大考生: 历年考研真题资料是十分珍贵的,研究真题有利于咱们从中分析出题人的思路和心态,因为每年专业课考试不管在题型还是在内容上都有很高的相似度，考研学子们一定要重视. 有什么疑问可以随时联系育明教育梁老师,我会为根据各位考生的具体情况提供更加有针对性的指导。 part I Vocabulary and Grammar 6. B 2. D 3. B meteorologist 气象学者 4. D 5. A 6. D except 后排除的内容与主语往往是同一类的,而except for 后所排除的内容与主语往往不是同一类的。例如,试比较:All the buildings are excellent except this one./All the buildings are excellent except for their location. (all 和glimmer 不是同一类事物) 7. B 8. A 9. D 10. B 11. B 12. A The child reached out a hand towards the apple . Judy reached into her handbag and handed me a small printed leaflet...朱蒂把手伸进提包，拿出一张小的印刷传单给我。I reached across the table and squeezed his hand...我把手伸到桌子的另一边，捏住他的手。13. A 14. B 15. D 16. B apt, liable, prone: 三个词都含“易于的”意思, 它们只能作表语, 不能作定语, 后面都接不定式。apt 是常用词, 尤其是用在口语中, 表示“有...倾向的”、“易于...的”, 如: He is apt to get excited over trifles.他容易为小事而激动。liable 指“易于产生某种(对主语)不利的后果”, 因此常用于警告, 如:Y ou're liable to get cold if you are not careful.你若不当心就有可能感冒。prone 侧重主语(往往是人, 极少用于物)的本性, 使之“倾向于”(某种弱点、错误或不良行为), 如:He was prone to anger.他易于发怒。17. D 18. B 19. A 20. A 21. B 22. C 23. B 24. D 25. D 苦恼的;难过的;哀伤的Someone who feels wretched feels very unhappy. 26. D insurance rate 保险费率 27. B excessively accommodating/excessively meticulous; fussy/They were exceedingly kind. 28. B 29. B 30. A PART II T ext A 31. C 32. B 33. A 34. C 35. D
高考物理模拟试题精编(一) (考试用时：60分钟试卷满分：110分) 第Ⅰ卷(选择题共48分) 一、单项选择题(本题共5小题，每小题6分，共30分．在每小题给出的四个选项中，只有一项是符合题目要求的．) 14．物体从斜面(斜面足够长)底端以某一初速度开始向上做匀减速直线运动，经t秒到达位移的中点，则物体从斜面底端到最高点时 共用时间为() A．2t B.2t C．(3－2)t D．(2＋2)t 15．一质量为M、带有挂钩的球形物体套在倾角为θ的细 杆上，并能沿杆匀速下滑，若在挂钩上再吊一质量为m的物体， 让它们沿细杆下滑，如图所示，则球形物体() A．仍匀速下滑 B．沿细杆加速下滑 C．受到细杆的摩擦力不变 D．受到细杆的弹力不变 16．如图甲所示，直角三角形斜劈abc固定在水平面上．t＝0时，一物块(可视为质点)从底端a以初速度v0沿斜面ab向上运动，到达顶端b时速率恰好为零，之后沿斜面bc下滑至底端 c.若物块与斜面ab、bc间的动摩擦因数相等，物块在两斜面上运动的速率v随时间变化的规律如图乙所示，已知重力加速度g＝10 m/s2，则下列物理量中不能求出的是()
A．斜面ab的倾角θ B．物块与斜面间的动摩擦因数μ C．物块的质量m D．斜面bc的长度L 17．如图所示，一理想变压器原、副线圈匝数之比为3∶1，原线圈两端接入一正弦交流电源，副线圈电路中R为负载电阻，交流电压表和交流电流表都是理想电表．下列结论正确的是() A．若电压表读数为36 V，则输入电压的峰值为108 V B．若输入电压不变，副线圈匝数增加到原来的2倍，则电流表的读数增加到原来的4倍 C．若输入电压不变，负载电阻的阻值增加到原来的2倍，则输入功率也增加到原来的2倍 D．若只将输入电压增加到原来的3倍，则输出功率增加到原来的9倍 18．如图所示，一个大小可忽略，质量为m的模型飞机， 在距水平地面高为h的水平面内以速率v绕圆心O做半径为R 的匀速圆周运动，O′为圆心O在水平地面上的投影点．某时 刻该飞机上有一小螺丝掉离飞机，不计空气对小螺丝的作用力， 重力加速度大小为g.下列说法正确的是() A．飞机处于平衡状态 B．空气对飞机的作用力大小为m v2 R C．小螺丝第一次落地点与O′点的距离为2hv2 g ＋R2
高三物理试题 一、选择题（共12个小题，每小题4分,共计48分。每小题只有一选项是正确的。） 1．图中重物的质量为m ，轻细线AO 和BO 的A 、B 端是固定的，平衡时AO 是水平的，BO 与水平面的夹角为θ，AO 的拉力1F 和BO 的拉力2F 的大小是（ ） A ．θcos 1mg F = B.F 1=mgtg θ C.θ sin 2 mg F = D. θsin 2mg F = 2．如图所示，一物体静止在以O 端为轴的斜木板上，当其倾角θ逐渐增大，且物体尚未滑动之前的过程中（） A ．物体所受重力与支持力的合力逐渐增大 B ．物体所受重力与静摩擦力的合力逐渐增大 C ．物体所受重力、支持力及静摩擦力的合力逐渐增大 D ．物体所受重力对O 轴的力矩逐渐增大 3．如图所示，水平恒力F 拉质量为m 的木块沿水平放置在地面上的长木板向右运动中，木板保持静止。若木板质量为M ，木块与木板、木板与地面间的动摩擦因数分别为1μ、2μ，则木板与地面间的摩擦力大小为（） A.F B.mg 1μ C.g M m )(2+μ D.mg mg 21μμ+ 4．如图所示，在倾角为30°的斜面顶端装有定滑轮，用劲度系数k=100N/m 的轻质弹簧和细绳连接后分别与物体a 、b 连接起来，细绳跨过定滑轮，b 放在斜面后，系统处于静止状态，不计一切摩擦，若kg m a 1=则 弹簧的伸长量是（） A.0cm B.10cm C.20cm D.30cm 5．一列火车从静止开始做匀加速直线运动，一个人站在第1节车厢前端观察并计时，若第一节车厢从他身边经过历时2s ，全部列车用6s 过完，则车厢的节数是（ ） A.3节 B.8节 C.9节 D.10节 6．在交通事故的分析中，刹车线的长度是很重要的依据，刹车线是汽车刹车后，停止转动的轮胎在地面上滑动时留下的痕迹。在某次交通事故中，汽车刹车线长度14m ，假设汽车轮胎与地面间的动摩擦因数为0.7，g =10m/s 2 ，则汽车开始刹车的速度为（ ） A ．7m/s B ．10 m/s C ．14 m/s D ．20 m/s 7．从空中同一点，以 s m v /100=的速度将a 球竖直上抛的同时将b 球以相同的速度大小水平 抛出，取2 /10s m g =，则两球先后落地的时间差为（） A.1s B.2s C.4s D.无法确定
1998 年全国硕士研究生入学考试英语试题文章翻译 Part I (略) Part II Cloze Test 直到最近，大多数的历史学家对工业革命仍然颇有微词。尽管他们承认从长远角度讲，工业革命已大大地提高了一般人的生活水平。然而他们坚持认为，工业革命在1750和1850年间引起的直接结果是给英国大多数人民带来了普遍的贫穷和苦难。相比之下，他们把在此之前从1650到1750的一百年看成是一个繁荣富足的时期。尽管那个时候英国还是一个完全意义上的农业国家。 然而，人们通常认为这种观点是错误的。历史和经济学专家已指出两件事情：一是1650至1750年间以显著的贫困为特征；二是工业革命不但没有加重这种贫困，反而使绝大多数人的生活得到了改善。 Part ⅢReading Comprehension Passage 1 很少有像巨型大坝那样的伟大成果如此吸引人们。也许是因为人们倍受洪水和干旱的摆布，所以驾驭洪水的想法特别地强烈。但是被吸引有时也意味着盲目，有几个巨型大坝工程就有弊大于利的危险。 大坝给人们的教训是大的不一定就是好的。但这个教训并没有阻止建立巨大而强劲的大坝，它们已经成为国家成就和人们努力表现自己的象征。埃及由于建造了阿斯旺大坝而巩固了在阿拉伯世界中的领导地位。土耳其在力图进人第一世界的努力中也包括了修建Ataturk大坝。 但是大坝不会像预期的那样产生效果。例如，阿斯旺大坝阻止了尼罗河的洪水泛滥，但也使埃及失去了洪水带来的肥沃的淤泥——这些损失的所有回报仅仅是一个充满了病患的大水库，它现在沉积了如此多的淤泥，以致于发不出电了。 但是，控制洪水的神话仍在继续。本周，在文明的欧洲的中心，斯洛伐克与匈牙利就是为了多瑙河上的一座大坝引起争端，差点动用了军队。这个巨大的工程可能会带来其他大坝通常造成的问题。但斯洛伐克正在要求脱离捷克而独立，因此需要建一座大坝来证明自己的实力。 与此同时，尽管银行的顾问们说大坝将给普通大众的生活带来困苦和环境的破坏，但世界银行还是贷款给印度修建Narmada大坝，这事后被证明是个大错。受益的是权力阶层，但也无法保证。 对大坝造成的影响和控制洪水的成本和收益进行恰当而科学的研究才能帮助解决这些冲突。即使不修建这些巨型大坝，水利发电、洪水控制和农田灌溉也都是可能做到的，但是当你相信神话的时候，你就很难做到合理和科学，世界应
2010 年全国硕士研究生入学统一考试英语（二）试题答案与解析 Section I Use of English 一、文章题材结构分析 本文是取材于新闻报道，叙述了猪流感的爆发，产生的严重影响以及政府采取的针对性措施。首段和第二段简 述了猪流感的爆发引起世界各国的重视。第三段引用专家的观点，认为瘟疫并不严重。第四段和第五段以墨西哥及 美国的情况为例，说明了猪流感的严重性和致命性。第六段叙述了联邦政府针对猪流感的具体措施。 二、试题解析 1.【答案】D 【解析】上文提到“…was declared a global epidemic…”，根据declare 的逻辑（“宣布为”），可知应该选D 项 designated“命名，制定”，而不是C 项commented“评论”，这是典型的近义词复现题目。2．【答案】C 【解析】本题目可依据“句意”找到意思线索，选出答案，难度在于出处句是个长难句。本句的理解应该抓住alert、 meeting 和a sharp rise 三者的关系，根据after a sharp rise 可知是rise（“病例数的增加”）是meeting（“日内瓦专家 会议”）的原因，由此可推导出alert 并非是meeting 的原因，而是结果，即meeting 使得alert 升级。根据上述分析 可以排除B、D 选项，B 项activated“激活，激起”，D 项“促使，引起”，此两项的选择都在讲alert 导致了meeting 的召开。而C 项followed 意思是“紧随，跟在……之后”，体现出after 的逻辑，完全满足本句rise 之后是meeting， meeting 之后是alert 的逻辑，所以是正确项。而A 项proceeded“继续”，属不及物动词，不可接宾语，用法和逻辑 用在此处都不合适。 3．【答案】B 【解析】本题目应该关注并列连词and，从并列呼应来看：空格后的表达in Britain…对应前面的in Australia， 所以空格处rising _____ 应该对应a sharp rise in cases（“病例数的剧增”），因此空格处是“数量”的逻辑才对。A 项 digits“（阿拉伯）数字”，不表示数量，不能与rising 形成搭配；C 项amounts“数量”，常修饰不可数名词（此处指 的是cases，可数名词）；D 项sums“金额，款项”，不能用于表达“病例数”。B 项numbers “数量”，修饰可数名词（如： large numbers of cases 大量的病例），符合题意。 4．【答案】A 【解析】此处句子开头的“But”是重要的逻辑线索，与上文意思（第二段）形成对比反差。上文的关键性表达 如“heightened alert”、“emergency meeting”和“a sharp rise in cases”都在讲述猪流感的严重性，所以根据But 和in
2018年高考物理全真模拟试题（十） 满分110分，时间60分钟 第Ⅰ卷(选择题共48分) 选择题：本题共8小题，每小题6分．在每小题给出的四个选项中，第1～4题只有一项符合题目要求，第5～8题有多项符合题目要求．全部选对的得6分，选对但不全的得3分，有选错的得0分． 1．下列说法正确的是() A．自然界的电荷只有两种，库仑把它们命名为正电荷和负电荷 B．欧姆发现了电流的热效应 C．楞次根据通电螺线管的磁场和条形磁铁的磁场的相似性，提出了分子电流假说D．电流的单位“安培”是国际单位制中的基本单位 2．如图所示，静止在水平地面上倾角为θ的光滑斜面体上，有一斜劈A，A的上表面水平且放有一斜劈B，B的上表面上有一物块C，A、B、C一起沿斜面匀加速下滑．已知A、B、C的质量均为m，重力加速度为g.下列说法正确的是() A．A、B间摩擦力为零 B．C可能只受两个力作用 C．A加速度大小为g cos θ D．斜面体受到地面的摩擦力为零 3．如图所示，真空中两个等量异种点电荷＋q(q＞0)和－q以相同角速度绕O点在纸面中沿逆时针方向匀速转动，O点离＋q较近，则() A．O点的磁感应强度方向始终垂直纸面向外 B．O点的磁感应强度方向始终垂直纸面向里 C．O点的磁感应强度方向随时间周期性变化 D．O点的磁感应强度大小随时间周期性变化 4．如图甲所示，以等腰直角三角形ABC为边界的有界匀强磁场垂直于纸面向里，一个等腰直角三角形线框abc的直角边ab的长是AB长的一半，线框abc在纸面内，线框的cb 边与磁场边界BC在同一直线上，现在让线框匀速地向右通过磁场区域，速度始终平行于BC边，则在线框穿过磁场的过程中，线框中产生的电流随时间变化的关系图象是(设电流沿顺时针方向为正)()
高考物理试题及答案 HEN system office room 【HEN16H-HENS2AHENS8Q8-HENH1688】
2015高考物理（北京卷） 13．下列说法正确的是 A ．物体放出热量，其内能一定减小 B ．物体对外做功，其内能一定减小 C ．物体吸收热量，同时对外做功，其内能可能增加 D ．物体放出热量，同时对外做功，其内能可能不变 14．下列核反应方程中，属于仪衰变的是 A ．H O He N 1117842147+→+ B ．He Th U 4 22349023892+→ C ．n He H H 10423121+→+ D ．e Pa Th 0 12349123490-+→ 15．周期为的简谐横波沿x 轴传播，该波在某时刻的图像如图所示，此时质点P 沿y 轴负方向运动。则该波 A ．沿x 轴正方向传播，波速v =20m/s B ．沿x 轴正方向传播，波速v =10m/s C ．沿x 轴负方向传播，波速v =20m/s D ．沿x 轴负方向传播，波速v =10m/s 16．假设地球和火星都绕太阳做匀速圆周运动，己知地球到太阳的距离小于火星到太 阳的距离，那么 A ．地球公转周期大于火星的公转周期 B ．地球公转的线速度小于火星公转的线速度 C ．地球公转的加速度小于火星公转的加速度 D ．地球公转的角速度大于火星公转的角速度 17．验观察到，静止在匀强磁场中A 点的原子核发生β衰变，衰变产生的新核与电 子恰在纸面内做匀速圆周运动，运动方向和轨迹示意如 图。则 A ．轨迹1是电子的，磁场方向垂直纸面向外 B ．轨迹2是电子的，磁场方向垂直纸面向外 C ．轨迹l 是新核的，磁场方向垂直纸面向里 D ．轨迹2是新核的，磁场方向垂直纸面向里 18．“蹦极”运动中，长弹性绳的一端固定，另一端绑在人身上，人从几十米高处跳 下。将蹦极过程简化为人沿竖直方向的运动。从绳恰好伸直，到人第一次下降至最低点的过程中，下列分析正确的是
2001年考研英语翻译真题精练精讲 一、全真试卷 In less than30years time the Star Trek holodeck will be a reality. Direct links between the brains nervous system and a computer will also create full sensory virtual environments，allowing virtual vacations like those in the film Total Recall. （71）There will be television chat shows hosted by robots，and cars with pollution monitors that will disable them when they offend.（72）Children will play with dolls equipped with personality chips，computers with in-built personalities will be regarded as workmates rather than tools，relaxation will be in front of smell-television，and digital age will have arrived. According to BT s futurologist，Ian Pearson，these are among the developments scheduled for the first few decades of the new millennium（a period of 1000years），when supercomputers will dramatically accelerate progress in all areas of life. （73）Pearson has pieced together the work of hundreds of researchers around the world to produce a unique millennium technology calendar that gives the latest dates when we can expect hundreds or key breakthroughs and discoveries to take place. Some of the biggest developments will be in medicine，including an extended life expectancy and dozens of artificial organs coming into use between now and 2040. Pearson also predicts a breakthrough in computer-human links. “By linking directly to our nervous system，computers could pick up what we feel and，hopefully，simulate feeling too so that we can start to develop full sensory environments，rather like the holidays in Total Recall or the Star Trek holodeck,”, he says.（74）But that，Pearson points out，is only the start of man-machine integration:”It will be the beginning of the long process of integration that will ultimately lead to a fully electronic human befo re the end of the next century.” Through his research，Pearson is able to put dates to most of the breakthroughs that can be predicted. However，there are still no forecasts for when faster-that-light travel will be available，or when human cloning will be perfected，or when time travel will be possible. But he does expect social problems as a result of technological advances. A boom in neighborhood surveillance cameras will，for example，cause problems in2010，while the arrival of synthetic lifelike robots will mean people may not be able to distinguish between their human friends and the droids.（75）And home appliances will also become so smart that controlling and operating them will result in the breakout of a new psychological disorder—kitchen rage. 二、翻译题解 （71）Therewill betelevision chat shows hosted by robots, and cars with pollution monitorsthatwill disablethem when they offend. 句子拆分： 拆分点参考：分词,标点符号，连词 There will be television chat shows// hosted by robots//, and cars with pollution monitors// that will disable them// when they offend. 解读： 1）主干结构是带双主语的存在句：There will be television chat shows..., and cars... 2）两个主语都带有定语：第一个主语television chat shows的定语是过去分词短语hosted by robots，第二个主语cars的定语是介词短语with pollution monitors。
2020年高考物理全真模拟试题附答案二精 编版
新人教版高考物理全真模拟试题附答案（二） 注意事项：本试题分三部分。第一部分为单项选择题；第二部分和第三部分有多种题型组成。第一部分、第二部分为全体考生必做题，提供了两个选修模块的试题，考生必须选择其中一个模块的试题作答。 第一部分（共48分共同必做） 一、本题共16小题，每小题3分，共48分。在每个小题给出的四个选项中，只有一个选项是正确的。选对的得3分，选错或不答的得0分。 1、关于速度，速度改变量，加速度，正确的说法是： A、物体运动的速度改变量很大，它的加速度一定很大 B、速度很大的物体，其加速度可以很小，可以为零 C、某时刻物体的速度为零，其加速度不可能为零 D、加速度很大时，运动物体的速度一定很大 2、沿一条直线运动的物体，当物体的加速度逐渐减小时，下列说法正确的是： A、物体运动的速度一定增大 B、物体运动的速度一定减小 C、物体运动速度的变化量一定减少 D、物体 运动的路程一定增大 3、如图所示为某物体做直线运动的图象，关于这个物 体在4s内运动的情况，下列说法正确的是： A、物体始终向同一方向运动 B、加速度大小不变，方向与初速度方向相同 C、4s末物体离出发点最远 D、4s内通过的路程为4m，位移为零 仅供学习与交流，如有侵权请联系网站删除谢谢10
仅供学习与交流，如有侵权请联系网站删除 谢谢10 4、如图，A 、B 两物体通过跨过光滑滑轮的细线连在一起，它们均处于静止状态，A 物体的受力情况是 A ．受4个力作用，其中弹力有2个 B ．受4个力作用，其中弹力有1个 C ．受3个力作用，其中弹力有2个 D ．受3个力作用，其中弹力有1个 5、木块在斜向下的推力作用下，静止在水平地面上，如不改变力F 的大小，而使F 与水平面的夹角α逐渐增大(不超过90o)，则 A ．木块对地面的压力不变 B ．木块对地面的压力逐渐减小 C ．木块对地面的摩擦力逐渐增大 D ．木块对地面的摩擦力逐渐减小 6、一个物体受到多个力作用而保持静止，后来物体所受的各力中只有一个力逐渐减小到零后又逐渐增大，其它力保持不变，直至物体恢复到开始的受力情况，则物体在这一过程中 A ．物体的速度逐渐增大到某一数值后又逐渐减小到零 B ．物体的速度从零逐渐增大到某一数值后又逐渐减小到另一数值 C ．物体的速度从零开始逐渐增大到某一数值 D ．以上说法均不对 7、神州五号成功发射，杨利伟成为中国航天第一人。当他处于超重状态时，他不可能处在 A ．火箭发射升空的过程中 B ．航天器在预定轨道上运行的过程中 C ．载人仓返回地面的过程中 D ．在离心机上训练时 8、人站在地面上将两脚弯曲，再用力蹬地，就能跳离地面，人能跳起的原因是
2018年高考物理试题及答案 二、选择题：本题共8小题，每小题6分。在每小题给出的四个选项中，第14~18题只有一 项符合题目要求，第19~21题有多项符合题目要求。全部选对的得6分，选对但不全的得3分，有选错的得0分。 14．高铁列车在启动阶段的运动可看作初速度为零的均加速直线运动，在启动阶段列车的动能A．与它所经历的时间成正比 B．与它的位移成正比 C．与它的速度成正比 D．与它的动量成正比 15．如图，轻弹簧的下端固定在水平桌面上，上端放有物块P，系统处于静止状态，现用一竖直向上的力F作用在P上，使其向上做匀加速直线运动，以x表示P离开静止位置的位移，在弹簧恢复原长前，下列表示F和x之间关系的图像可能正确的是 A． B． C．
D． 16．如图，三个固定的带电小球a、b和c，相互间的距离分别为ab=5 cm，bc=3 cm，ca= 4 cm。小球c所受库仑力的合力的方向平衡于a、b的连线。设小球a、b所带电荷量 的比值的绝对值为k，则 A．a、b的电荷同号， 16 9 k= B．a、b的电荷异号， 16 9 k= C．a、b的电荷同号， 64 27 k= D．a、b的电荷异号， 64 27 k= 17．如图，导体轨道OPQS固定，其中PQS是半圆弧，Q为半圆弧的中心，O为圆心。轨道的电阻忽略不计。OM是有一定电阻。可绕O转动的金属杆。M端位于PQS上，O M与轨道接触良好。空间存在半圆所在平面垂直的匀强磁场，磁感应强度的大小为B，现使OM从OQ位置以恒定的角速度逆时针转到OS位置并固定（过程Ⅰ）；再使磁感应强度的大小以一定的变化率从B增加到B'（过程Ⅱ）。在过程Ⅰ、Ⅱ中，流过OM 的电荷量相等，则B B ' 等于
2011年全国硕士研究生入学考试英语(一)试题文章翻译 Section I Use of English 古希腊哲学家亚里士多德把笑看作是“有益于身体健康的宝贵锻炼”。尽管有些相反的意见，但笑可能对身体健康影响极小。笑确实能对心脏和血管产生短期的改变，笑能够促进心律呼吸速率。但是因为大笑很难持续，一次狂笑不可能像比如走路或者慢跑那样对心血管功能产生很大的益处。 实际上，其他的锻炼可以拉紧增强肌肉，很显然笑确是起到了相反的作用，二十世纪三十年代的一项研究表明笑可以放松肌肉，在狂笑平息之后45分钟内会降低肌肉张力。 这样的身体放松可能会帮助减轻心理紧张状态的影响。笑的行为毕竟可能会产生其他形式的身体上的反馈来提高个体的情绪状态。根据一个经典的情绪理论，我们的感觉部分根源于身体上的反映。十九世纪末人们便争论这一说法：人们不会因为他们伤心而哭，但当开始 尽管悲伤能产生眼泪，证据显示情绪是肌肉反应的结果。1988年德国乌子堡大学的社会心理学家做了一个实验，他让志愿者用牙咬住一支笔做出假笑，或者用嘴含住一支笔，这个动作会让人产生一种失望的表情。那些被强制锻炼笑肌的人比那些嘴唇皱着表情失望的人在观看有趣的动画片时反应更加丰富，这暗示了表情可能会影响情绪，而不只是反过来情绪会影响表情。同样，笑这一生理行为可以改善心
Section II Reading Comprehension Part A Text 1 纽约爱乐乐团决定聘请Alan Gilbert作为下一任的音乐总监，这从2009年任命被宣布之日起就在古典音乐界引起了热议。别的不说，大部分人的反应是积极的。“好啊，终于好了！” Anthony Tommasini写道，他可是一个以严肃著称的古典音乐评论家。 但是，这个任命之所以引起人们惊讶的原因却是Gilbert相对而言并不是很有名。甚至在时代杂志上发文支持Gilbert任命的Tommasini都称其为“低调的音乐家，在他身上找不到那种飞扬跋扈的指挥家的气质。”爱乐乐团迄今为止都是由像Gustav Mahler和Pierre Boulez那样的音乐家领导的。这样去描述这个乐团的下一位 指挥，至少对于时代的读者而言，这是一种苍白的表扬。 就我看来，我不知道Gilbert是否是一个伟大的指挥家或者是一个好的指挥。但是我能确定的是，他能表演出很多有趣的乐章，但是我却应该不会去Avery Fisher Hall或者其他地方去听一场有趣的交响乐演出。我要做的事情就是去我的CD架上，或者打开的我的电脑 从iTunes上下载更多的唱片。 那些忠实的音乐会观众会讲唱片并不能代替现场的演出，但是他们忽略了核心问题。当下为了获得艺术爱好者的时间，关注度和金钱，
最新高考物理模拟试题精编及答案解析(十六) (考试用时：60分钟 试卷满分：110分) 第Ⅰ卷(选择题 共48分) 一、单项选择题(本题共5小题，每小题6分，共30分．在每小题给出的四个选项中，只有一项是符合题目要求的．) 14．下列说法中不正确的是( ) A ．用比值法定义的物理概念在物理学中占有相当大的比例，例如场强E ＝F q ，电容C ＝Q U ，加速度a ＝F m ，都是采用比值法定义的 B ．如果电场线与等势面不垂直，那么电场强度就有一个沿着等势面的分量，在等势面上移动电荷，静电力就要做功．这里用的逻辑方法是假设法 C ．在推导匀变速直线运动的位移公式时，把整个运动过程划分成很多小段，每一小段近似看作匀速直线运动，然后把各小段的位移相加．这里采用了微元法 D ．用点电荷来代替实际带电体是采用了理想模型的方法 15．如图所示，一个带电荷量为q ，质量为m 的小球，以 某一初速度在匀强电场中从O 点竖直向上抛出，电场方向与 水平方向成45°角，小球的运动轨迹恰好满足抛物线方程y ＝ kx 2，且小球通过点P ? ?? ??1k ，1k .已知重力加速度为g ，则( ) A ．小球初速度的大小为 g k B ．电场强度的大小为mg q C ．小球通过点P 时的动能为5mg 4k D ．小球从O 点运动到P 点的过程中，电势能减少2mg k 16．如图甲所示，理想变压器原、副线圈的匝数比n 1∶n 2＝3∶1，L 1、L 2
为两相同灯泡，R、L、D和C分别为定值电阻、理想线圈、理想二极管和电容器，其中C＝10 μF且电容器不会被击穿．当原线圈两端接如图乙所示的正弦交变电压时，下列说法中正确的是() A．灯泡L1一定比L2暗 B．电容器C放电周期为2×10－2 s C．副线圈两端的电压有效值为12 V D．电容器C所带电荷量为1.2×10－4 C 17．如图所示，丘陵地带输电线路的电线杆常常要拖着 电线翻山越岭，图中A、C为一根输电线的两端，B为输电 线的最低点．设输电线为粗细均匀的匀质导线．由于导线自 身的重力的作用可能使导线在某点断开，则下列说法正确的 是() A．输电线内部拉力处处相等，所以任意处断裂都有可能 B．最易断裂点在B点 C．最易断裂点在C点 D．最易断裂点在A点 18．2016年11月17日12时41分，我国航天员景海鹏、陈冬踏上返回之旅．他们在天宫二号空间实验室已工作生活了30天．创造了中国航天员太空驻留时间的新纪录．假设未来的某一天我国宇航员登上某一星球，测得该星球表面的重力加速度是地球表面重力加速度的2倍，而该星球的平均密度与地球的
2017·全国卷Ⅱ(物理)
14．O2[2017·全国卷Ⅱ] 如图，一光滑大圆环固定在桌面上，环面位于竖直平面内，在 大圆环上套着一个小环，小环由大圆环的最高点从静止开始下滑，在小环下滑的过程中，大 圆环对它的作用力( )
图1 A．一直不做功 B．一直做正功 C．始终指向大圆环圆心 D．始终背离大圆环圆心 14．A [解析] 光滑大圆环对小环的作用力只有弹力，而弹力总跟接触面垂直，且小环
的速度总是沿大圆环切线方向，故弹力一直不做功，A 正确，B 错误；当小环处于最高点和
最低点时，大圆环对小环的作用力均竖直向上，C、D 错误．
15．D4[2017·全国卷Ⅱ] 一静止的铀核放出一个α 粒子衰变成钍核，衰变方程为23982U→23940 Th＋42He.下列说法正确的是( )
A．衰变后钍核的动能等于α 粒子的动能 B．衰变后钍核的动量大小等于α 粒子的动量大小 C．铀核的半衰期等于其放出一个α 粒子所经历的时间 D．衰变后α 粒子与钍核的质量之和等于衰变前铀核的质量 15．B [解析] 衰变过程动量守恒，生成的钍核的动量与α粒子的动量等大反向，根据 p2 Ek＝2m，可知衰变后钍核的动能小于α粒子的动能，所以 B 正确，A 错误；半衰期是一半数 量的铀核衰变需要的时间，C 错误；衰变过程放出能量，质量发生亏损，D 错误． 16．B7[2017·全国卷Ⅱ] 如图，一物块在水平拉力 F 的作用下沿水平桌面做匀速直线运 动．若保持 F 的大小不变，而方向与水平面成 60°角，物块也恰好做匀速直线运动，物块与 桌面间的动摩擦因数为( )
图1
This movement, driven by powerful and diverse motivation, built a nation out of a wilderness and, by its nature, shaped the character and destiny of an uncharted continent. The United States is the product of two principal forces-the immigration of European peoples with their varied ideas, customs, and national characteristics and the impact of a new country which modified these traits. But, the force of geographic conditions peculiar to America, the interplay of the varied national groups upon one another, and the sheer difficulty of maintaining old-world ways in a raw, new continent caused significant changes. The first shiploads of immigrants bound for the territory which is now the United States crossed the Atlantic more than a hundred years after the 15th-and-16th-century explorations of North America. The virgin forest with its richness and variety of trees was a veritable real treasure-house which extended from Maine all the way down to Georgia.
一、翻译命题原则和测试重点 1. 汉译英题型 2. 一般的短句翻译，内容日常，关键在正确用词、搭配、语法。 3. 实质为补全句子，考察语法结构和词组运用知识：句型、词 组、单词拼写、大小写、标点符号等 二、翻译原则与应试技巧 1. 正确理解原文词义，正确选词，重点吃透原文 例如：入世与否，对中国来讲，是一个面子问题。 The access to WTO, for China, is a question of dignity 2. 注意词的搭配：重点是定语和中心词、动宾 例如：1. 他整个下午都在忙着接电话。 He was busy answering the telephones all afternoon. 2. 被告在法庭上承认了自己的罪行。 The accused confessed his crime in court. 3. 具体翻译方法的运用 （1）增译法：冠词、时态词、动态词、连词、概括词 例如：a. 虚心使人进步，骄傲使人落后 modesty helps one to go forward, while conceit makes one lag behind. 例如: b.谁都知道战场是艰苦的 Everyone knows that life on battlefields is very hard. （2）减词法a：使之符合英文习惯，不能死译
例如：中国足球的落后状态必须改变。 The (state/condition of) backwardness of the Chinese football must be changed. 总结：汉语中的范畴词在英文中往往省略，用英文中 相应的抽象名词翻译,常考范畴词为： 谦虚态度：modesty 发展过程：development 残暴行为：brutality 同情心理：sympathy 悲伤情绪：sadness 无知表现：innocence 稳定性： stability 灵敏度：sensibility 防爆措施：anti-violence 同化作用：assimilation （3）转换词性：重点是动词派生词、介词和副词 例如a：看到喷气式飞机令我非常向往。 The sight of the jet filled me with special longing. 例如b: 她越过草地、跨上台阶。 She skimmed over the lawn and up the steps. （4）巧用英语中的词缀 表能力的‘得’（able-，-ible）：消息靠的住吗？Is…reliable? 表‘过多’的over-：她加班了5个小时：she overworked for 5… 表‘免除’的‘- free’：昆明是个不冻城：Kungming is a ice-free.. 表‘超过’的‘out-’: 他比他妻子多活了3年：…outlived his wife for… 考察重点 虚拟语气