jtag的经典例子
module jtag(TCK,TMS, TDI, PROGRAM_COUNT, SFR_DATA, SOURCE_DI, XRAMDI, PROGDI, TRESET, SCLK,
//Output
TDO, //SOURCE_AJ, DESTIN_AJ, XRAMAJ, PROGAJ, DESTIN_DOJ, XRAMDOJ,
PROGRAM_COUNTJ, PROGDOJ,
NXRAMRJ, nXRAMWJ, NPSENJ ,PROGWE, SFR_WRITEJ, Write_SFR, Read_SFR
, Read_RAM, NDESTIN_WEJ, nDESTIN_WEJ, Write_PC,
ICReset,ICDisable,ICClock_Disable,ICClock_Enable
);
//Input
input TCK;
input TMS;
input TDI;
input TRESET;
input SCLK; //IC stop feedback signal at step_into state
input [15:0] PROGRAM_COUNT; //present PC value input [7:0] SFR_DATA;
input [7:0] SOURCE_DI;
input [7:0] XRAMDI;
input [7:0] PROGDI;
//Output
output ICReset;
output ICDisable;
output ICClock_Disable;
output TDO;
//output [7:0] SOURCE_AJ;
//output [15:0] XRAMAJ;
//output [15:0] PROGAJ;
//output [7:0] DESTIN_DOJ;
//output [7:0] XRAMDOJ;
//output [7:0] PROGDOJ;
//output [15:0] PROGRAM_COUNTJ;
output Write_PC;
output NXRAMRJ;
output nXRAMWJ;//NXRAMWJ,
output NPSENJ;
output Write_SFR,SFR_WRITEJ;
output Read_SFR;
output Read_RAM;
output nDESTIN_WEJ,NDESTIN_WEJ;
output PROGWE;
// Test Access Port(TAP) controller controls the scan chains logic .
// The architecture of the TAP design fully complied with the IEEE
// Standard 1149.1-2090 Standard Test Access Port and Boundary-Scan Architectur
// For further details of it, please refer to the standard.
//port declare
//data bus and address bus for different area
wire [7:0]DESTIN_DOJ;
wire [7:0]XRAMDOJ;
wire [7:0]PROGDOJ;
wire [7:0] SOURCE_AJ;
wire [7:0] DESTIN_AJ;
wire [15:0]XRAMAJ;
wire [15:0]PROGAJ;
//read and write flag for different area reg NXRAMRJ;
reg nXRAMWJ, NXRAMWJ;
reg NPSENJ;
reg PROGWE;
reg Read_SFR;
reg Read_RAM;
reg nDESTIN_WEJ, NDESTIN_WEJ; reg Write_SFR;
reg SFR_WRITEJ;
//Instruction register: IR_WIDTH 8bits reg [7:0]InstructionReg;
reg [7:0]InstructionRegLat;
//test data registers
reg [7:0]IDCodeReg;
reg BypassReg;
reg [7:0]INTESTReg;
reg [7:0]INTESTRegLat;
reg [7:0]CtrlReg;
reg [7:0]CtrlRegLat;
reg [7:0]DataReg;
reg [7:0]DataRegLat;
reg [15:0]AddrReg;
reg [15:0]AddrRegLat;
//set break point
reg [15:0]BreakPointReg;
reg [15:0]BreakPointLat1;
reg [15:0]BreakPointLat2;
reg [15:0]BreakPointLat3;
reg [15:0]BreakPointLat4;
reg [15:0]BreakPointLat5;
reg [15:0]PcReg;
reg [15:0]PcRegLat;
wire [15:0]PROGRAM_COUNTJ;
//TDO select
wire TDO;
reg OutEnable;
reg SelectedTDO; // data out
wire OutSelect; // select instruction or test data is cl ocked out
wire InstructionOut;
wire DataPathOut; // test data register out port ,select which test data path to be clock out
wire BypassOut;
wire IDCodeOut;
wire INTESTOut;
wire DataOut;
wire AddrOut;
wire CtrlOut;
wire PcOut;
wire BreakPointOut;
//ICDisable and reset flag
reg ICReset;
//wire reset;
wire ICClock_Disable;
wire ICClock_Enable;
reg ICDisable;
reg ICClock_Disable1;
reg ICClock_Disable2;
reg ICClock_Disable3;
wire Stepin_flag;
reg [1:0] Disable2_CNT ;
reg flag;
reg flag_sample;
wire Breakpoint_flag;
//reg [1:0] disable3_CNT;
//reg disable3_CNT_enable;
// break_point informations and flags //break point enable
reg Break1_enable;
reg Break2_enable;
reg Break3_enable;
reg Break4_enable;
reg Break5_enable; wire Break1Comp; wire Break2Comp; wire Break3Comp; wire Break4Comp; wire Break5Comp;
//disable break point wire Break1Disable; wire Break2Disable; wire Break3Disable; wire Break4Disable; wire Break5Disable;
// instruction selected reg [19:0] InstruDecode;
wire EXTESTSelected; wire IDCODESelected; wire INTESTSelected; wire BYPASSSelected; wire CTRLSelected;
wire DATASelected;
wire ADDRSelected;
wire PCSelected;
wire Write_PC;
wire BreakPoint1Selected; wire BreakPoint2Selected; wire BreakPoint3Selected; wire BreakPoint4Selected; wire BreakPoint5Selected;
wire BreakPoint_Disable; wire Break1DisableSelected; wire Break2DisableSelected; wire Break3DisableSelected; wire Break4DisableSelected; wire Break5DisableSelected;
//TAP state machine reset flag wire TapReset;
//TAP state register: 4bits
reg [3:0]TapState;
//UPDATA_IR FLAG
reg IR_Update_flag;
//define the TAP states
parameter EXIT2_DR =4’h0;
parameter EXIT1_DR =4’h1;
parameter SHIFT_DR =4’h2;
parameter PAUSE_DR =4’h3;
parameter SELECT_IR_SCAN =4’h4;
parameter UPDATE_DR =4’h5;
parameter CAPTURE_DR =4’h6;
parameter SELECT_DR_SCAN =4’h7;
parameter EXIT2_IR =4’h8;
parameter EXIT1_IR =4’h9;
parameter SHIFT_IR =4’hA;
parameter PAUSE_IR =4’hB;
parameter RUN_TEST_IDLE =4’hC;
parameter UPDATE_IR =4’hD;
parameter CAPTURE_IR =4’hE;
parameter TEST_LOGIC_RESET =4’hF;
parameter DEVICE_IDCODE =1;
/************************************TAP State
Machine***********************************/
always @ ( posedge TCK or posedge TRESET) begin: p_TAPseq
if (TRESET)
TapState <=TEST_LOGIC_RESET;
else
begin: TAPState
case (TapState) // synopsys full_case parallel_case EXIT2_DR: //4’h0
begin
if (TMS)
TapState <= UPDATE_DR;
else
TapState <= SHIFT_DR;
end
EXIT1_DR: //4’h1
begin
if (TMS)
TapState <= UPDATE_DR;
else
TapState <= PAUSE_DR;
end
SHIFT_DR: //4’h2
begin
if (TMS)
TapState <= EXIT1_DR;
end
PAUSE_DR: //4’h3
begin
if (TMS)
TapState <= EXIT2_DR;
end
SELECT_IR_SCAN: //4’h4 begin
if (TMS)
TapState <= TEST_LOGIC_RESET; else
TapState <= CAPTURE_IR;
end
UPDATE_DR: //4’h5
begin
if (TMS)
TapState <= SELECT_DR_SCAN; else
TapState <= RUN_TEST_IDLE; end
CAPTURE_DR: //4’h6
begin
if (TMS)
TapState <= EXIT1_DR;
else
TapState <= SHIFT_DR;
end
SELECT_DR_SCAN: //4’h7 begin
if (TMS)
TapState <= SELECT_IR_SCAN; else
TapState <= CAPTURE_DR;
end
EXIT2_IR: //4’h8
begin
if (TMS)
TapState <= UPDATE_IR; else
TapState <= SHIFT_IR; end
EXIT1_IR: //4’h9
begin
if (TMS)
TapState <= UPDATE_IR; else
TapState <= PAUSE_IR; end
SHIFT_IR: //4’hA begin
if (TMS)
TapState <= EXIT1_IR; end
PAUSE_IR: //4’hB begin
if (TMS)
TapState <= EXIT2_IR;
end
RUN_TEST_IDLE: //4’hC
if (TMS) TapState <= SELECT_DR_SCAN; UPDATE_IR: //4’hD
begin
if (TMS)
TapState <= SELECT_DR_SCAN;
else
TapState <= RUN_TEST_IDLE;
end
CAPTURE_IR: //4’hE
begin
if (TMS)
TapState <= EXIT1_IR;
else
TapState <= SHIFT_IR;
end
TEST_LOGIC_RESET: //4’hF
if (!TMS) TapState <= RUN_TEST_IDLE;
endcase
end //TAPState
end // p_TAPseq
/*always @(TapState)
if(TapState==`TEST_LOGIC_RESET) TapReset =1;
else TapReset =0;*/
assign TapReset = (TapState==TEST_LOGIC_RESET)? 1:0;
//assign reset = TapReset || ICReset;
/************************************ TAP State Machine end ***********************************/
/***********************Instruction
Register***********************/
//The fixed value 0001 is loaded into the instruction register during the CAPTURE_IR controller state.
always @ (posedge TCK or posedge TapReset)
begin
if(TapReset)
InstructionReg <= 0;//01;
else if(TapState==CAPTURE_IR) InstructionReg[7:0] <= 0;//8’h41;
else if(TapState==SHIFT_IR)
InstructionReg[7:0] <= {TDI,InstructionReg[7:1]}; end
always @ (posedge TapReset or negedge TCK) begin
if(TapReset) begin
InstructionRegLat = 0;
flag = 0;
IR_Update_flag=0;
end
else if( TapState==UPDATE_IR)
begin
InstructionRegLat = InstructionReg;
IR_Update_flag=1;
if(InstructionRegLat[7:6] == 2’b10)
flag = !flag;
else
flag=0;
end
else
IR_Update_flag=0;
end
//************************Instruction Register End*******************/
//******************** instruction decode ***********************/
//instructionregLat select test data register for output
always @(posedge TapReset or posedge SCLK)
begin
if(TapReset)
InstruDecode[19:0]=20’h00000;
else begin
case(InstructionRegLat[7:0])
8’h40: InstruDecode[19:0]=20’h00001; //EXTESTSelected
8’h41: InstruDecode[19:0]=20’h00001<< 1 ; //IDCODESelected
8’h42: InstruDecode[19:0]=20’h00001<< 2 ; //PCSelected
8’H44: InstruDecode[19:0]=20’h00001<< 3 ; //Write_PC
8’H45: InstruDecode[19:0]=20’h00001<< 4; //INTESTSelected 8’h49: InstruDecode[19:0]=20’h00001<< 5 ; //BreakPoint1Sele cted
8’h4a: InstruDecode[19:0]=20’h00001<< 6 ; //BreakPoint2Sele cted
8’h4b: InstruDecode[19:0]=20’h00001<< 7 ; //BreakPoint3Sele cted
8’h4c: InstruDecode[19:0]=20’h00001<< 8 ; //BreakPoint4Sele cted
8’h4d: InstruDecode[19:0]=20’h00001<< 9 ; //BreakPoint5Sele cted
8’h50: InstruDecode[19:0]=20’h00001<< 10 ; //BreakPoint_Dis able
8’h51: InstruDecode[19:0]=20’h00001<< 11; //Break1DisableSe lected
8’h52: InstruDecode[19:0]=20’h00001<< 12; //Break2DisableSe lected
8’h53: InstruDecode[19:0]=20’h00001<< 13; //Break3DisableSe lected
8’h54: InstruDecode[19:0]=20’h00001<< 14; //Break4DisableSe
lected
8’h55: InstruDecode[19:0]=20’h00001<< 15; //Break5DisableSe lected
8’h61: InstruDecode[19:0]=20’h00001<< 16; //CTRLSelected
8’h62: InstruDecode[19:0]=20’h00001<< 17; //DATASelected
8’h64: InstruDecode[19:0]=20’h00001<< 18; //ADDRSelected
default: InstruDecode[19:0]=20’h00001<< 19; //BYPASSSelected endcase
end
end
assign EXTESTSelected = InstruDecode[0];
assign IDCODESelected = InstruDecode[1];
assign PCSelected = InstruDecode[2];
assign Write_PC = InstruDecode[3];
assign INTESTSelected = InstruDecode[4];
assign BreakPoint1Selected = InstruDecode[5];
assign BreakPoint2Selected = InstruDecode[6];
assign BreakPoint3Selected = InstruDecode[7];