PSoC? Mixed-Signal Array
Final Data Sheet
CY8C29466, CY8C29566,CY8C29666, and CY8C29866
PSoC? Functional Overview
The PSoC ? family consists of many Mixed-Signal Array with On-Chip Controller devices. These devices are designed to replace multiple traditional MCU-based system components with one, low cost single-chip programmable device. PSoC devices include configurable blocks of analog and digital logic,as well as programmable interconnects. This architecture allows the user to create customized peripheral configurations that match the requirements of each individual application.Additionally, a fast CPU, Flash program memory, SRAM data memory, and configurable IO are included in a range of conve-nient pinouts and packages.
The PSoC architecture, as illustrated on the left, is comprised of four main areas: PSoC Core, Digital System, Analog System,and System Resources. Configurable global busing allows all the device resources to be combined into a complete custom system. The PSoC CY8C29x66 family can have up to eight IO ports that connect to the global digital and analog interconnects,providing access to 16 digital blocks and 12 analog blocks.
The PSoC Core
The PSoC Core is a powerful engine that supports a rich fea-ture set. The core includes a CPU, memory, clocks, and config-urable GPIO (General Purpose IO).
The M8C CPU core is a powerful processor with speeds up to 24 MHz, providing a four MIPS 8-bit Harvard architecture micro-processor. The CPU utilizes an interrupt controller with 25 vec-
Features
■Powerful Harvard Architecture Processor
?M8C Processor Speeds to 24 MHz ?Two 8x8 Multiply, 32-Bit Accumulate ?Low Power at High Speed
? 3.0V to 5.25V Operating Voltage
?Operating Voltages Down to 1.0V Using On-Chip Switch Mode Pump (SMP)
?Industrial Temperature Range: -40°C to +85°C ■Advanced Peripherals (PSoC Blocks)
?12 Rail-to-Rail Analog PSoC Blocks Provide:
- Up to 14-Bit ADCs - Up to 9-Bit DACs
- Programmable Gain Amplifiers
- Programmable Filters and Comparators ?16 Digital PSoC Blocks Provide:
- 8- to 32-Bit Timers, Counters, and PWMs - CRC and PRS Modules - Up to 4 Full-Duplex UARTs
- Multiple SPI ? Masters or Slaves - Connectable to all GPIO Pins
?Complex Peripherals by Combining Blocks
■Precision, Programmable Clocking
?Internal ±2.5% 24/48 MHz Oscillator
?24/48 MHz with Optional 32.768 kHz Crystal ?Optional External Oscillator, up to 24 MHz ?Internal Oscillator for Watchdog and Sleep ■Flexible On-Chip Memory
?32K Bytes Flash Program Storage 50,000
Erase/Write Cycles
?2K Bytes SRAM Data Storage
?In-System Serial Programming (ISSP)?Partial Flash Updates ?Flexible Protection Modes ?EEPROM Emulation in Flash ■Programmable Pin Configurations
?25 mA Sink on all GPIO
?Pull up, Pull down, High Z, Strong, or Open
Drain Drive Modes on all GPIO ?Up to 12 Analog Inputs on GPIO
?Four 40 mA Analog Outputs on GPIO ?Configurable Interrupt on all GPIO
■Additional System Resources
?I 2C ? Slave, Master, and Multi-Master to
400 kHz
?Watchdog and Sleep Timers
?User-Configurable Low Voltage Detection ?Integrated Supervisory Circuit
?On-Chip Precision Voltage Reference ■Complete Development Tools
?Free Development Software
(PSoC Designer?)
?Full-Featured, In-Circuit Emulator and
Programmer
?Full Speed Emulation
?Complex Breakpoint Structure ?128K Bytes Trace Memory ?Complex Events
? C Compilers, Assembler, and Linker
tors, to simplify programming of real time embedded events. Program execution is timed and protected using the included Sleep and Watch Dog Timers (WDT).
Memory encompasses 32 KB of Flash for program storage, 2 KB of SRAM for data storage, and up to 2 KB of EEPROM emu-lated using the Flash. Program Flash utilizes four protection lev-els on blocks of 64 bytes, allowing customized software IP protection.
The PSoC device incorporates flexible internal clock genera-tors, including a 24 MHz IMO (internal main oscillator) accurate to 2.5% over temperature and voltage. The 24 MHz IMO can also be doubled to 48 MHz for use by the digital system. A low power 32 kHz ILO (internal low speed oscillator) is provided for the Sleep timer and WDT. If crystal accuracy is desired, the ECO (32.768 kHz external crystal oscillator) is available for use as a Real Time Clock (RTC) and can optionally generate a crys-tal-accurate 24 MHz system clock using a PLL. The clocks, together with programmable clock dividers (as a System Resource), provide the flexibility to integrate almost any timing requirement into the PSoC device.
PSoC GPIOs provide connection to the CPU, digital and analog resources of the device. Each pin’s drive mode may be selected from eight options, allowing great flexibility in external interfac-ing. Every pin also has the capability to generate a system inter-rupt on high level, low level, and change from last read.
The Digital System
The Digital System is composed of 16 digital PSoC blocks. Each block is an 8-bit resource that can be used alone or com-bined with other blocks to form 8, 16, 24, and 32-bit peripherals, which are called user module references. Digital peripheral con-figurations include those listed below.
■PWMs (8 to 32 bit)
■PWMs with Dead band (8 to 32 bit)
■Counters (8 to 32 bit)
■Timers (8 to 32 bit)
■UART 8 bit with selectable parity (up to 4)
■SPI master and slave (up to 4 each)
■I2C slave and multi-master (1 available as a System Resource)
■Cyclical Redundancy Checker/Generator (8 to 32 bit)
■IrDA (up to 4)
■Pseudo Random Sequence Generators (8 to 32 bit)
The digital blocks can be connected to any GPIO through a series of global buses that can route any signal to any pin. The buses also allow for signal multiplexing and for performing logic operations. This configurability frees your designs from the con-straints of a fixed peripheral controller.
Digital blocks are provided in rows of four, where the number of blocks varies by PSoC device family. This allows you the opti-mum choice of system resources for your application. Family resources are shown in the table titled PSoC Device Character-istics on page 3.
Digital System Block Diagram
The Analog System
The Analog System is composed of 12 configurable blocks, each comprised of an opamp circuit allowing the creation of complex analog signal flows. Analog peripherals are very flexi-ble and can be customized to support specific application requirements. Some of the more common PSoC analog func-tions (most available as user modules) are listed below.
■Analog-to-digital converters (up to 4, with 6- to 14-bit resolu-tion, selectable as Incremental, Delta Sigma, and SAR)
■Filters (2, 4, 6, or 8 pole band-pass, low-pass, and notch)
■Amplifiers (up to 4, with selectable gain to 48x)
■Instrumentation amplifiers (up to 2, with selectable gain to 93x)
■Comparators (up to 4, with 16 selectable thresholds)
■DACs (up to 4, with 6- to 9-bit resolution)
■Multiplying DACs (up to 4, with 6- to 9-bit resolution)
■High current output drivers (four with 40 mA drive as a Core Resource)
■1.3V reference (as a System Resource)
■DTMF Dialer ■Modulators ■Correlators ■Peak Detectors
■
Many other topologies possible
Analog blocks are provided in columns of three, which includes one CT (Continuous Time) and two SC (Switched Capacitor)blocks, as shown in the figure below.
Analog System Block Diagram
Additional System Resources
System Resources, some of which have been previously listed,provide additional capability useful to complete systems.Resources include a multiplier, decimator, switch mode pump,low voltage detection, and power on reset. Statements describ-ing the merits of each system resource are presented below.
■
Digital clock dividers provide three customizable clock fre-quencies for use in applications. The clocks can be routed to both the digital and analog systems. Additional clocks can be generated using digital PSoC blocks as clock dividers.■Multiply accumulate (MAC) provides fast 8-bit multiplier with 32-bit accumulate, to assist in general math and digital filters.■
The decimator provides a custom hardware filter for digital signal, processing applications including the creation of Delta Sigma ADCs.
■
The I2C module provides 100 and 400 kHz communication over two wires. Slave, master, and multi-master modes are all supported.
■
Low Voltage Detection (LVD) interrupts can signal the appli-cation of falling voltage levels, while the advanced POR (Power On Reset) circuit eliminates the need for a system supervisor.
■An internal 1.3 voltage reference provides an absolute refer-ence for the analog system, including ADCs and DACs.■
An integrated switch mode pump (SMP) generates normal operating voltages from a single 1.2V battery cell, providing a low cost boost converter.
PSoC Device Characteristics
Depending on your PSoC device characteristics, the digital and analog systems can have 16, 8, or 4 digital blocks and 12, 6, or 4 analog blocks. The following table lists the resources available for specific PSoC device groups. The PSoC device covered by this data sheet is highlighted below.
PSoC Device Characteristics
PSoC Part Number D i g i t a l I O
D i g i t a l R o w s
D i g i t a l B l o c k s
A n a l o g I n p u t s
A n a l o g O u t p u t s
A n a l o g C o l u m n s
A n a l o g
B l o c k s
S R A M S i z e F l a s h S i z e CY8C29x66up to 644161244122K 32K CY8C27x43
up to 4428124412256 Bytes 16K CY8C24x945614482261K 16K CY8C24x23A up to 241412226256 Bytes 4K CY8C21x34up to 281428024a a.Limited analog functionality .
512 Bytes 8K CY8C21x23
16148024a 256 Bytes 4K CY8C20x34
up to 28
28
3b
b.Two analog blocks and one CapSense.
512 Bytes
8K
Getting Started
The quickest path to understanding the PSoC silicon is by read-ing this data sheet and using the PSoC Designer Integrated Development Environment (IDE). This data sheet is an over-view of the PSoC integrated circuit and presents specific pin, register, and electrical specifications. For in-depth information, along with detailed programming information, reference the PSoC Mixed-Signal Array Technical Reference Manual.
For up-to-date Ordering, Packaging, and Electrical Specification information, reference the latest PSoC device data sheets on the web at https://www.doczj.com/doc/425309258.html,/psoc.
Development Kits
Development Kits are available from the following distributors: Digi-Key, Avnet, Arrow, and Future. The Cypress Online Store at https://www.doczj.com/doc/425309258.html,/cypressstore/ contains develop-ment kits, C compilers, and all accessories for PSoC develop-ment. Click on PSoC (Programmable System-on-Chip) to view a current list of available items.
Technical Training Modules
Free PSoC technical training modules are available for users new to PSoC. Training modules cover designing, debugging, advanced analog and CapSense. Go to http:// https://www.doczj.com/doc/425309258.html,/techtrain.
Consultants
Certified PSoC Consultants offer everything from technical assistance to completed PSoC designs. To contact or become a PSoC Consultant, go to the following Cypress support web site: https://www.doczj.com/doc/425309258.html,/support/cypros.cfm.
Technical Support
PSoC application engineers take pride in fast and accurate response. They can be reached with a 4-hour guaranteed response at https://www.doczj.com/doc/425309258.html,/support/login.cfm. Application Notes
A long list of application notes will assist you in every aspect of your design effort. To view the PSoC application notes, go to the https://www.doczj.com/doc/425309258.html, web site and select Application Notes under the Design Resources list located in the center of the web page. Application notes are listed by date by default.Development Tools
PSoC Designer is a Microsoft? Windows-based, integrated development environment for the Programmable System-on-Chip (PSoC) devices. The PSoC Designer IDE and application runs on Windows NT 4.0, Windows 2000, Windows Millennium (Me), or Windows XP. (Reference the PSoC Designer Func-tional Flow diagram below.)
PSoC Designer helps the customer to select an operating con-figuration for the PSoC, write application code that uses the PSoC, and debug the application. This system provides design database management by project, an integrated debugger with In-Circuit Emulator, in-system programming support, and the CYASM macro assembler for the CPUs.
PSoC Designer also supports a high-level C language compiler developed specifically for the devices in the family.
PSoC Designer Subsystems
PSoC Designer Software Subsystems
Device Editor
The Device Editor subsystem allows the user to select different onboard analog and digital components called user modules using the PSoC blocks. Examples of user modules are ADCs, DACs, Amplifiers, and Filters.
The device editor also supports easy development of multiple configurations and dynamic reconfiguration. Dynamic configu-ration allows for changing configurations at run time.
PSoC Designer sets up power-on initialization tables for selected PSoC block configurations and creates source code for an application framework. The framework contains software to operate the selected components and, if the project uses more than one operating configuration, contains routines to switch between different sets of PSoC block configurations at run time. PSoC Designer can print out a configuration sheet for a given project configuration for use during application pro-gramming in conjunction with the Device Data Sheet. Once the framework is generated, the user can add application-specific code to flesh out the framework. It’s also possible to change the selected components and regenerate the framework. Design Browser
The Design Browser allows users to select and import precon-figured designs into the user’s project. Users can easily browse a catalog of preconfigured designs to facilitate time-to-design. Examples provided in the tools include a 300-baud modem, LIN Bus master and slave, fan controller, and magnetic card reader. Application Editor
In the Application Editor you can edit your C language and Assembly language source code. You can also assemble, com-pile, link, and build.
Assembler. The macro assembler allows the assembly code to be merged seamlessly with C code. The link libraries auto-matically use absolute addressing or can be compiled in relative mode, and linked with other software modules to get absolute addressing.
C Language Compiler. A C language compiler is available that supports Cypress’ PSoC family devices. Even if you have never worked in the C language before, the product quickly allows you to create complete C programs for the PSoC family devices.
The embedded, optimizing C compiler provides all the features of C tailored to the PSoC architecture. It comes complete with embedded libraries providing port and bus operations, standard keypad and display support, and extended math functionality.Debugger
The PSoC Designer Debugger subsystem provides hardware in-circuit emulation, allowing the designer to test the program in a physical system while providing an internal view of the PSoC device. Debugger commands allow the designer to read and program and read and write data memory, read and write IO registers, read and write CPU registers, set and clear break-points, and provide program run, halt, and step control. The debugger also allows the designer to create a trace buffer of registers and memory locations of interest.
Online Help System
The online help system displays online, context-sensitive help for the user. Designed for procedural and quick reference, each functional subsystem has its own context-sensitive help. This system also provides tutorials and links to FAQs and an Online Support Forum to aid the designer in getting started. Hardware Tools
In-Circuit Emulator
A low cost, high functionality ICE (In-Circuit Emulator) is avail-able for development support. This hardware has the capability to program single devices.
The emulator consists of a base unit that connects to the PC by way of the USB port. The base unit is universal and will operate with all PSoC devices. Emulation pods for each device family are available separately. The emulation pod takes the place of the PSoC device in the target board and performs full speed (24 MHz) operation.
Designing with User Modules
The development process for the PSoC device differs from that of a traditional fixed function microprocessor. The configurable analog and digital hardware blocks give the PSoC architecture a unique flexibility that pays dividends in managing specification change during development and by lowering inventory costs. These configurable resources, called PSoC Blocks, have the ability to implement a wide variety of user-selectable functions. Each block has several registers that determine its function and connectivity to other blocks, multiplexers, buses, and to the IO pins. Iterative development cycles permit you to adapt the hard-ware as well as the software. This substantially lowers the risk of having to select a different part to meet the final design requirements.
To speed the development process, the PSoC Designer Inte-grated Development Environment (IDE) provides a library of pre-built, pre-tested hardware peripheral functions, called “User Modules.” User modules make selecting and implementing peripheral devices simple, and come in analog, digital, and mixed signal varieties. The standard User Module library con-tains over 50 common peripherals such as ADCs, DACs Tim-ers, Counters, UARTs, and other not-so common peripherals such as DTMF Generators and Bi-Quad analog filter sections. Each user module establishes the basic register settings that implement the selected function. It also provides parameters that allow you to tailor its precise configuration to your particular application. For example, a Pulse Width Modulator User Mod-ule configures one or more digital PSoC blocks, one for each 8 bits of resolution. The user module parameters permit you to establish the pulse width and duty cycle. User modules also provide tested software to cut your development time. The user module application programming interface (API) provides high-level functions to control and respond to hardware events at run-time. The API also provides optional interrupt service rou-tines that you can adapt as needed.
The API functions are documented in user module data sheets that are viewed directly in the PSoC Designer IDE. These data sheets explain the internal operation of the user module and provide performance specifications. Each data sheet describes the use of each user module parameter and documents the set-ting of each register controlled by the user module.
The development process starts when you open a new project and bring up the Device Editor, a graphical user interface (GUI) for configuring the hardware. You pick the user modules you need for your project and map them onto the PSoC blocks with point-and-click simplicity. Next, you build signal chains by inter-connecting user modules to each other and the IO pins. At this stage, you also configure the clock source connections and enter parameter values directly or by selecting values from drop-down menus. When you are ready to test the hardware configuration or move on to developing code for the project, you perform the “Generate Application” step. This causes PSoC Designer to generate source code that automatically configures the device to your specification and provides the high-level user module API functions.
User Module and Source Code Development Flows The next step is to write your main program, and any sub-rou-
tines using PSoC Designer’s Application Editor subsystem. The Application Editor includes a Project Manager that allows you to open the project source code files (including all gener-ated code files) from a hierarchal view. The source code editor provides syntax coloring and advanced edit features for both C and assembly language. File search capabilities include simple string searches and recursive “grep-style” patterns. A single mouse click invokes the Build Manager. It employs a profes-sional-strength “makefile” system to automatically analyze all file dependencies and run the compiler and assembler as nec-essary. Project-level options control optimization strategies used by the compiler and linker. Syntax errors are displayed in a console window. Double clicking the error message takes you directly to the offending line of source code. When all is correct,
the linker builds a HEX file image suitable for programming. The last step in the development process takes place inside the PSoC Designer’s Debugger subsystem. The Debugger down-loads the HEX image to the In-Circuit Emulator (ICE) where it runs at full speed. Debugger capabilities rival those of systems costing many times more. In addition to traditional single-step, run-to-breakpoint and watch-variable features, the Debugger provides a large trace buffer and allows you define complex breakpoint events that include monitoring address and data bus values, memory locations and external signals.
Document Conventions
Acronyms Used
The following table lists the acronyms that are used in this doc-ument.
Units of Measure
A units of measure table is located in the Electrical Specifica-tions section. Table3-1 on page19 lists all the abbreviations used to measure the PSoC devices.
Numeric Naming
Hexidecimal numbers are represented with all letters in upper-case with an appended lowercase ‘h’ (for example, ‘14h’ or ‘3Ah’). Hexidecimal numbers may also be represented by a ‘0x’prefix, the C coding convention. Binary numbers have an appended lowercase ‘b’ (e.g., 01010100b’ or ‘01000011b’). Numbers not indicated by an ‘h’, ‘b’, or 0x are decimal.Table of Contents
For an in depth discussion and more information on your PSoC device, obtain the PSoC Mixed Signal Array Technical Refer-ence Manual. This document encompasses and is organized into the following chapters and sections.
1.Pin Information (8)
1.1Pinouts (8)
1.1.128-Pin Part Pinout (8)
1.1.244-Pin Part Pinout (9)
1.1.348-Pin Part Pinouts (10)
1.1.4100-Pin Part Pinout (12)
1.1.5100-Pin Part Pinout (On-Chip Debug) (14)
2.Register Reference (16)
2.1Register Conventions (16)
2.1.1Abbreviations Used (16)
2.2Register Mapping Tables (16)
3.Electrical Specifications (19)
3.1Absolute Maximum Ratings (20)
3.2Operating Temperature (20)
3.3DC Electrical Characteristics (21)
3.3.1DC Chip-Level Specifications (21)
3.3.2DC General Purpose IO Specifications (21)
3.3.3DC Operational Amplifier Specifications (22)
3.3.4DC Low Power Comparator Specifications (23)
3.3.5DC Analog Output Buffer Specifications (24)
3.3.6DC Switch Mode Pump Specifications (25)
3.3.7DC Analog Reference Specifications (26)
3.3.8DC Analog PSoC Block Specifications (27)
3.3.9DC POR, SMP, and LVD Specifications (27)
3.3.10DC Programming Specifications (28)
3.4AC Electrical Characteristics (29)
3.4.1AC Chip-Level Specifications (29)
3.4.2AC General Purpose IO Specifications (31)
3.4.3AC Operational Amplifier Specifications (32)
3.4.4AC Low Power Comparator Specifications (34)
3.4.5AC Digital Block Specifications (34)
3.4.6AC Analog Output Buffer Specifications (35)
3.4.7AC External Clock Specifications (36)
3.4.8AC Programming Specifications (36)
3.4.9AC I2C Specifications (37)
4.Packaging Information (38)
4.1Packaging Dimensions (38)
4.2Thermal Impedances (42)
4.3Capacitance on Crystal Pins (43)
4.4Solder Reflow Peak Temperature (43)
5.Development Tool Selection (44)
5.1Software (44)
5.1.1PSoC Designer (44)
5.1.2PSoC Express (44)
5.1.3PSoC Programmer (44)
5.1.4CY3202-C iMAGEcraft C Compiler (44)
5.2Development Kits (44)
5.2.1CY3215-DK Basic Development Kit (44)
5.2.2CY3210-ExpressDK Development Kit (45)
5.3Evaluation Tools (45)
5.3.1CY3210-MiniProg1 (45)
5.3.2CY3210-PSoCEval1 (45)
5.3.3CY3214-PSoCEvalUSB (45)
5.4Device Programmers (45)
5.4.1CY3216 Modular Programmer (45)
5.4.2CY3207ISSP In-System Serial Programmer (ISSP) (45)
5.5Accessories (Emulation and Programming) (46)
5.63rd-Party Tools (46)
5.7Build a PSoC Emulator into Your Board (46)
6.Ordering Information (47)
6.1Ordering Code Definitions (47)
7.Sales and Service Information (48)
7.1Revision History (48)
7.2Copyrights and Code Protection (48)
Acronym Description
AC alternating current
ADC analog-to-digital converter
API application programming interface
CPU central processing unit
CT continuous time
DAC digital-to-analog converter
DC direct current
ECO external crystal oscillator
EEPROM electrically erasable programmable read-only memory FSR full scale range
GPIO general purpose IO
GUI graphical user interface
HBM human body model
ICE in-circuit emulator
ILO internal low speed oscillator
IMO internal main oscillator
IO input/output
IPOR imprecise power on reset
LSb least-significant bit
LVD low voltage detect
MSb most-significant bit
PC program counter
PLL phase-locked loop
POR power on reset
PPOR precision power on reset
PSoC?Programmable System-on-Chip?
PWM pulse width modulator
SC switched capacitor
SLIMO slow IMO
SMP switch mode pump
SRAM static random access memory
1.Pin Information
This chapter describes, lists, and illustrates the CY8C29x66 PSoC device pins and pinout configurations.
1.1Pinouts
The CY8C29x66 PSoC device is available in a variety of packages which are listed and illustrated in the following tables. Every port pin (labeled with a “P”) is capable of Digital IO. However, Vss, Vdd, SMP, and XRES are not capable of Digital IO.
1.1.128-Pin Part Pinout
Table 1-1. 28-Pin Part Pinout (PDIP, SSOP, SOIC)
Table 1-2. 44-Pin Part Pinout (TQFP)
Table 1-3. 48-Pin Part Pinout (SSOP)
Table 1-4. 48-Pin Part Pinout (QFN**)
1.1.4100-Pin Part Pinout Table 1-5. 100-Pin Part Pinout (TQFP)
Pin No.
Type
Name Description Pin
No.
Type
Name Description Digital Analog Digital Analog
1NC No connection.51NC No connection.
2NC No connection.52IO P5[0]
3IO I P0[1]Analog column mux input.53IO P5[2]
4IO P2[7]54IO P5[4]
5IO P2[5]55IO P5[6]
6IO I P2[3]Direct switched capacitor block input.56IO P3[0]
7IO I P2[1]Direct switched capacitor block input.57IO P3[2]
8IO P4[7]58IO P3[4]
9IO P4[5]59IO P3[6]
10IO P4[3]60NC No connection.
11IO P4[1]61NC No connection.
12NC No connection.62Input XRES Active high external reset with internal pull
down.
13NC No connection.63IO P4[0]
14Power SMP Switch Mode Pump (SMP) connection to
external components required.
64IO P4[2]
15Power Vss Ground connection.65Power Vss Ground connection.
16IO P3[7]66IO P4[4]
17IO P3[5]67IO P4[6]
18IO P3[3]68IO I P2[0]Direct switched capacitor block input.
19IO P3[1]69IO I P2[2]Direct switched capacitor block input.
20IO P5[7]70IO P2[4]External Analog Ground (AGND).
21IO P5[5]71NC No connection.
22IO P5[3]72IO P2[6]External Voltage Reference (VREF).
23IO P5[1]73NC No connection.
24IO P1[7]I2C Serial Clock (SCL).74IO I P0[0]Analog column mux input.
25NC No connection.75NC No connection.
26NC No connection.76NC No connection.
27NC No connection.77IO IO P0[2]Analog column mux input and column output. 28IO P1[5]I2C Serial Data (SDA).78NC No connection.
29IO P1[3]79IO IO P0[4]Analog column mux input and column output. 30IO P1[1]Crystal (XTALin), I2C Serial Clock (SCL),
ISSP-SCLK*.
80NC No connection.
31NC No connection.81IO I P0[6]Analog column mux input.
32Power Vdd Supply voltage.82Power Vdd Supply voltage.
33NC No connection.83Power Vdd Supply voltage.
34Power Vss Ground connection.84Power Vss Ground connection.
35NC No connection.85Power Vss Ground connection.
36IO P7[7]86IO P6[0]
37IO P7[6]87IO P6[1]
38IO P7[5]88IO P6[2]
39IO P7[4]89IO P6[3]
40IO P7[3]90IO P6[4]
41IO P7[2]91IO P6[5]
42IO P7[1]92IO P6[6]
43IO P7[0]93IO P6[7]
44IO P1[0]Crystal (XTALout), I2C Serial Data (SDA),
ISSP-SDATA*.
94NC No connection.
45IO P1[2]95IO I P0[7]Analog column mux input.
46IO P1[4]Optional External Clock Input (EXTCLK).96NC No connection.
47IO P1[6]97IO IO P0[5]Analog column mux input and column output. 48NC No connection.98NC No connection.
49NC No connection.99IO IO P0[3]Analog column mux input and column output. 50NC No connection.100NC No connection.
LEGEND: A = Analog, I = Input, and O = Output.
* These are the ISSP pins, which are not High Z at POR (Power On Reset). See the PSoC Mixed-Signal Array Technical Reference Manual for details.
CY8C29866 100-Pin PSoC Device
1.1.5100-Pin Part Pinout (On-Chip Debug)
The 100-pin TQFP part is for the CY8C29000 On-Chip Debug (OCD) PSoC device.Note This part is only used for in-circuit debugging. It is NOT available for production Table 1-6. 100-Pin Part Pinout (TQFP)
Pin No.D i g i t a l
A n a l o g
Name
Description
Pin No.D i g i t a l
A n a l o g
Name Description
1NC No connection.51IO M P1[6]2NC
No connection.
52IO M P5[0]3IO I, M P0[1]Analog column mux input.
53IO M P5[2]4IO M P2[7]54IO M P5[4]5IO M P2[5]55IO M P5[6]6IO I, M P2[3]Direct switched capacitor block input.56IO M P3[0]7IO I, M P2[1]Direct switched capacitor block input.
57IO M P3[2]8IO M P4[7]58IO M P3[4]9IO M P4[5]59IO M
P3[6]10IO M P4[3]60HCLK OCD high-speed clock output.11IO M P4[1]
61CCLK OCD CPU clock output.
12OCDE OCD even data IO.62Input XRES Active high pin reset with internal pull down.
13OCDO OCD odd data output.63IO M P4[0]14NC
No connection.
64IO M P4[2]15Power Vss Ground connection.
65Power Vss Ground connection.
16IO M P3[7]66IO M P4[4]17IO M P3[5]67IO M P4[6]18IO M P3[3]68IO I, M P2[0]Direct switched capacitor block input.19IO M P3[1]69IO I, M P2[2]Direct switched capacitor block input.20IO M P5[7]70IO P2[4]External Analog Ground (AGND) input.21IO M P5[5]71NC No connection.
22IO M P5[3]72IO P2[6]External Voltage Reference (VREF) input.23IO M P5[1]73NC No connection.
24IO M P1[7]
I2C Serial Clock (SCL).74IO
I
P0[0]Analog column mux input.25NC No connection.75NC No connection.26NC No connection.76NC No connection.
27NC
No connection.
77IO I, M P0[2]Analog column mux input and column output.28IO P1[5]I2C Serial Data (SDA)
78NC No connection.
29IO P1[3]79IO
I, M
P0[4]Analog column mux input and column output.30IO P1[1]
Crystal (XTALin), I2C Serial Clock (SCL), ISSP SCLK*.80NC
No connection.
31NC
No connection.
81IO I, M P0[6]Analog column mux input.32Power Vss Ground connection.
82Power Vdd
Supply voltage.33USB D+83NC
No connection.
34USB D-84Power Vss
Ground connection.35Power Vdd Supply voltage.
85NC No connection.36IO P7[7]86NC No connection.37IO P7[6]87NC No connection.38IO P7[5]88NC No connection.39IO P7[4]89NC No connection.40IO P7[3]90NC No connection.41IO P7[2]91NC No connection.42IO P7[1]92NC No connection.43IO
P7[0]93NC No connection.44NC No connection.94NC
No connection.
45NC No connection.95IO I, M P0[7]
Analog column mux input.46NC No connection.96NC
No connection.
47NC No connection.
97IO IO, M P0[5]
Analog column mux input and column output.48IO P1[0]Crystal (XTALout), I2C Serial Data (SDA), ISSP SDATA*.
98NC No connection.
49IO P1[2]99IO
IO, M P0[3]
Analog column mux input and column output.50
IO
P1[4]
Optional External Clock Input (EXTCLK).
100
NC
No connection.
LEGEND A = Analog, I = Input, O = Output, NC = No Connection, M = Analog Mux Input, OCD = On-Chip Debugger.
* These are the ISSP pins, which are not High Z at POR. See the PSoC Mixed-Signal Array Technical Reference Manual for details.
CY8C29000 OCD
Not for Production
2.Register Reference
This chapter lists the registers of the CY8C29x66 PSoC device. For detailed register information, reference the PSoC Mixed-Signal Array Technical Reference Manual.
2.1Register Conventions
2.1.1Abbreviations Used
The register conventions specific to this section are listed in the following table. 2.2Register Mapping Tables
The PSoC device has a total register address space of 512 bytes. The register space is referred to as IO space and is divided into two banks. The XOI bit in the Flag register (CPU_F) determines which bank the user is currently in. When the XOI bit is set the user is in Bank 1.
Note In the following register mapping tables, blank fields are reserved and should not be accessed.
Convention Description R Read register or bit(s)
W Write register or bit(s)
L Logical register or bit(s)
C Clearable register or bit(s)
#Access is bit specific
Register Map Bank 0 Table: User Space
Name Addr (0,Hex)Access Name Addr (0,Hex)Access Name Addr (0,Hex)Access Name Addr (0,Hex)Access PRT0DR00RW DBB20DR040#ASC10CR080RW RDI2RI C0RW PRT0IE01RW DBB20DR141W ASC10CR181RW RDI2SYN C1RW PRT0GS02RW DBB20DR242RW ASC10CR282RW RDI2IS C2RW PRT0DM203RW DBB20CR043#ASC10CR383RW RDI2LT0C3RW PRT1DR04RW DBB21DR044#ASD11CR084RW RDI2LT1C4RW PRT1IE05RW DBB21DR145W ASD11CR185RW RDI2RO0C5RW PRT1GS06RW DBB21DR246RW ASD11CR286RW RDI2RO1C6RW PRT1DM207RW DBB21CR047#ASD11CR387RW C7
PRT2DR08RW DCB22DR048#ASC12CR088RW RDI3RI C8RW PRT2IE09RW DCB22DR149W ASC12CR189RW RDI3SYN C9RW PRT2GS0A RW DCB22DR24A RW ASC12CR28A RW RDI3IS CA RW PRT2DM20B RW DCB22CR04B#ASC12CR38B RW RDI3LT0CB RW PRT3DR0C RW DCB23DR04C#ASD13CR08C RW RDI3LT1CC RW PRT3IE0D RW DCB23DR14D W ASD13CR18D RW RDI3RO0CD RW PRT3GS0E RW DCB23DR24E RW ASD13CR28E RW RDI3RO1CE RW PRT3DM20F RW DCB23CR04F#ASD13CR38F RW CF
PRT4DR10RW DBB30DR050#ASD20CR090RW CUR_PP D0RW PRT4IE11RW DBB30DR151W ASD20CR191RW STK_PP D1RW PRT4GS12RW DBB30DR252RW ASD20CR292RW D2
PRT4DM213RW DBB30CR053#ASD20CR393RW IDX_PP D3RW PRT5DR14RW DBB31DR054#ASC21CR094RW MVR_PP D4RW PRT5IE15RW DBB31DR155W ASC21CR195RW MVW_PP D5RW PRT5GS16RW DBB31DR256RW ASC21CR296RW I2C_CFG D6RW PRT5DM217RW DBB31CR057#ASC21CR397RW I2C_SCR D7# PRT6DR18RW DCB32DR058#ASD22CR098RW I2C_DR D8RW PRT6IE19RW DCB32DR159W ASD22CR199RW I2C_MSCR D9# PRT6GS1A RW DCB32DR25A RW ASD22CR29A RW INT_CLR0DA RW PRT6DM21B RW DCB32CR05B#ASD22CR39B RW INT_CLR1DB RW PRT7DR1C RW DCB33DR05C#ASC23CR09C RW INT_CLR2DC RW PRT7IE1D RW DCB33DR15D W ASC23CR19D RW INT_CLR3DD RW PRT7GS1E RW DCB33DR25E RW ASC23CR29E RW INT_MSK3DE RW PRT7DM21F RW DCB33CR05F#ASC23CR39F RW INT_MSK2DF RW DBB00DR020#AMX_IN60RW A0INT_MSK0E0RW DBB00DR121W61A1INT_MSK1E1RW DBB00DR222RW62A2INT_VC E2RC DBB00CR023#ARF_CR63RW A3RES_WDT E3W DBB01DR024#CMP_CR064#A4DEC_DH E4RC DBB01DR125W ASY_CR65#A5DEC_DL E5RC DBB01DR226RW CMP_CR166RW A6DEC_CR0E6RW DBB01CR027#67A7DEC_CR1E7RW DCB02DR028#68MUL1_X A8W MUL0_X E8W DCB02DR129W69MUL1_Y A9W MUL0_Y E9W DCB02DR22A RW6A MUL1_DH AA R MUL0_DH EA R DCB02CR02B#6B MUL1_DL AB R MUL0_DL EB R DCB03DR02C#TMP_DR06C RW ACC1_DR1AC RW ACC0_DR1EC RW DCB03DR12D W TMP_DR16D RW ACC1_DR0AD RW ACC0_DR0ED RW DCB03DR22E RW TMP_DR26E RW ACC1_DR3AE RW ACC0_DR3EE RW DCB03CR02F#TMP_DR36F RW ACC1_DR2AF RW ACC0_DR2EF RW DBB10DR030#ACB00CR370RW RDI0RI B0RW F0
DBB10DR131W ACB00CR071RW RDI0SYN B1RW F1
DBB10DR232RW ACB00CR172RW RDI0IS B2RW F2
DBB10CR033#ACB00CR273RW RDI0LT0B3RW F3
DBB11DR034#ACB01CR374RW RDI0LT1B4RW F4
DBB11DR135W ACB01CR075RW RDI0RO0B5RW F5
DBB11DR236RW ACB01CR176RW RDI0RO1B6RW F6
DBB11CR037#ACB01CR277RW B7CPU_F F7RL DCB12DR038#ACB02CR378RW RDI1RI B8RW F8
DCB12DR139W ACB02CR079RW RDI1SYN B9RW F9
DCB12DR23A RW ACB02CR17A RW RDI1IS BA RW FA
DCB12CR03B#ACB02CR27B RW RDI1LT0BB RW FB
DCB13DR03C#ACB03CR37C RW RDI1LT1BC RW FC
DCB13DR13D W ACB03CR07D RW RDI1RO0BD RW FD
DCB13DR23E RW ACB03CR17E RW RDI1RO1BE RW CPU_SCR1FE# DCB13CR03F#ACB03CR27F RW BF CPU_SCR0FF# Blank fields are Reserved and should not be accessed.# Access is bit specific.
Register Map Bank 1 Table: Configuration Space
Name Addr(1,Hex)Access Name Addr(1,Hex)Access Name Addr(1,Hex)Access Name Addr(1,Hex)Access PRT0DM000RW DBB20FN40RW ASC10CR080RW RDI2RI C0RW PRT0DM101RW DBB20IN41RW ASC10CR181RW RDI2SYN C1RW PRT0IC002RW DBB20OU42RW ASC10CR282RW RDI2IS C2RW PRT0IC103RW43ASC10CR383RW RDI2LT0C3RW PRT1DM004RW DBB21FN44RW ASD11CR084RW RDI2LT1C4RW PRT1DM105RW DBB21IN45RW ASD11CR185RW RDI2RO0C5RW PRT1IC006RW DBB21OU46RW ASD11CR286RW RDI2RO1C6RW PRT1IC107RW47ASD11CR387RW C7
PRT2DM008RW DCB22FN48RW ASC12CR088RW RDI3RI C8RW PRT2DM109RW DCB22IN49RW ASC12CR189RW RDI3SYN C9RW PRT2IC00A RW DCB22OU4A RW ASC12CR28A RW RDI3IS CA RW PRT2IC10B RW4B ASC12CR38B RW RDI3LT0CB RW PRT3DM00C RW DCB23FN4C RW ASD13CR08C RW RDI3LT1CC RW PRT3DM10D RW DCB23IN4D RW ASD13CR18D RW RDI3RO0CD RW PRT3IC00E RW DCB23OU4E RW ASD13CR28E RW RDI3RO1CE RW PRT3IC10F RW4F ASD13CR38F RW CF
PRT4DM010RW DBB30FN50RW ASD20CR090RW GDI_O_IN D0RW PRT4DM111RW DBB30IN51RW ASD20CR191RW GDI_E_IN D1RW PRT4IC012RW DBB30OU52RW ASD20CR292RW GDI_O_OU D2RW PRT4IC113RW53ASD20CR393RW GDI_E_OU D3RW PRT5DM014RW DBB31FN54RW ASC21CR094RW D4
PRT5DM115RW DBB31IN55RW ASC21CR195RW D5
PRT5IC016RW DBB31OU56RW ASC21CR296RW D6
PRT5IC117RW57ASC21CR397RW D7
PRT6DM018RW DCB32FN58RW ASD22CR098RW D8
PRT6DM119RW DCB32IN59RW ASD22CR199RW D9
PRT6IC01A RW DCB32OU5A RW ASD22CR29A RW DA
PRT6IC11B RW5B ASD22CR39B RW DB
PRT7DM01C RW DCB33FN5C RW ASC23CR09C RW DC
PRT7DM11D RW DCB33IN5D RW ASC23CR19D RW OSC_GO_EN DD RW PRT7IC01E RW DCB33OU5E RW ASC23CR29E RW OSC_CR4DE RW PRT7IC11F RW5F ASC23CR39F RW OSC_CR3DF RW DBB00FN20RW CLK_CR060RW A0OSC_CR0E0RW DBB00IN21RW CLK_CR161RW A1OSC_CR1E1RW DBB00OU22RW ABF_CR062RW A2OSC_CR2E2RW 23AMD_CR063RW A3VLT_CR E3RW DBB01FN24RW64A4VLT_CMP E4R DBB01IN25RW65A5E5
DBB01OU26RW AMD_CR166RW A6E6 27ALT_CR067RW A7DEC_CR2E7RW DCB02FN28RW ALT_CR168RW A8IMO_TR E8W DCB02IN29RW CLK_CR269RW A9ILO_TR E9W DCB02OU2A RW6A AA BDG_TR EA RW 2B6B AB ECO_TR EB W DCB03FN2C RW TMP_DR06C RW AC EC
DCB03IN2D RW TMP_DR16D RW AD ED
DCB03OU2E RW TMP_DR26E RW AE EE 2F TMP_DR36F RW AF EF
DBB10FN30RW ACB00CR370RW RDI0RI B0RW F0
DBB10IN31RW ACB00CR071RW RDI0SYN B1RW F1
DBB10OU32RW ACB00CR172RW RDI0IS B2RW F2 33ACB00CR273RW RDI0LT0B3RW F3
DBB11FN34RW ACB01CR374RW RDI0LT1B4RW F4
DBB11IN35RW ACB01CR075RW RDI0RO0B5RW F5
DBB11OU36RW ACB01CR176RW RDI0RO1B6RW F6 37ACB01CR277RW B7CPU_F F7RL DCB12FN38RW ACB02CR378RW RDI1RI B8RW F8
DCB12IN39RW ACB02CR079RW RDI1SYN B9RW F9
DCB12OU3A RW ACB02CR17A RW RDI1IS BA RW FLS_PR1FA RW 3B ACB02CR27B RW RDI1LT0BB RW FB
DCB13FN3C RW ACB03CR37C RW RDI1LT1BC RW FC
DCB13IN3D RW ACB03CR07D RW RDI1RO0BD RW FD
DCB13OU3E RW ACB03CR17E RW RDI1RO1BE RW CPU_SCR1FE# 3F ACB03CR27F RW BF CPU_SCR0FF#
3.Electrical Specifications
This chapter presents the DC and AC electrical specifications of the CY8C29x66 PSoC device. For the most up to date electrical specifications, confirm that you have the most recent data sheet by going to the web at https://www.doczj.com/doc/425309258.html,/psoc. Specifications are valid for -40o C ≤ T A≤ 85o C and T J≤ 100o C, except where noted.
Refer to Table3-17 for the electrical specifications on the internal main oscillator (IMO) using SLIMO mode.
Figure 3-1. Voltage versus CPU Frequency Figure 3-1b. IMO Frequency Trim Options
The following table lists the units of measure that are used in this chapter.
Table 3-1: Units of Measure
Symbol Unit of Measure Symbol Unit of Measure
o C degree CelsiusμW microwatts
dB decibels mA milli-ampere
fF femto farad ms milli-second
Hz hertz mV milli-volts
KB1024 bytes nA nanoampere
Kbit1024 bits ns nanosecond
kHz kilohertz nV nanovolts
k?kilohm?ohm
MHz megahertz pA picoampere
M?megaohm pF picofarad
μA microampere pp peak-to-peak
μF microfarad ppm parts per million
μH microhenry ps picosecond
μs microsecond sps samples per second
μV microvoltsσsigma: one standard deviation
μVrms microvolts root-mean-square V volts
3.1
Absolute Maximum Ratings
3.2
Operating Temperature
Table 3-2: Absolute Maximum Ratings
Symbol Description
Min Typ
Max Units
Notes
T STG
Storage Temperature
-55
25+100
o C
Higher storage temperatures will reduce data retention time. Recommended storage temper-ature is +25o C ± 25o C. Extended duration stor-age temperatures above 65o C will degrade reliability.
T A Ambient Temperature with Power Applied -40–+85o C
Vdd Supply Voltage on Vdd Relative to Vss -0.5–+6.0
V
V IO DC Input Voltage
Vss - 0.5–Vdd + 0.5V V IOZ DC Voltage Applied to Tri-state Vss - 0.5–Vdd + 0.5V I MIO Maximum Current into any Port Pin
-25–+50mA I MAIO Maximum Current into any Port Pin Configured as Analog Driver
-50–+50mA ESD Electro Static Discharge Voltage 2000––V Human Body Model ESD.
LU
Latch-up Current
–
–
200
mA
Table 3-3: Operating Temperature
Symbol Description
Min Typ
Max Units
Notes
T A Ambient Temperature -40–+85o C
T J
Junction Temperature
-40
–+100
o
C
The temperature rise from ambient to junction is package specific. See “Thermal Impedances” on page 42. The user must limit the power con-sumption to comply with this requirement.