现代计算机组成原理实验
学号 1115108052
姓名詹炳鑫
班级电子2班
华侨大学电子工程系
现代计算机组成原理实验一.程序
Cfq
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY cfq IS
GENERIC (n:INTEGER:=5;
m:INTEGER:=9);
PORT(
clock,resetn,start: IN STD_LOGIC;
x,y : IN STD_LOGIC_VECTOR(n DOWNTO 1);
p : OUT STD_LOGIC_VECTOR(m DOWNTO 1);
done : OUT STD_LOGIC);
END cfq;
ARCHITECTURE ONE OF cfq IS
SIGNAL ry : STD_LOGIC_VECTOR(n DOWNTO 1);
SIGNAL pp : STD_LOGIC_VECTOR(m+1 DOWNTO 0);
SIGNAL state: INTEGER RANGE 0 TO 5;
BEGIN
mulyiply: PROCESS(resetn, clock)
VARIABLE temp: STD_LOGIC_VECTOR(n+1 DOWNTO 1);
BEGIN
IF resetn='0' THEN
ry <= (OTHERS=>'0');
pp <= (OTHERS=>'0');
state <= 0;
done <= '0';
ELSIF clock'EVENT AND clock ='1' THEN
CASE state IS
WHEN 0 =>
ry <= y;
pp <= "00000"&x&'0';
IF start = '1' THEN
state <= 1;
END IF;
WHEN 5 =>
IF pp(1 DOWNTO 0)="01" THEN
temp:=(pp(m+1)&PP(m+1 DOWNTO n+1))+(ry(n)&ry);
ELSIF PP(1 DOWNTO 0)="10" THEN
temp:=(pp(m+1)&PP(m+1 DOWNTO n+1))+NOT(ry(n)&ry)+1;
ELSE
temp:=(pp(m+1)&PP(m+1 DOWNTO n+1));
END IF;
p<=temp(n DOWNTO 1)&PP(n DOWNTO 2);
done <= '1';
state <= 0;
WHEN OTHERS =>
IF pp(1 DOWNTO 0)="01" THEN
temp:=(pp(m+1)&PP(m+1 DOWNTO n+1))+(ry(n)&ry);
ELSIF PP(1 DOWNTO 0)="10" THEN
temp:=(pp(m+1)&PP(m+1 DOWNTO n+1))+NOT(ry(n)&ry)+1;
ELSE
temp:=(pp(m+1)&PP(m+1 DOWNTO n+1));
END IF;
pp<=temp&PP(n DOWNTO 1);
state <= state+1;
END CASE;
END IF;
END PROCESS;
END ONE;
Cfq-tb
-- Copyright (C) 1991-2011 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- *************************************************************************** -- This file contains a Vhdl test bench template that is freely editable to
-- suit user's needs .Comments are provided in each section to help the user
-- fill out necessary details.
-- *************************************************************************** -- Generated on "03/10/2011 16:48:18"
-- Vhdl Test Bench template for design : cfq
--
-- Simulation tool : ModelSim-Altera (VHDL)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY cfq_tb IS
END cfq_tb;
ARCHITECTURE cfq_arch OF cfq_tb IS
COMPONENT cfq
PORT(
clock,resetn,start: IN STD_LOGIC;
x,y : IN STD_LOGIC_VECTOR(5 DOWNTO 1);
p : OUT STD_LOGIC_VECTOR(9 DOWNTO 1);
done : OUT STD_LOGIC);
END COMPONENT;
SIGNAL clock : STD_LOGIC:='0';
SIGNAL done : STD_LOGIC:='0';
SIGNAL p : STD_LOGIC_VECTOR(9 DOWNTO 1):="000000000";
SIGNAL resetn : STD_LOGIC:='0';
SIGNAL start : STD_LOGIC:='0';
SIGNAL x : STD_LOGIC_VECTOR(5 DOWNTO 1):="00001";
SIGNAL y : STD_LOGIC_VECTOR(5 DOWNTO 1):="00011";
CONSTANT CLK_P : TIME := 10 ns;
BEGIN
i1 : cfq
PORT MAP (
-- list connections between master ports and signals
clock => clock,
done => done,
p => p,
resetn => resetn,
start => start,
x => x,
y => y
);
PROCESS --产生时钟信号进程，没有敏感信号，永久自动启动进程
BEGIN
clock <= '0'; --CLK首先输出0,30ns后输出1 W AIT FOR CLK_P;
clock <= '1';
W AIT FOR CLK_P; --30ns后返回
END PROCESS;
resetn <= '0','1' AFTER 25 ns;
start <= '0','1' AFTER 45 ns, '0' AFTER 155 ns;
END cfq_arch;
二.仿真结果：
1*3
-1*3
-1*-3
1*-3
总