June 2011Doc ID 2411 Rev 111/31
M48T08
M48T08Y, M48T18
5 V , 64 Kbit (8 Kb x 8) TIMEKEEPER ? SRAM
Features
■Integrated ultra low power SRAM, real-time clock, power-fail control circuit, and battery ■BYTEWIDE ? RAM-like clock access ■BCD coded year, month, day, date, hours, minutes, and seconds
■Typical clock accuracy of ±1 minute a month, at 25 °C
■Automatic power-fail chip deselect and WRITE protection
■
WRITE protect
V PFD = power-fail deselect voltage):–M48T08: V CC = 4.75 to 5.5 V; 4.5 V ≤ V PFD ≤ 4.75 V
–M48T18/T08Y: V CC = 4.5 to 5.5 V; 4.2 V ≤ V PFD ≤ 4.5 V ■Software controlled clock calibration for high accuracy applications
■Self-contained battery and crystal in the CAPHAT ? DIP package
■Packaging includes a 28-lead SOIC and SNAPHAT ? top (to be ordered separately)■
SOIC package provides direct connection for a snaphat top which contains the battery and crystal
■Pin and function compatible with DS1643 and JEDEC standard 8 K x 8 SRAMs ■
RoHS compliant
–Lead-free second level interconnect
https://www.doczj.com/doc/41709549.html,
Contents M48T08, M48T08Y, M48T18
Contents
1Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2Operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1READ mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2WRITE mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.3Data retention mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.4Power-fail interrupt pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3Clock operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.1Reading the clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.2Setting the clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.3Stopping and starting the oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.4Calibrating the clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.5V CC noise and negative going transients . . . . . . . . . . . . . . . . . . . . . . . . . 18 4Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 8Environmental information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 9Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
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M48T08, M48T08Y, M48T18List of tables List of tables
Table 1.Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Table 2.Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 3.READ mode AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 4.WRITE mode AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 5.Register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 6.Absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 7.Operating and AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 8.Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 9.DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 10.Power down/up AC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 11.Power down/up trip points DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 12.PCDIP28 – 28-pin plastic DIP, battery CAPHAT?, package mech. data . . . . . . . . . . . . . 23 Table 13.SOH28 – 28-lead plastic SO, 4-socket battery SNAPHAT?, package mech. data. . . . . . . 24 Table 14.SH – 4-pin SNAPHAT? housing for 48 mAh battery & crystal, package mech. data. . . . . 25 Table 15.SH – 4-pin SNAPHAT? housing for 120 mAh battery & crystal, package mech. data. . . . 26 Table 16.Ordering information scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 17.SNAPHAT? battery table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 18.Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Doc ID 2411 Rev 113/31
List of figures M48T08, M48T08Y, M48T18 List of figures
Figure 1.Logic diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 2.DIP connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 3.SOIC connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 4.Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 5.READ mode AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 6.WRITE enable controlled, WRITE AC waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 7.Chip enable controlled, WRITE AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 8.Crystal accuracy across temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 9.Clock calibration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 10.Supply voltage protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 11.AC testing load circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 12.Power down/up mode AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 13.PCDIP28 – 28-pin plastic DIP, battery CAPHAT?, package outline. . . . . . . . . . . . . . . . . 23 Figure 14.SOH28 – 28-lead plastic small outline, 4-socket battery SNAPHAT?, package outline. . . 24 Figure 15.SH – 4-pin SNAPHAT? housing for 48 mAh battery & crystal, package outline. . . . . . . . . 25 Figure 16.SH – 4-pin SNAPHAT? housing for 120 mAh battery & crystal, package outline. . . . . . . . 26 Figure 17.Recycling symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4/31Doc ID 2411 Rev 11
M48T08, M48T08Y, M48T18Description 1 Description
The M48T08/18/08Y TIMEKEEPER? RAM is an 8 K x 8 non-volatile static RAM and real-
time clock which is pin and function compatible with the DS1643. The monolithic chip is
available in two special packages to provide a highly integrated battery-backed memory and
real-time clock solution.
The M48T08/18/08Y is a non-volatile pin and function equivalent to any JEDEC standard
8 K x 8 SRAM. It also easily fits into many ROM, EPROM, and EEPROM sockets, providing
the non-volatility of PROMs without any requirement for special WRITE timing or limitations
on the number of WRITEs that can be performed.
The 28-pin, 600 mil DIP CAPHAT? houses the M48T08/18/08Y silicon with a quartz crystal
and a long-life lithium button cell in a single package.
The 28-pin, 330 mil SOIC provides sockets with gold-plated contacts at both ends for direct
connection to a separate SNAPHAT? housing containing the battery and crystal. The unique
design allows the SNAPHAT? battery package to be mounted on top of the SOIC package
after the completion of the surface mount process. Insertion of the SNAPHAT? housing after
reflow prevents potential battery and crystal damage due to the high temperatures required
for device surface-mounting. The SNAPHAT? housing is keyed to prevent reverse insertion.
The SOIC and battery/crystal packages are shipped separately in plastic anti-static tubes or
in tape & reel form. For the 28-lead SOIC, the battery/crystal package (e.g., SNAPHAT?)
part number is “M4T28-BR12SH” or “M4T32-BR12SH”.
Doc ID 2411 Rev 115/31
Description M48T08, M48T08Y, M48T18
Table 1.Signal names
A0-A12Address inputs
DQ0-DQ7Data inputs / outputs
INT Power fail interrupt (open drain)
E1Chip enable 1
E2Chip enable 2
G Output enable
W WRITE enable
V CC Supply voltage
V SS Ground
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M48T08, M48T08Y, M48T18Description
Doc ID 2411 Rev 117/31
Operation modes M48T08, M48T08Y, M48T18
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2 Operation modes
As Figure 4 on page 7 shows, the static memory array and the quartz-controlled clock
oscillator of the M48T08/18/08Y are integrated on one silicon chip. The two circuits are interconnected at the upper eight memory locations to provide user accessible BYTEWIDE? clock information in the bytes with addresses 1FF8h-1FFFh.
The clock locations contain the year, month, date, day, hour, minute, and second in 24-hour BCD format. Corrections for 28, 29 (leap year - valid until 2100), 30, and 31 day months are made automatically. Byte 1FF8h is the clock control register. This byte controls user access to the clock information and also stores the clock calibration setting.
The eight clock bytes are not the actual clock counters themselves; they are memory locations consisting of BiPORT? READ/WRITE memory cells. The M48T08/18/08Y
includes a clock control circuit which updates the clock bytes with current information once per second. The information can be accessed by the user in the same manner as any other location in the static memory array.
The M48T08/18/08Y also has its own power-fail detect circuit. The control circuitry
constantly monitors the single 5 V supply for an out-of-tolerance condition. When V CC is out of tolerance, the circuit write protects the SRAM, providing a high degree of data security in the midst of unpredictable system operation brought on by low V CC . As V CC falls below the battery backup switchover voltage (V SO ), the control circuitry connects the battery which maintains data and clock operation until valid power returns.Table 2.
Operating modes
Note:
X = V IH or V IL ; V SO = Battery backup switchover voltage.
Mode V CC
E1E2G W DQ0-DQ7Power Deselect 4.75 to 5.5 V
or
4.5 to
5.5 V
V IH X X X High Z Standby Deselect X V IL X X High Z Standby WRITE V IL V IH X V IL D IN Active READ V IL V IH V IL V IH D OUT Active READ V IL V IH V IH V IH High Z Active Deselect V SO to V PFD (min)(1)1.See Table 11 on page 22 for details.
X X X X H igh Z CMOS standby Deselect
≤ V SO (1)X
X
X
X
High Z
Battery backup mode
M48T08, M48T08Y, M48T18Operation modes
Doc ID 2411 Rev 119/31
2.1 READ mode
enable 1) is low, and E2 (chip enable 2) is high. The device architecture allows ripple-through access of data from eight of 65,536 locations in the static storage array. Thus, the unique address specified by the 13 address inputs defines which one of the 8,192 bytes of data is to be accessed. Valid data will be available at the data I/O pins within address access time (t AVQV be available after the latter of the chip enable access times (t E1LQV or t E2HQV ) or output enable access time (t GLQV ).
outputs are activated before t AVQV , the data lines will be driven to an indeterminate state until t AVQV will remain valid for output data hold time (t AXQX ) but will go indeterminate until the next address access.
Note:WRITE enable (W) = high.
Operation modes M48T08, M48T08Y, M48T18
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Table 3.
READ mode AC characteristics
Note:
Valid for ambient operating temperature: T A = 0 to 70 °C; V CC = 4.75 to 5.5 V or 4.5 to 5.5 V (except where noted).
2.2 WRITE mode
The M48T08/18/08Y is in the WRITE mode whenever W, E1, and E2 are active. The start of
a WRITE is referenced from the latter occurring falling edge of W or E1, or the rising edge of E2. A WRITE is terminated by the earlier rising edge of W or E1, or the falling edge of E2. The addresses must be held valid throughout the cycle. E1 or W must return high or E2 low for a minimum of t E1HAX or t E2LAX from chip enable or t WHAX from WRITE enable prior to the initiation of another READ or WRITE cycle. Data-in must be valid t DVWH prior to the end of WRITE and remain valid for t WHDX afterward. G should be kept high during WRITE cycles to avoid bus contention; however, if the output bus has been activated by a low on E1 and G and a high on E2, a low on W will disable the outputs t WLQZ after W falls.
Symbol
Parameter (1)
M48T08/M48T18/T08Y
Unit
–100/–10 (T08Y)–150/–15 (T08Y)Min
Max
Min Max
t AVAV READ cycle time
100
150
ns t AVQV Address valid to output valid 100150ns t E1LQV Chip enable 1 low to output valid 100150ns t E2HQV Chip enable 2 high to output valid 100150ns t GLQV Output enable low to output valid 50
75ns t E1LQX Chip enable 1 low to output transition 1010ns t E2HQX Chip enable 2 high to output transition 1010ns t GLQX Output enable low to output transition 5
5
ns t E1HQZ Chip enable 1 high to output Hi-Z 5075ns t E2LQZ Chip enable 2 low to output Hi-Z 5075ns t GHQZ Output enable high to output Hi-Z 40
60
ns t AXQX
Address transition to output transition
55
ns
分销商库存信息:
STM
M48T08Y-10MH1E M48T08Y-10MH1F M48T18-150PC1 M48T08-150PC1M48T18-100PC1M48T08-100PC1