M16C/6N Group (M16C/6NK, M16C/6NM)
Renesas MCU
Under development
This document is under development and its contents are subject to change
Specifications written in this manual are believed to be accurate, but are not guaranteed to be entirely free of error. Specifications in this manual may be changed for functional or performance improvements. Please make sure your manual is the latest edition.
REJ03B0058-0210
Rev.2.10Aug 25, 2006
1. Overview
The M16C/6N Group (M16C/6NK, M16C/6NM) of MCUs are built using the high-performance silicon gate CMOS process using the M16C/60 Series CPU core and are packaged in 100-pin and 128-pin plastic molded LQFP. These MCUs operate using sophisticated instructions featuring a high level of instruction efficiency. With 1 Mbyte of address space, they are capable of executing instructions at high speed. Being equipped with two CAN (Controller Area Network) modules in the M16C/6N Group (M16C/6NK, M16C/6NM),the MCU is suited to drive automotive and industrial control systems. The CAN modules comply with the 2.0B specification. In addition, this MCU contains a multiplier and DMAC which combined with fast instruction processing capability, makes it suitable for control of various OA, communication equipment which requires high-speed arithmetic/logic operations.
1.1 Applications
? Car audio and industrial control systems, other (Normal-ver. product)
? Automotive, industrial control systems and other automobile, other (T/V-ver. product)
元器件交易网https://www.doczj.com/doc/3412931322.html,
Item
Specification
Normal-ver.T/V-ver.
CPU Number of fundamental 91 instructions
instructions
Minimum instruction 41.7 ns (f(BCLK) = 24 MHz,50.0 ns (f(BCLK) = 20 MHz,execution time 1/1 prescaler, without software wait)1/1 prescaler, without software wait)Operating mode Single-chip, memory expansion, Single-chip mode
and microprocessor modes
Address space 1 Mbyte Memory capacity Refer to Table 1.3 Product Information
Peripheral Ports Input/Output: 87 pins, Input: 1 pin Function Multifunction timers Timer A: 16 bits ? 5 channels
Timer B: 16 bits ? 6 channels Three-phase motor control circuit
Serial interfaces 3 channels
Clock synchronous, UART, I 2C-bus (1), IEBus (2)2 channels
Clock synchronous
A/D converter 10-bit A/D converter: 1 circuit, 26 channels D/A converter 8 bits ? 2 channels DMAC 2 channels CRC calculation circuit CRC-CCITT CAN module 2 channels with 2.0B specification Watchdog timer 15 bits ? 1 channel (with prescaler)Interrupts Internal: 32 sources, External: 9 sources
Software: 4 sources, Priority levels: 7 levels
Clock generation circuits 4 circuits
? Main clock oscillation circuit (*)? Sub clock oscillation circuit (*)? On-chip oscillator
? PLL frequency synthesizer
(*) Equipped with on-chip feedback resistor
Oscillation-stopped detector Main clock oscillation stop and re-oscillation detection function
Electrical Supply voltage VCC = 3.0 to 5.5 V (f(BCLK) = 24 MHz,VCC = 4.2 to 5.5 V (f(BCLK) = 20 MHz,Characteristics 1/1 prescaler, without software wait)1/1 prescaler, without software wait)
Consumption Mask ROM 21 mA (f(BCLK) = 24 MHz,-current PLL operation, no division)
Flash memory 23 mA (f(BCLK) = 24 MHz,21 mA (f(BCLK) = 20 MHz,
PLL operation, no division)PLL operation, no division)
Mask ROM 3 μA (f(BCLK) = 32 kHz, Wait mode, Oscillation capacity Low)Flash memory 0.8 μA (Stop mode, Topr = 25°C)
Flash Memory Programming and erasure voltage 3.0 ± 0.3 V or 5.0 ± 0.5 V 5.0 ± 0.5 V Version Programming and erasure endurance 100 times I/O I/O withstand voltage 5.0 V Characteristics Output current 5 mA Operating Ambient Temperature -40 to 85°C T version: -40 to 85°C
V version: -40 to 125°C (option)
Device Configuration CMOS high-performance silicon gate Package 100-pin molded-plastic LQFP 1.2 Performance Overview
Tables 1.1 and 1.2 list the Functions and Specifications for M16C/6N Group (M16C/6NK, M16C/6NM).Table 1.1 Functions and Specifications for M16C/6N Group (100-pin Version: M16C/6NK)
NOTES:
1. I 2C-bus is a trademark of Koninklijke Philips Electronics N.V.
2. IEBus is a trademark of NEC Electronics Corporation.
Item
Specification
Normal-ver.T/V-ver.
CPU Number of fundamental91 instructions
instructions
Minimum instruction41.7 ns (f(BCLK) = 24 MHz,50.0 ns (f(BCLK) = 20 MHz,
execution time1/1 prescaler, without software wait)1/1 prescaler, without software wait)
Operating mode Single-chip, memory expansion, Single-chip mode
and microprocessor modes
Address space 1 Mbyte
Memory capacity Refer to Table 1.3 Product Information
Peripheral Ports Input/Output: 113 pins, Input: 1 pin
Function Multifunction timers Timer A: 16 bits ? 5 channels
Timer B: 16 bits ? 6 channels
Three-phase motor control circuit
Serial interfaces 3 channels
Clock synchronous, UART, I2C-bus (1), IEBus (2)
4 channels
Clock synchronous
A/D converter10-bit A/D converter: 1 circuit, 26 channels
D/A converter8 bits ? 2 channels
DMAC 2 channels
CRC calculation circuit CRC-CCITT
CAN module 2 channels with 2.0B specification
Watchdog timer15 bits ? 1 channel (with prescaler)
Interrupts Internal: 34 sources, External: 12 sources
Software: 4 sources, Priority levels: 7 levels
Clock generation circuits 4 circuits
? Main clock oscillation circuit (*)
? Sub clock oscillation circuit (*)
? On-chip oscillator
? PLL frequency synthesizer
(*) Equipped with on-chip feedback resistor
Oscillation-stopped detector Main clock oscillation stop and re-oscillation detection function Electrical Supply voltage VCC = 3.0 to 5.5 V (f(BCLK) = 24 MHz,VCC = 4.2 to 5.5 V (f(BCLK) = 20 MHz, Characteristics1/1 prescaler, without software wait)1/1 prescaler, without software wait) Consumption Mask ROM21 mA (f(BCLK) = 24 MHz,-
current PLL operation, no division)
Flash memory23 mA (f(BCLK) = 24 MHz,21 mA (f(BCLK) = 20 MHz,
PLL operation, no division)PLL operation, no division)
Mask ROM 3 μA (f(BCLK) = 32 kHz, Wait mode, Oscillation capacity Low)
Flash memory0.8 μA (Stop mode, Topr = 25°C)
Flash Memory Programming and erasure voltage 3.0 ± 0.3 V or 5.0 ± 0.5 V 5.0 ± 0.5 V
Version Programming and erasure endurance100 times
I/O I/O withstand voltage 5.0 V
Characteristics Output current 5 mA
Operating Ambient Temperature-40 to 85°C T version: -40 to 85°C
V version: -40 to 125°C (option) Device Configuration CMOS high-performance silicon gate
Package128-pin molded-plastic LQFP
Table 1.2 Functions and Specifications for M16C/6N Group (128-pin Version: M16C/6NM)
NOTES:
1. I2C-bus is a trademark of Koninklijke Philips Electronics N.V.
2. IEBus is a trademark of NEC Electronics Corporation.
option: All options are on request basis.
1.4 Product Information
Table 1.3 lists the Product Information and Figure 1.2 shows the Type Number, Memory Size, and Packages.
Table 1.3 Product Information As of Aug. 2006 Type No.ROM Capacity RAM Capacity Package Type (2)Remarks
M306NKFHGP384 K + 4 Kbytes31 Kbytes PLQP0100KB-A Flash Normal-ver. M306NMFHGP PLQP0128KB-A memory
M306NKFJGP512 K + 4 Kbytes31 Kbytes PLQP0100KB-A version (1)
M306NMFJGP PLQP0128KB-A
M306NKFHTGP(D)384 K + 4 Kbytes31 Kbytes PLQP0100KB-A T-ver.
M306NMFHTGP(D)PLQP0128KB-A
M306NKFJTGP512 K + 4 Kbytes31 Kbytes PLQP0100KB-A
M306NMFJTGP PLQP0128KB-A
M306NKFHVGP(D)384 K + 4 Kbytes31 Kbytes PLQP0100KB-A V-ver.
M306NMFHVGP(D)PLQP0128KB-A
M306NKFJVGP(D)512 K + 4 Kbytes31 Kbytes PLQP0100KB-A
M306NMFJVGP(D)PLQP0128KB-A
M306NKME-XXXGP192 Kbytes16 Kbytes PLQP0100KB-A Mask Normal-ver. M306NMME-XXXGP PLQP0128KB-A ROM
M306NKMG-XXXGP256 Kbytes20 Kbytes PLQP0100KB-A version
M306NMMG-XXXGP PLQP0128KB-A
(D): Under development
NOTES:
1. Data flash memory provides an additional 4 Kbytes of ROM capacity (block A).
2. The correspondence between new and old package types is as follows.
PLQP0100KB-A: 100P6Q-A
PLQP0128KB-A: 128P6Q-A
Type No. M30 6N K M G T - XXX GP
Package type:
GP: Package PLQP0100KB-A (100P6Q-A)
PLQP0128KB-A (128P6Q-A)
ROM No.
Omitted on flash memory version
Characteristics
(no): Normal-ver.
T: T-ver. (Automotive 85°C version)
V: V-ver.(Automotive 125°C version)
ROM capacity:
E: 192 Kbytes
G: 256 Kbytes
H: 384 Kbytes
J: 512 Kbytes
Memory type:
M: Mask ROM version
F: Flash memory version
Shows the number of CAN module, pin count, etc.
6N Group
M16C Family
Pin No.Control
Port
Interrupt
Timer Pin UART Pin
Analog CAN Module Bus Control Pin Pin Pin Pin Pin (1)
1P9_4TB4IN DA1
2P9_3TB3IN DA0
3P9_2TB2IN SOUT3
4P9_1TB1IN SIN3
5P9_0TB0IN CLK3
6BYTE
7CNVSS
8XCIN P8_7
9XCOUT P8_6
10_____________
RESET
11XOUT
12VSS
13XIN
14VCC1
15P8_5________
NMI
16P8_4_________
INT2ZP
17P8_3_________
INT1
18P8_2_________
INT0
19P8_1___
TA4IN/U
20P8_0TA4OUT/U(SIN4)
21P7_7TA3IN CRX1
22P7_6TA3OUT CTX1
23P7_5____
TA2IN/W(SOUT4)
24P7_4TA2OUT/W(CLK4)
25P7_3___
TA1IN/V____________________
CTS2/RTS2
26P7_2TA1OUT/V CLK2
27P7_1TA0IN/TB5IN RXD2/SCL2
28P7_0TA0OUT TXD2/SDA2
29P6_7TXD1/SDA1
30P6_6RXD1/SCL1
31P6_5CLK1
32P6_4___________________________
CTS1/RTS1/CTS0/CLKS1
33P6_3TXD0/SDA0
34P6_2RXD0/SCL0
35P6_1CLK0
36P6_0____________________
CTS0/RTS0
37P5_7_________
RDY/CLKOUT 38P5_6ALE
39P5_5___________
HOLD 40P5_4___________
HLDA 41P5_3BCLK
42P5_2______
RD 43P5_1__________________
WRH/BHE 44P5_0_______________
WRL/WR 45P4_7_______
CS3 46P4_6_______
CS2 47P4_5_______
CS1 48P4_4_______
CS0 49P4_3A19
50P4_2A18 NOTE:
Pin No.Control
Port
Interrupt
Timer Pin UART Pin
Analog CAN Module Bus Control Pin Pin Pin Pin Pin (1)
51P4_1A17 52P4_0A16 53P3_7A15 54P3_6A14 55P3_5A13 56P3_4A12 57P3_3A11 58P3_2A10 59P3_1A9
60VCC2
61P3_0A8(/-/D7) 62VSS
63P2_7AN2_7A7(/D7/D6) 64P2_6AN2_6A6(/D6/D5) 65P2_5AN2_5A5(/D5/D4) 66P2_4AN2_4A4(/D4/D3) 67P2_3AN2_3A3(/D3/D2) 68P2_2AN2_2A2(/D2/D1) 69P2_1AN2_1A1(/D1/D0) 70P2_0AN2_0A0(/D0/-) 71P1_7_________
INT5D15 72P1_6_________
INT4D14 73P1_5_________
INT3D13 74P1_4D12 75P1_3D11 76P1_2D10 77P1_1D9
78P1_0D8
79P0_7AN0_7D7
80P0_6AN0_6D6
81P0_5AN0_5D5
82P0_4AN0_4D4
83P0_3AN0_3D3
84P0_2AN0_2D2
85P0_1AN0_1D1
86P0_0AN0_0D0
87P10_7______
KI3AN7
88P10_6______
KI2AN6
89P10_5______
KI1AN5
90P10_4______
KI0AN4
91P10_3AN3
92P10_2AN2
93P10_1AN1
94AVSS
95P10_0AN0
96VREF
97AVCC
98P9_7SIN4______________
ADTRG 99P9_6SOUT4ANEX1CTX0
100P9_5CLK4ANEX0CRX0
NOTE:
Pin No.Control
Port
Interrupt
Timer Pin UART Pin
Analog CAN Module Bus Control Pin Pin Pin Pin Pin (1)
1VREF
2AVCC
3P9_7SIN4______________
ADTRG
4P9_6SOUT4ANEX1CTX0
5P9_5CLK4ANEX0CRX0
6P9_4TB4IN DA1
7P9_3TB3IN DA0
8P9_2TB2IN SOUT3
9P9_1TB1IN SIN3
10P9_0TB0IN CLK3
11P14_1
12P14_0
13BYTE
14CNVSS
15XCIN P8_7
16XCOUT P8_6
17_____________
RESET
18XOUT
19VSS
20XIN
21VCC1
22P8_5________
NMI
23P8_4_________
INT2ZP
24P8_3_________
INT1
25P8_2_________
INT0
26P8_1___
TA4IN/U
27P8_0TA4OUT/U(SIN4)
28P7_7TA3IN CRX1
29P7_6TA3OUT CTX1
30P7_5____
TA2IN/W(SOUT4)
31P7_4TA2OUT/W(CLK4)
32P7_3___
TA1IN/V____________________
CTS2/RTS2
33P7_2TA1OUT/V CLK2
34P7_1TA0IN/TB5IN RXD2/SCL2
35P7_0TA0OUT TXD2/SDA2
36P6_7TXD1/SDA1
37VCC1
38P6_6RXD1/SCL1
39VSS
40P6_5CLK1
41P6_4___________________________
CTS1/RTS1/CTS0/CLKS1
42P6_3TXD0/SDA0
43P6_2RXD0/SCL0
44P6_1CLK0
45P6_0____________________
CTS0/RTS0
46P13_7_________
INT8
47P13_6_________
INT7
48P13_5_________
INT6
49P13_4
50P5_7_________
RDY/CLKOUT NOTE:
Pin No.Control
Port
Interrupt
Timer Pin UART Pin
Analog CAN Module Bus Control Pin Pin Pin Pin Pin (1)
51P5_6ALE 52P5_5___________
HOLD 53P5_4___________
HLDA 54P13_3
55P13_2
56P13_1
57P13_0
58P5_3BCLK 59P5_2______
RD 60P5_1__________________
WRH/BHE 61P5_0_______________
WRL/WR 62P12_7
63P12_6
64P12_5
65P4_7_______
CS3 66P4_6_______
CS2 67P4_5_______
CS1 68P4_4_______
CS0 69P4_3A19 70P4_2A18 71P4_1A17 72P4_0A16 73P3_7A15 74P3_6A14 75P3_5A13 76P3_4A12 77P3_3A11 78P3_2A10 79P3_1A9
80P12_4
81P12_3
82P12_2
83P12_1
84P12_0
85VCC2
86P3_0A8(/-/D7) 87VSS
88P2_7AN2_7A7(/D7/D6) 89P2_6AN2_6A6(/D6/D5) 90P2_5AN2_5A5(/D5/D4) 91P2_4AN2_4A4(/D4/D3) 92P2_3AN2_3A3(/D3/D2) 93P2_2AN2_2A2(/D2/D1) 94P2_1AN2_1A1(/D1/D0) 95P2_0AN2_0A0(/D0/-) 96P1_7_________
INT5D15 97P1_6_________
INT4D14 98P1_5_________
INT3D13 99P1_4D12 100P1_3D11 NOTE:
Pin No.Control
Port
Interrupt
Timer Pin UART Pin
Analog CAN Module Bus Control Pin Pin Pin Pin Pin (1)
101P1_2D10 102P1_1D9 103P1_0D8 104P0_7AN0_7D7 105P0_6AN0_6D6 106P0_5AN0_5D5 107P0_4AN0_4D4 108P0_3AN0_3D3 109P0_2AN0_2D2 110P0_1AN0_1D1 111P0_0AN0_0D0 112P11_7SIN6
113P11_6SOUT6
114P11_5CLK6
115P11_4
116P11_3
117P11_2SOUT5
118P11_1SIN5
119P11_0CLK5
120P10_7______
KI3AN7 121P10_6______
KI2AN6 122P10_5______
KI1AN5 123P10_4______
KI0AN4 124P10_3AN3
125P10_2AN2
126P10_1AN1
127AVSS
128P10_0AN0
NOTE:
1. Not available the bus control pins in T/V-ver..
1.6 Pin Functions
Tables 1.9 to 1.11 list the Pin Functions.
Table 1.9 Pin Functions (100-pin and 128-pin Versions) (1)
I I I I
I
I/O I/O O I/O
I/O
O O
O I O I
VCC1, VCC2,VSS
AVCC, AVSS
_____________
RESET CNVSS
BYTE D0 to D7D8 to D15A0 to A19
A0/D0 to A7/D7
A1/D0 to A8/D7
_______
_______
CS0 to CS3
_______________
WRL/WR _________________WRH/BHE ______RD
ALE __________HOLD
__________
HLDA ________RDY
Power supply input
Analog power supply input Reset input CNVSS (2)
External data bus width
select input (2)Bus control pins (3)
Apply 3.0 to 5.5 V to the VCC1 and VCC2 pins and 0 V to the VSS
pin. The VCC apply condition is that VCC2 = VCC1 (1).
Applies the power supply for the A/D converter. Connect the AVCC pin to VCC1. Connect the AVSS pin to VSS.
The MCU is in a reset state when applying “L ” to the this pin.
Switches processor mode. Connect this pin to VSS to when after a reset to start up in single-chip mode. Connect this pin to VCC1to start up in microprocessor mode.
Switches the data bus in external memory space. The data bus is 16-bit long when the this pin is held “L ” and 8-bit long when the this pin is held “H ”. Set it to either one. Connect this pin to VSS when single-chip mode.
Inputs and outputs data (D0 to D7) when these pins are set as the separate bus.
Inputs and outputs data (D8 to D15) when external 16-bit data bus is set as the separate bus.Output address bits (A0 to A19).
Input and output data (D0 to D7) and output address bits (A0 to A7) by time-sharing when external 8-bit data bus are set as the multiplexed bus.
Input and output data (D0 to D7) and output address bits (A1 to A8) by time-sharing when external 16-bit data bus are set as the multiplexed bus.____________________________
Output CS0 to CS3 signals. CS0 to CS3 are chip-select signals to specify an external space._____________________________________________________
Output WRL, WRH, (WR, BHE), RD signals. WRL and WRH or ______________
BHE, and WR can be switched by program.______________________
? WRL, WRH, and RD are selected ________
The WRL signal becomes “L ” by writing data to an even address in an external memory space._________
The WRH signal becomes “L ” by writing data to an odd address in an external memory space._____
The RD pin signal becomes “L ” by reading data in an external memory space.___________________
? WR, BHE, and RD are selected ______
The WR signal becomes “L ” by writing data in an external memory space.
_____
The RD signal becomes “L ” by reading data in an external memory space.________
The BHE signal becomes “L ” by accessing an odd address.___________________
Select WR, BHE, and RD for an external 8-bit data bus.ALE is a signal to latch the address.__________
While the HOLD pin is held “L ”, the MCU is placed in a hold state.__________
In a hold state, HLDA outputs a “L ” signal.
________
While applying a “L ” signal to the RDY pin, the MCU is placed in a wait state.
Signal Name
Pin Name I/O Type Description
I: Input O: Output I/O: Input/Output
NOTES:
1. In this manual, hereafter, VCC refers to VCC1 unless otherwise noted.
2. Connect to VSS in T/V-ver..
I O I O O O I I I I/O I I I O I O I/O I I O O O I/O I/O I I
I I/O
I O
I O
XIN XOUT XCIN XCOUT BCLK CLKOUT
NT0 to INT8 (2)________NMI
______
______
KI0 to KI3
TA0OUT to TA4OUT TA0IN to TA4IN ZP
TB0IN to TB5IN __________U, U, V, V, W, W ____________________CTS0 to CTS2____________________
RTS0 to RTS2CLK0 to CLK6 (2)RXD0 to RXD2SIN3 to SIN6 (2)TXD0 to TXD2SOUT3 to SOUT6 (2)CLKS1SDA0 to SDA2SCL0 to SCL2VREF
AN0 to AN7
AN0_0 to AN0_7AN2_0 to AN2_7_____________ADTRG ANEX0
ANEX1
DA0, DA1CRX0, CRX1
CTX0, CTX1Main clock
input
Main clock output Sub clock input
Sub clock output
BCLK output (3)Clock output INT interrupt input _______
NMI interrupt input
Key input
interrupt input Timer A
Timer B Three-phase motor control output Serial interface I 2C mode
Reference voltage input A/D converter
D/A converter CAN module I/O pins for the main clock oscillation circuit. Connect a ceramic
resonator or crystal oscillator between XIN and XOUT (1)
.
To use the external clock, input the clock from XIN and leave XOUT open.
I/O pins for a sub clock oscillation circuit. Connect a crystal oscillator between XCIN and XCOUT (1).
To use the external clock, input the clock from XCIN and leave XCOUT open.
Outputs the BCLK signal.
The clock of the same cycle as fC, f8, or f32 is output.______
Input pins for the INT interrupt._______
Input pin for the NMI interrupt.Input pins for the key input interrupt.
These are timer A0 to timer A4 I/O pins.These are timer A0 to timer A4 input pins.Input pin for the Z-phase.
These are timer B0 to timer B5 input pins.
These are Three-phase motor control output pins.
These are transmit control input pins.These are receive control output pins.These are transfer clock I/O pins.These are serial data input pins.These are serial data input pins.These are serial data output pins.These are serial data output pins.
This is output pin for transfer clock output from multiple pins function.
These are serial data I/O pins.
These are transfer clock I/O pins. (however, SCL2 for the N-channel open drain output.)
Applies the reference voltage for the A/D converter and D/A converter.
Analog input pins for the A/D converter.
This is an A/D trigger input pin.
This is the extended analog input pin for the A/D converter,and is the output in external op-amp connection mode.
This is the extended analog input pin for the A/D converter.These are the output pins for the D/A converter.These are the input pins for the CAN module.These are the output pins for the CAN module.Signal Name Pin Name I/O Type
Description
I: Input O: Output I/O: Input/Output
NOTES:
1. Ask the oscillator maker the oscillation characteristic.________________
2. INT6 to INT8, CLK5, CLK6, SIN5, SIN6, SOUT5, SOUT6 are only in the 128-pin version.
8-bit I/O ports in CMOS, having a direction register to select an input or output.
Each pin is set as an input port or output port. An input port can be set for a pull-up or for no pull-up in 4-bit unit by program.
(however P7_1 and P9_1 for the N-channel open drain output.)
_______
Input pin for the NMI interrupt.
Pin states can be read by the P8_5 bit in the P8 register.
I/O port
Input port
P0_0 to P0_7P1_0 to P1_7P2_0 to P2_7P3_0 to P3_7P4_0 to P4_7P5_0 to P5_7P6_0 to P6_7P7_0 to P7_7P8_0 to P8_4P8_6, P8_7P9_0 to P9_7P10_0 to P10_7P11_0 to P11_7 (1)P12_0 to P12_7 (1)P13_0 to P13_7 (1)P14_0, P14_1 (1)
P8_5
I/O
I
Signal Name
Pin Name I/O Type Description
I: Input O: Output I/O: Input/Output NOTE:
1. Ports P11 to P14 are only in the 128-pin version.
2.3 Frame Base Register (FB)
FB is configured with 16 bits, and is used for FB relative addressing.
2.4 Interrupt Table Register (INTB)
INTB is configured with 20 bits, indicating the start address of an interrupt vector table.
2.5 Program Counter (PC)
PC is configured with 20 bits, indicating the address of an instruction to be executed.
2.6 User Stack Pointer (USP), Interrupt Stack Pointer (ISP)
Stack pointer (SP) comes in two types: USP and ISP, each configured with 16 bits.
Your desired type of stack pointer (USP or ISP) can be selected by the U flag of FLG.
2.7 Static Base Register (SB)
SB is configured with 16 bits, and is used for SB relative addressing.
2.8 Flag Register (FLG)
FLG consists of 11 bits, indicating the CPU status.
2.8.1 Carry Flag (C Flag)
This flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit.
2.8.2 Debug Flag (D Flag)
This flag is used exclusively for debugging purpose. During normal use, set to 0.
2.8.3 Zero Flag (Z Flag)
This flag is set to 1 when an arithmetic operation resulted in 0; otherwise, it is 0.
2.8.4 Sign Flag (S Flag)
This flag is set to 1 when an arithmetic operation resulted in a negative value; otherwise, it is 0.
2.8.5 Register Bank Select Flag (B Flag)
Register bank 0 is selected when this flag is 0; register bank 1 is selected when this flag is 1.
2.8.6 Overflow Flag (O Flag)
This flag is set to 1 when the operation resulted in an overflow; otherwise, it is 0.
2.8.7 Interrupt Enable Flag (I Flag)
This flag enables a maskable interrupt.
Maskable interrupts are disabled when the I flag is 0, and are enabled when the I flag is 1. The I flag is set to 0 when the interrupt request is accepted.
2.8.8 Stack Pointer Select Flag (U Flag)
ISP is selected when the U flag is 0; USP is selected when the U flag is 1.
The U flag is set to 0 when a hardware interrupt request is accepted or an INT instruction for software interrupt Nos. 0 to 31 is executed.
2.8.9 Processor Interrupt Priority Level (IPL)
IPL is configured with three bits, for specification of up to eight processor interrupt priority levels from level
0 to level 7.
If a requested interrupt has priority greater than IPL, the interrupt request is enabled.
2.8.10 Reserved Area
4. Special Function Registers (SFRs)
An SFR (Special Function Register) is a control register for a peripheral function.
Tables 4.1 to 4.16 list the SFR Information.Table 4.1 SFR Information (1) (5)
0000h 0001h 0002h 0003h 0004h 0005h 0006h 0007h 0008h 0009h 000Ah 000Bh 000Ch 000Dh 000Eh 000Fh 0010h 0011h 0012h 0013h 0014h 0015h 0016h 0017h 0018h 0019h 001Ah 001Bh 001Ch 001Dh 001Eh 001Fh 0020h 0021h 0022h 0023h 0024h 0025h 0026h 0027h 0028h 0029h 002Ah 002Bh 002Ch 002Dh 002Eh 002Fh 0030h 0031h 0032h 0033h 0034h 0035h 0036h 0037h 0038h 0039h 003Ah 003Bh 003Ch 003Dh 003Eh 003Fh
Processor Mode Register 0 (1)
Processor Mode Register 1
System Clock Control Register 0System Clock Control Register 1Chip Select Control Register (4)
Address Match Interrupt Enable Register Protect Register
Oscillation Stop Detection Register (2)Watchdog Timer Start Register Watchdog Timer Control Register Address Match Interrupt Register 0
Address Match Interrupt Register 1Chip Select Expansion Control Register (4)PLL Control Register 0Processor Mode Register 2DMA0 Source Pointer
DMA0 Destination Pointer DMA0 Transfer Counter DMA0 Control Register DMA1 Source Pointer DMA1 Destination Pointer DMA1 Transfer Counter DMA1 Control Register PM0PM1CM0CM1CSR AIER PRCR CM2WDTS WDC RMAD0
RMAD1
CSE PLC0PM2 SAR0
DAR0
TCR0
DM0CON SAR1
DAR1
TCR1
DM1CON X: Undefined
NOTES:
1. Bits PM00 and PM01 in the PM0 register do not change at software reset, watchdog timer reset and oscillation stop detection reset.* Effective when memory expansion and microprocessor modes (= Normal-ver.).
2. Bits CM20, CM21, and CM27 in the CM2 register do not change at oscillation stop detection reset.
3. CNVSS pin = H is not available in T/V-ver.. Do not set a value.Address Register
Symbol
After Reset
00000000b (CNVSS pin is "L") 00000011b (CNVSS pin is "H") (3)
00001000b 01001000b 00100000b 00000001b XXXXXX00b XX000000b
0X000000b XXh 00XXXXXXb
00h 00h X0h
00h 00h X0h
00h 0001X010b XXX00000b
XXh XXh XXh XXh XXh XXh XXh XXh
00000X00b
XXh XXh XXh XXh XXh XXh XXh XXh
00000X00b
XXXXX000b XXXXX000b XXXXX000b XX00X000b XXXXX000b XXXXX000b XXXXX000b XX00X000b XX00X000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XX00X000b XX00X000b XXXXX000b XXXXX000b XX00X000b XXXXX000b XX00X000b XX00X000b XX00X000b
XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh
0040h 0041h 0042h 0043h 0044h 0045h 0046h 0047h 0048h 0049h 004Ah 004Bh 004Ch 004Dh 004Eh 004Fh 0050h 0051h 0052h 0053h 0054h 0055h 0056h 0057h 0058h 0059h 005Ah 005Bh 005Ch 005Dh 005Eh 005Fh 0060h 0061h 0062h 0063h 0064h 0065h 0066h 0067h 0068h 0069h 006Ah 006Bh 006Ch 006Dh 006Eh 006Fh 0070h 0071h 0072h 0073h 0074h 0075h 0076h 0077h 0078h 0079h 007Ah 007Bh 007Ch 007Dh 007Eh 007Fh
C01WKIC C0RECIC C0TRMIC INT3IC TB5IC S5IC TB4IC U1BCNIC TB3IC U0BCNIC C1RECIC S4IC INT5IC C1TRMIC S3IC INT4IC U2BCNIC DM0IC DM1IC C01ERRIC ADIC KUPIC S2TIC S2RIC S0TIC S0RIC S1TIC S1RIC TA0IC TA1IC TA2IC INT7IC TA3IC INT6IC TA4IC TB0IC S6IC TB1IC INT8IC TB2IC INT0IC INT1IC INT2IC
Address
Register
Symbol After Reset CAN0/1 Wake-up Interrupt Control Register
CAN0 Successful Reception Interrupt Control Register CAN0 Successful Transmission Interrupt Control Register INT3 Interrupt Control Register Timer B5 Interrupt Control Register SI/O5 Interrupt Control Register (1)Timer B4 Interrupt Control Register
UART1 Bus Collision Detection Interrupt Control Register Timer B3 Interrupt Control Register
UART0 Bus Collision Detection Interrupt Control Register CAN1 Successful Reception Interrupt Control Register SI/O4 Interrupt Control Register INT5 Interrupt Control Register
CAN1 Successful Transmission Interrupt Control Register SI/O3 Interrupt Control Register INT4 Interrupt Control Register
UART2 Bus Collision Detection Interrupt Control Register DMA0 Interrupt Control Register DMA1 Interrupt Control Register
CAN0/1 Error Interrupt Control Register A/D Conversion Interrupt Control Register Key Input Interrupt Control Register
UART2 Transmit Interrupt Control Register UART2 Receive Interrupt Control Register UART0 Transmit Interrupt Control Register UART0 Receive Interrupt Control Register UART1 Transmit Interrupt Control Register UART1 Receive Interrupt Control Register Timer A0 Interrupt Control Register Timer A1 Interrupt Control Register Timer A2 Interrupt Control Register INT7 Interrupt Control Register (1)Timer A3 Interrupt Control Register INT6 Interrupt Control Register (1)Timer A4 Interrupt Control Register Timer B0 Interrupt Control Register SI/O6 Interrupt Control Register (1)Timer B1 Interrupt Control Register INT8 Interrupt Control Register (1)Timer B2 Interrupt Control Register INT0 Interrupt Control Register INT1 Interrupt Control Register INT2 Interrupt Control Register
CAN0 Message Box 0: Identifier / DLC
CAN0 Message Box 0: Data Field
CAN0 Message Box 0: Time Stamp
CAN0 Message Box 1: Identifier / DLC
CAN0 Message Box 1: Data Field
CAN0 Message Box 1: Time Stamp
X: Undefined
NOTES:
1. These registers exist only in the 128-pin version.
2. Blank spaces are reserved. No access is allowed.