chapter9.fm Page 406 Friday, April 5, 2002 4:15 PM
CHAPTER
9
COPING WITH INTERCONNECT
Driving large capacitors n Dealing with transmision line effects in wires n Signal integrity in the presence of interconnect parasitics n Noise in supply networks n
9.1 9.2 Introduction Capacitive Parasitics 9.2.1 9.2.2 Capacitance and Reliability—Cross Talk Capacitance and Performance in CMOS 9.5 9.3 Resistive Parasitics 9.3.1 9.3.2 9.3.3 Resistance and Reliability—Ohmic Voltage Drop Electromigration Resistance and Performance—RC Delay 9.6 9.7 Perspective: Networks-on-a-Chip Chapter Summary 9.5.1 9.5.2 9.4 Inductive Parasitics 9.4.1 9.4.2 Inductance and Reliability— Voltage Drop Inductance and Performance—Transmission Line Effects
Advanced Interconnect Techniques Reduced-Swing Circuits Current-Mode Transmission Techniques
406
chapter9.fm Page 407 Friday, April 5, 2002 4:15 PM
Section 9.1
Introduction
407
9.1
Introduction
In previous Chapters, we have pointed out the growing impact of interconnect parasitics on all design metrics of digital integrated circuits. As mentioned, interconnect introduces three types of parasitic effects—capacitive, resistive, and inductive—, all of which influence the signal integrity and degrade the performance of the circuit. While so far we have concentrated on the modeling aspects of the wire, we now analyze how interconnect affects the circuit operation, and we present a collection of design techniques to cope with these effects. The discussion addresses each parasitic in sequence.
9.2
Capacitive Parasitics
9.2.1 Capacitance and Reliability—Cross Talk
An unwanted coupling from a neighboring signal wire to a network node introduces an interference that is generally called cross talk. The resulting disturbance acts as a noise source and can lead to hard-to-trace intermittent errors, since the injected noise depends upon the transient value of the other signals routed in the neighborhood. In integrated circuits, this intersignal coupling can be both capacitive and inductive, as shown earlier in Figure 1.10. Capacitive cross talk is the dominant effect at current switching speeds, although inductive coupling forms a major concern in the design of the input-output circuitry of mixed-signal circuits. The potential impact of capacitive crosstalk is influenced by the impedance of the line under examination. If the line is floating, the disturbance caused by the coupling persists and may be worsened by subsequent switching on adjacent wires. If the wire is driven, on the other hand, the signal returns to its original level. Floating Lines Let us consider the circuit configuration of Figure 9.1. Line X is coupled to wire Y by a parasitic capacitance CXY. Line Y sees a total capacitance to ground equal to CY. Assume that the voltage at node X experiences a step change equal to VX . This step appears on node Y attenuated by the capacitive voltage divider. CXY V Y = ---------------------- V X CY + CX Y
X VX CXY Y CY
Figure 9.1 Capacitive coupling to a floating line.
(9.1)
Circuits that are particularly susceptive to capacitive cross talk are networks with lowswing precharged nodes, located in adjacency to full-swing wires (with VX = VDD ). Examples are dynamic memories, low-swing on-chip busses, and some dynamic logic families.
chapter9.fm Page 408 Friday, April 5, 2002 4:15 PM
408
COPING WITH INTERCONNECT
Chapter 9
Example 9.1 Interwire Capacitance and Cross Talk Consider the dynamic logic circuit of Figure 9.2. The storage capacitance CY of the dynamic node Y is composed of the diffusion capacitances of the pre- and discharge transistors, the gate capacitance of the connecting inverter, and the wire capacitance. A nonrelated signal Y is routed as a Metal1 wire over the polysilicon gate of one of the transistors in the inverter. This creates a parasitic capacitance CXY with respect to node Y. Suppose now that node Y is precharged to 2.5 V and that signal X undergoes a transition from 2.5 V to 0 V. The charge redistribution causes a voltage drop V Y on node Y, as given by Eq. (9.1). Assume that CX equals 6 fF. An overlap of 3× 1 m2 between metal1 and polysilicon results in a parasitic coupling capacitance of 0.5 fF (3 × 1 × 0.057 + 2 × 3 × 0.054), as obtained from Table 4.2. The computation of the fringing effect in the case of overlapping wires is complex and depends upon the relative orientation of the wires. We assumed in this analysis that two sides of the cross section contribute. A 2.5 V transition on Y thus causes a voltage disturbance of 0.19 V on the dynamic node (or 7.5%). Combined with other parasitic effects, such as charge redistribution and clock feedthrough, this might lead to circuit malfunctioning.
V DD CLK
C XY Y CY PDN X 2.5 V 0V
In 1 In 2 In 3 CLK
Figure 9.2 Cross talk in dynamic circuits.
Driven Lines If the line Y is driven with a resistance RY, a step on line X results in a transient on line Y (Figure 9.3a). The transient decays with a time constant τXY = R Y(CXY +CY ). The actual impact on the "victim line" is a strong function of the rise (fall) time of the interfering signal. If the rise time is comparable or larger than the time constant, the peak value of disturbance is diminished. This is illustrated by the simulated waveforms of b. Obviously, keeping the driving impedance of a wire—and hence τXY —low goes a long way towards reducing the impact of capacitive cross talk. The keeper transistor, added to a dynamic gate or precharged wire, is an excellent example of how impedance reduction helps to control noise. In summary, the impact of cross talk on the signal integrity of driven nodes is rather limited. The resulting glitches may cause malfunctioning of connecting sequential ele-
chapter9.fm Page 409 Friday, April 5, 2002 4:15 PM
Section 9.2
Capacitive Parasitics
409
X RY VX CXY Y CY
V (Volt)
0.5 0.45 0.4 0.35 0.3 0.25 0.2 0.15 0.1 0.05 0
t r = 5 psec tr = 100 psec tr = 200 psec
tr = 500 psec
(a) Driven line Y with interferer X
Figure 9.3 Capacitive coupling to a driven line.
0
0.2
0.4
0.6
0.8 x 10
1
-9
t(sec)
(b) Voltage response for different rise times of V x (0 t0 2.5 V) (Rx = 10 k, C y = 20 fF, C xy = 5 fF)
ments, and should therefore be carefully monitored. However, the most important effect is an increase in delay as is discussed in a subsequent paragraph. Design Techniques—Dealing with Capacitive Cross Talk Cross talk is a proportional noise source. This means that scaling the signal levels to increase noise margins does not help since the noise sources scale in a similar way. The only options in addressing the problem is to control the circuit geometry, or to adopt signaling conventions that are less sensitive to coupled energy. A number of ground rules can be established (as advocated in [Dally98]). 1. It is obviously not a good idea to allow the capacitance between two signal wires to grow too large if one wants to keep cross talk at a minimum. It is, for instance, bad practice to have two wires on the same layer run parallel for a long distance. One is often tempted to do just that when distributing the two clocks in a two-phase system or when routing a bus. Wires on adjacent layers should be run perpindicular. 2. Avoid floating nodes if at all possible. Nodes sensitive to cross talk problems, such as precharged busses, should be equiped with keeper devices to reduce the impedance. 3. Sensitive nodes should be well-separated from full-swing signals. 4. Make the rise (fall) time as large as possible, subject to timing constraints. 5. Use differential signaling in sensitive low-swing wiring networks. This turns the cross talk signal into a common-mode noise source that does not impact the operation of the circuit. 6. If necessary, provide a shielding wire—GND or VDD —between the two signals (Figure 9.4). This effectively turns the interwire capacitance into a capacitance-toground and eliminates interference.
chapter9.fm Page 410 Friday, April 5, 2002 4:15 PM
410
COPING WITH INTERCONNECT
Chapter 9
7. The interwire capacitance between signals on different layers can be further reduced by the addition of extra routing layers. When four or more routing layers are available, we can fall back to an approach often used in printed circuit board design. Every signal layer is interleaved with a GND or VDD metal plane (Figure 9.4).
Shielding wire GND
V DD
Shielding layer
GND Figure 9.4 Cross section of routing layers, illustrating the use of shielding to reduce capacitive cross talk.
Substrate (GND)
9.2.2
Capacitance and Performance in CMOS
Cross Talk and Performance The previous section discussed the impact of capacitive crosstalk on the signal integrity. Even when cross talk does not result in fatal breakdown of the circuit, it still should be monitored carefully as it also impacts the performance of the gate. The circuit schematic of Figure 9.5 is illustrative of how capacitive cross talk may result in a data-dependent variation of the propagation delay. Assume that the inputs to the three parallel wires X, Y,
X
Cc Y Cc Z Figure 9.5 Impact of cross talk on propagation delay.
and Z experience simultaneous transitions. Wire Y (called the victim wire) switches in a direction that is opposite to the transitions of its neighboring signals X and Z. The coupling
chapter9.fm Page 411 Friday, April 5, 2002 4:15 PM
Section 9.2
Capacitive Parasitics
411
capacitances experience a voltage swing that is double the signal swing, and hence represent an effective capacitive load that is twice as large as Cc—the by now well-known Miller effect. Since the coupling capacitance represents a large fraction of the overall capacitance in the deep-submicron dense wire structures, this increase in capacitance is substantial, and has a major impact on the propagation delay of the circuit. Observe that this is a worst-case scenario. If all inputs experience a simultaneous transition in the same direction, the voltage over the coupling capacitances remains constant, resulting in a zerocontribution to the effective load capacitance. The total load capacitance CL of gate Y hence depends upon the data activities on the neighboring signal,s and varies between the following bounds: C G N D ≤ CL ≤ C GND + 4C c (9.2)
with CGND the capacitance of node Y to ground, including the diffusion and fanout capacitances. In [Sylvester98], it was established that for a 0.25 m technology the wire delay with noise is potentially 80% larger than the wire delay without noise (scenario of Figure 9.5; wire length = 100 m, fanout = 2). Complicating the analysis of this problem is the fact that the capacitance not only depends upon the values of the surrounding wires, but also upon the exact timing of the transitions. The simultaneity of transitions can only be detected from detailed timing simulations, making the timing verification process substantially more complex. The ensuing explosion in verification cost caused by the unpredictably of the actual delay is hence a source of major concern. Just assuming worst-case conditions for the capacitances—this is, always assuming the Miller effect—leads to an overly pessimistic estimation, and overkill in the circuit design. Design Techniques—Circuit Fabrics with Predictable Wire Delay
With cross talk making wire-delay more and more unpredictable, a designer can choose between a number of different methodology options to address the issue, some of which are enumerated below. 1. Evaluate and improve—After detailed extraction and simulation, the bottlenecks in delay are identified, and the circuit is appropriately modified. 2. Constructive layout generation—Wire routing programs take into account the effects of the adjacent wires, ensuring that the performance requirements are met. 3. Predictable structures—By using predefined, known, or conservative wiring structures, the designer is ensured that the circuit will meet his specifications and that cross talk will not be a show stopper. The first approach is the one most often used. It has the disadvantage of requiring many iterations through the complete design generation process, and hence being very slow. The second technique is appealing. The complexity of the required tool set makes it however doubtful how much of this ambitious goal is actually achievable in a reliable (and affordable) way in the foreseeable future. although major inroads have been made already. The last approach may be the only one that is really workable in the short haul. Just as regular structures helped to tame
chapter9.fm Page 412 Friday, April 5, 2002 4:15 PM
412
COPING WITH INTERCONNECT
Chapter 9
the complexity of transistor layout in the early 1980's, regular and predictable wiring topologies may be the way to address the capacitive cross talk problem. Field-programmable gate arrays (FPGA's), with their well-characterized interconnect grid, are an example in case. The availability of multiple layers of metal interconnect makes this approach viable for semi-custom (and custom) design as well. The dense wire fabric [Khatri99], shown in Figure 9.6, preV S G S V S V S G S V S
V
V
S
V SS GG S
V
S S
Figure 9.6 Dense wire fabric (DWF) [Khatri99]. S, V, and G stand for Signal, V D D, and GND, respectively.
sents such a solution. Minimum-width wires are prewired on a minimum pitch distance. Wires on adjacent layers are routed orthogonally, mimimizing the cross talk. Signals on the same layer are separated by VD D or GND shields. The wiring structure is personalized by providing via's at the appropriate places. The advantage of the approach is that cross talk is virtually eliminated, and that delay variation is reduced to maximally 2%. This comes at a cost in area, and a 5% capacitance—and hence performance and power—increase. For most designs, the reduction in design and verification time easily compensates for this performance penalty.
Capacitive Load and Performance The increasing values of the interconnect capacitances, especially those of the global wires, emphasize the need for effective driver circuits that can (dis)charge capacitances with sufficient speed. This need is further highlighted by the fact that in complex designs a single gate often has to drive a large fan-out and hence has a large capacitive load. Typical examples of large on-chip loads are busses, clock networks, and control wires. The latter include, for instance, reset and set signals. These signals control the operation of a large number of gates, so fan-out is normally high. Other examples of large fan-outs are encountered in memories where a large number of storage cells is connected to a small set of control and data wires. The capacitance of these nodes is easily in the multi-picofarad range. The worst case occurs when signals go off-chip. In this case, the load consists of the package wiring, the printed circuit board wiring, and the input capacitance of the connected ICs or components. Typical off-chip loads range from 20 to 50 pF, which is multi-
chapter9.fm Page 413 Friday, April 5, 2002 4:15 PM
Section 9.2
Capacitive Parasitics
413
ple thousand times larger than a standard on-chip load. Driving those nodes with sufficient speed becomes one of the most crucial design problems. The main secrets to the efficient driving of large capacitive loads was already unveiled in Chapter 5.They boil down to two dominant concepts: Adequate transistor sizing is instrumental when dealing with large loads, Partitioning drivers into chains of gradually-increasing buffers helps to deal with large fanout factors. Some other important conclusions from that analysis are worth repeating for the sake of clarity: When optimizing for performance, the delay of a multi-stage driver should be partitioned equally over all stages. If the number of stages can be freely chosen, a fanout (sizing) factor of approximately 4 per stage leads to the minimum delay for contemporary semiconductor processes. Choosing factors that are somewhat larger do not impact the performance that much, while yielding substantial area benefits. In the following sections, we elaborate further on this topic. We focus especially on the driving of very large capacitances, such as encountered when going off-chip. We also introduce some special, but useful driver circuits. Driving Off-Chip Capacitances—A Case Study. As established in Chapter 2, the increase in complexity of today's integrated circuits translates in an explosive need for input/outputs pins. Packages with over 1000 pins have become a necessity. This puts tough requirements on the bonding-pad design in terms of noise immunity. The simultaneous switching of a lot of pads, each driving a large capacitor, causes large transient currents and creates voltage fluctuations on the power and ground lines. This reduces the noise margins and affects the signal integrity, as will become apparent later in this chapter. At the same time, technology scaling reduces the internal capacitances on the chip, while off-chip capacitances remain approximately constant—typically 10-20 pF. The overall effective fanout factor F of an output-pin driver hence experiences a net increase when scaling technologies. In a consistent system-design approach, we expect the off-chip propagation delays to scale in the same way as the on-chip delays. This puts an even tougher burden on the bonding-pad buffer design. The challenges associated with a bonding-pad driver design are illustrated with a simple case study.
Example 9.2 Output Buffer-Design Consider the case where an on-chip minimum-size inverter has to drive an off-chip capacitor CL of 20 pF. Ci equals approximately 2.5 fF for a standard gate in a 0.25 m CMOS process. This corresponds to a t p0 of approximately 30 psec. The overall effective fanout F (the ratio between CL and Ci) equals 8000, which definitely calls for a multistage buffer design. From Eq. (5.36) and assuming that γ = 1, we learn that seven stages result in a near-optimal design with a scaling factor f of 3.6, and an overall propagation delay of 0.76 nsec. With a PMOS / NMOS ratio of 1.9— the optimum ratio derived for our standard process parameters in Example 5.6—and a minimum dimension of 0.25 m, we can derive the widths for the NMOS and PMOS transistors in the consecutive inverter stages, as shown in Table 9.1.
chapter9.fm Page 414 Friday, April 5, 2002 4:15 PM
414
Table 9.1 Stage W n (m) W p (m)
COPING WITH INTERCONNECT
Transistor sizes for optimally-sized cascaded buffers. 1 0.375 0.71 2 1.35 2.56 3 4.86 9.2 4 17.5 33.1 5 63 119.2 6 226.8 429.3
Chapter 9
7 816.5 1545.5
This solution obviously requires some extremely large transistors with gate widths of up to 1.5 mm! The overall size of this buffer equals several thousand minimum-size inverters, which is quite prohibitive as a complex chip requires a large number of those drivers. This argument clearly illustrates the enormous cost associated with attempting to achieve optimum delay.
Trading off Performance for Area and Energy Reduction. Fortunately, it is not necessary to achieve the optimal buffer delay in most cases. Off-chip communications can often be performed at a fraction of the on-chip clocking speeds. Relaxing the delay requirements still allows for off-chip clock speeds in excess of 100 Mhz, while substantially reducing the buffering requirements. This redefines the buffer design problem. Given a maximum propagation delay time tp,max, determine the number of buffer stages N and the required scaling factor f, such that the overall area is minimized. This is equivalent to finding a solution that sets tp as close as possible to tp,max. The optimization problem is now reformulated into the finding of the minimum integer value of N that obeys the constraints of Eq. (9.3). tp ,m a x f ------------- ≥ ln ( F ) ----------- = N × F1 N tp 0 ln ( f ) (9.3)
This transcendental optimization problem can be solved using a small computer program or using mathematical packages such as MATLAB [Etter93]. Figure 9.7 plots the righthand side of this equation as a function of N for some values of F. For a given value of the overall effective fanout F, and a maximum value of the delay (tpmax/tpo), the minimum number of buffers N is derived from inspection of the appropriate curve. Using the total width of the transitors as a measure, we can also project the area savings of the larger scaling factor. Assuming that the area of the minimum inverter equals Amin , and that scaling the transistors with a factor f results in a similar area increase, we can derive the area of the driver as a function of f. Adriver = ( 1 + f + f + … + f
N 2 N–1
)A min (9.4)
f –1 F–1 = ------------- Am i n = ------------ Amin f – 1 f–1
In short, the area of the driver is approaximately inversely proportional to the tapering factor f. Choosing larger values of f can help to substantially reduce the area cost.
chapter9.fm Page 415 Friday, April 5, 2002 4:15 PM
Section 9.2
Capacitive Parasitics
415
10,000 F = 10,000
1000 tp/tp 0 100 F = 1000 F = 100 Figure 9.7 tp/tp 0 as a function of the number of buffer stages for various values of the overall fanout F. 10 1 3 5 7 9 Number of buffer stages N 11
It is also worth reflecting briefly on the energy dissipation of the exponential buffer. While it takes an amount of energy equal to CLVDD 2 to just switch just the load capacitance, the driver itself consumes energy as well to switch its internal capacitances (ignoring short-circuit energy). This overhead energy is approximated by the expression below, E driver = ( 1 + f + f + … + f
2 N–1
)C i V DD (9.5)
2
CL 2 2 F–1 = ------------ Ci VD D ≈ ----------V DD f – 1 f–1
This means that driving a large capacitance fast (suing the optimum taperaing factor of 3.6) takes an extra 40% of energy. For large load capacitances, this is a substantial overhead. Backing off somewhat from the optimum tapering factor can help to reduce the extra dissipation.
Example 9.3 Output Driver Design—Revisited Applying these results to the bonding-pad driver problem and setting tp,max to 2 nsec results in the following solution: N = 3, f = 20, and tp = 1.8 nsec. The required transistor sizes are summarized in Table 9.2.
Table 9.2 Transistor sizes of redesigned cascaded buffer. Stage Wn ( m ) Wp ( m ) 1 0.375 0.71 2 7.5 14.4 3 150 284
The overall area of this solution is approximately 7.5 times smaller than the optimum solution, while its speed is reduced by less than a factor of 2.5. It also reduces the extra energy dissipation per switching transition due to the buffer intrinsic capacitances to an almost negligible amount. The overall dissipation of the combined buffer and load is reduced by 24%,
chapter9.fm Page 416 Friday, April 5, 2002 4:15 PM
416
COPING WITH INTERCONNECT
Chapter 9
which corresponds to a hefty amount given the size of the load capacitor. This clearly shows that designing a circuit for the right speed, not for the maximum speed, pays off!
Design Consideration—Implementing Wide Transistors
Even this redesigned buffer requires wide transistors. One must be careful when designing those devices, since the large value of W translates into very long gate connections. Long polyD(rain) Multiple Contacts S
D G
S(ource) polysilicon G(ate) (a) Small transistors in parallel Figure 9.8 Approaches to implementing very wide transistors. (b) Circular transistors S
silicon wires tend to be highly resistive, which degrades the switching performance. This problem can be addressed in a number of ways. For instance, a wide transistor can be constructed by connecting many smaller transistors in parallel (Figure 9.8a) or by using ring- or even spiral-shaped devices (Figure 9.8b). In each approach, the resistance of the gate is reduced with the aid of a low-resistance metal bypass connecting the shorter polysilicon sections. An example of a pad driver designed using these techniques is shown in Figure 9.9.
Design Consideration—Designing Reliable Input/Output Pads Design Challenge—Designing Reliable Output and Input Pads The design of bonding pad-drivers is obviously a critical and nontrivial task that is further complicated by noise and reliability considerations. For instance, the large transient currents resulting from the switching of the huge output capacitance can cause latchup to occur. Multiple well and substrate contacts supplemented with guard rings help avoid the onset of this destructive effect. Guard rings are grounded p+ diffusions in a p-well and supply-connected n+ diffusions in an n-well that are used to collect injected minority carriers before they reach the base of the paraistic bipolar transistors. These rings should surround the NMOS and PMOS transistors of the final stage of the output pad driver. The designer of an input pad faces some different challenges. The input of the first stage of the input buffer is directly connected to external circuitry, and is hence sensitive
chapter9.fm Page 417 Friday, April 5, 2002 4:15 PM
Section 9.2
Capacitive Parasitics
417
Bonding pad
GND
In
Out n + guard ring
In V DD GND Out
Figure 9.9 Layout of final stage of bonding-pad driver. The plot on the right side is a magnification of the NMOS transistor connected between GND and Out. See also Colorplate 13.
to any voltage excursions on the connected input pins. A human walking over a synthetic carpet over in 80% relative humidity can accumulate a voltage potential of 1.5 kV—you have probably experienced the sparks that jump from your hand when touching a metal object under those circumstances. The same is true for the assembly machinery. The gate connection of an MOS transistor has a very high input resistance (10 12 to 1013 ). The voltage at which the gate oxide punctures and breaks down is about 40-100 V, and is getting smaller with reducing oxide thicknesses. A human or machine, charged up to a high static potential, can hence easily cause a fatal breakdown of the input transistors to happen when brought in contact with the input pin. This phenomenum called Electrostatic Discharge (ESD) has proven to be fatal to many circuits duirng manufacturing and assembly. A combination of resistance and diode clamps are used to defray and limit this potentially destructive voltage. A typical electrostatic protection circuit is shown in Figure 9.10a. The protection diodes D1 and D2 turn on when the voltage at node X rises below VDD or goes below ground. The resistor R is used to limit the peak current that flows in the diodes in the event of an unusual voltage excursion. Current process tend to use tub resistors (p-diffusion in an n-well, and n-diffusion for a p-well) to implement the resistors, and values can be anywhere from 200 to 3 k. The designer should be aware that the resulting RC time-constant can be a performance limiting factor in high-speed circuits. Figure 9.10b shows the layout of a typical input pad.
chapter9.fm Page 418 Friday, April 5, 2002 4:15 PM
418
COPING WITH INTERCONNECT
Chapter 9
VDD D1 R PAD D2 (a) C X
Figure 9.10 Input protection Circuit (a), and layout of input pad (b).
BUFFER RESISTOR
Diode
PAD
(b)
The task of the pad designer seems to become harder for every new technology generation. Fortunately, a number of novel packaging technologies that reduce off-chip capacitance, are currently emerging. For instance, advanced technqiues such as ball grid arrays and chip-on-board go a long way in helping to reducing the off-chip driving requirements (see also Chapter 2). Some Interesting Driver Circuits. Sofar, most of our driver circuits have been simple inverters. Sometimes, some variants are necessary. The tri-state buffer is an example of such. Busses are essential in most digital systems. A bus is a bundle of wires that connect a set of sender and receiver devices such as processors, memories, disks, and input/output devices.When one device is sending on the bus, all other sending devices should be disconnected. This can be achieved by putting the output buffers of those devices in a highimpedance state Z that effectively disconnects the gate from the output wire. Such a buffer has three possible states—0, 1, and Z—and is therefore called a tri-state buffer. Implementing a tri-state inverter is straightforward in CMOS. Simultaneously turning off the NMOS and PMOS transistor produces a floating output node that is disconnected from its input. Two possible implementations of a tri-state buffer are shown in Figure 9.11. While the first one is simple, the second is more appropriate for driving large capacitances. Having transistors in series in the output stage is to be avoided due to the huge area overhead.
chapter9.fm Page 419 Friday, April 5, 2002 4:15 PM
Section 9.3
Resistive Parasitics
VD D V DD En
419
In
En Out En En In
Out
Figure 9.11 Two possible implementations of a tri-state buffer. En = 1 enables the buffer.
9.3
Resistive Parasitics
In this section, we discuss the impact of wiring resistance on reliability and performance. Before doing so, we first analyze the effects of scaling on the wiring resistance and introduce a number of approximative models for resistive wires. 9.3.1 Resistance and Reliability—Ohmic Voltage Drop
Current flowing through a resistive wire results in an ohmic voltage drop that degrades the signal levels. This is especially important in the power distribution network, where current levels can easily reach amperes, as illustrated in Figure 9.12 for the Compaq Alpha processor family. Consider now a 2 cm long V DD or GND wire with a current of 1mA per m
140
S upply Current (A)
3.5 2.5 2 1.5 1 0.5 0 EV4 EV5 EV6 EV7 EV8
Supply Voltage (V)
120 100 80 60 40 20 0
3
Figure 9.12 Evolution of power-supply current and supply voltage for different generations of the high-performance alpha microprocessor family from Compaq. Even with the reductions in supply voltage, a total supply current of over 100 A has to be supported for the newer generations.
width. This current is about the maximum that can be sustained by an aluminum wire due to electromigration, which is discussed in the subsequent section. Assuming a sheet resistance of 0.05 /q, the resistance of this wire (per m width) equals 1 k. A current of 1 mA/m would result in a voltage drop of 1 V. The altered value of the voltage supply reduces noise margins and changes the logic levels as a function of the distance from the supply terminals. This is demonstrated by the circuit in Figure 9.13, where an inverter placed far from the power and ground pins connects to a device closer to the supply. The difference in logic levels caused by the IR voltage drop over the supply rails might partially turn on transistor M1. This can result in an accidental discharging of the precharged, dynamic node X, or cause static power consumption if the connecting gate is static. In
chapter9.fm Page 420 Friday, April 5, 2002 4:15 PM
420
COPING WITH INTERCONNECT
Chapter 9
V DD
I
φ pre X M1 V
R′
V D D – V′
I
V Figure 9.13 Ohmic voltage drop on the supply rails reduces the noise margins.
R
short, the current pulses from the on-chip logic, memories and I/O pins cause voltage drops over the power-distribution network, and are the major source for on-chip powersupply noise. Beyond causing a reliability risk, IR drops on the supply network also impact the performance of the system. A small drop in the supplu voltage may cause a significant increase in delay. The most obvious solution to this problem is to reduce the maximum distance between the supply pins and the circuit supply connections. This is most easily accomplished through a structured layout of the power distribution network. A number of onchip power-distribution networks with peripheral bonding are shown in Figure 9.14. In all
(a) (b)
(c) Figure 9.14 On-chip power distribution networks. (a) Single layer power grid; (b) Dual layer grid; (c) Dual power plane.
cases, power and ground are brought onto the chip via bonding pads located on the four sides of the chip. Which approach to use depends upon the number of coarse metal layers (this is, thick, high pitch topmost metal layers) one wants to allocate to power distribution.
chapter9.fm Page 421 Friday, April 5, 2002 4:15 PM
Section 9.3
Resistive Parasitics
421
In the first approach (a), power and ground are routed vertically (or horizontally) on the same layer. Power is brought in from two sides of the chip. Local power strips are strapped to this upper grid, and then further routed on the lower metal levels. Method (b) uses two coarse metal layers for the power distribution, and the power is brought in from the four sides of the die. This approach was used in the EV5 generation of the Compaq Alpha processor [Herrick00]. The combination of power and clock distribution occupied more than 90% of the 3rd and 4th Al layers. One further and more aggressive step to take is to use two solid metal planes for the distribrution of V dd and GND (c). This approach has the advantage of drastically reducing the resistance of the network. The metal planes also act as shields between data signalling layers, hence reducing cross-talk. They also help to reduce the on-chip inductance. Obviously, this approach is only feasible when sufficient metal layers are available. The sizing of the power network is a non-trivial task. The power grid can be modeled as a network of resistors (wires) and current sources (logic), containing hundreds of millions of elements. Very often, many paths exist between the power pins and the supply connections of a chip module or gate. While in general the current follows the path of the lowest resistance, the exact flow depends upon factors such as the current draw from neighboring modules that share the same network. The analysis is complicated by the fact that peak currents drawn by the connected modules are distributed over time. IR drop is a dynamic phenomenon due primarily to simultaneous switching events such as clocks, and bus drivers. As large drivers begin to switch, the simultaneous demand from current from the power network stresses the grid. At the same time, a worst-case analysis adding all the peak currents may lead to a gross overdimensioning of the wires. The above makes it clear that computer-aided design tools are a necessary companion of the power-distribution network designer. Given the complexity of todays integrated circuits, transistor-level analysis of the complete power-network requirements is just not feasible. At the same time, partitioning of the problem over sub-sections might not result in an accurate picture either. Changes to the power grid in one section tend to have a global impact. This is illustrated in Figure 9.15, which shows the simulated IR voltage drop of a complex digital circuit. A first implementation (a) suffers from a more than acceptable drop in the upper right module of the design, because only the top portion of the power grid feeds the large drivers at the top. The lower portions of the module are not directly connected to the grid. Adding just one single strap to the network largely resolves this problem, as shown in (b). Therefore, an accurate picture of the IR risk cannot be obtained unless the entire chip is verified as a single entity. Any tool used for this purpose must have the capacity to analyze multi-million resistor grids. Fortunately, a number of efficient and quite accurate power-grid analysis tools are currently available [Simplex, ]. They combine a dynamic analyis of the current requirements of the circuit modules with a detailed modeling of the popwer network. Tools as such are quite indispensable in todays design process. 9.3.2 Electromigration
The current density (current per unit area) in a metal wire is limited due to an effect called electromigration. A direct current in a metal wire running over a substantial time period,
chapter9.fm Page 422 Friday, April 5, 2002 4:15 PM
422
COPING WITH INTERCONNECT
Chapter 9
Highest voltage drop
(a)
(b)
Figure 9.15 Simulated IR voltage drop in power-distribution network of two versions of a complex digital integrated circuit. The gray-scale is used to indicate the severeness of the voltage drop. Adding an extra strap to the upper layers of the power network (b) helps to address the large voltage trop in the upper right module in the initial design (a).
causes a transport of the metal ions. Eventually, this causes the wire to break or to shortcircuit to another wire. This type of failure will only occur after the device has been in use for some time. Some examples of failure caused by migration are shown in Figure 9.16. Notice how the first photo clearly shows hillock formation in the direction of the electron current flow.
(a) Line-open failure. Figure 9.16
(b) Open failure in contact plug.
Electromigration-related failure modes (Courtesy of N. Cheung and A. Tao, U.C. Berkeley).
The rate of the electromigration depends upon the temperature, the crystal structure, and the average current density. The latter is the only factor that can be effectively controlled by the circuit designer. Keeping the current below 0.5 to 1 mA/m normally prevents migration. This parameter can be used to determine the minimal wire width of the power and ground network. Signal wires normally carry an ac-current and are less susceptible to migration. The bidirectional flow of the electrons tends to anneal any damage done
chapter9.fm Page 423 Friday, April 5, 2002 4:15 PM
Section 9.3
Resistive Parasitics
423
to the crystal structure. Most companies impose a number of strict wire-sizing guidelines on their designers, based on measurements and past experience. Research results have shown that many of these rules tend to be overly conservative [Tao94]. Design Rule
Electromigration effects are proportional to the average current flow through the wire, while IR voltage drops are a function of the peak current.
At the technology level, a number of precautions can be taken to reduce the migration risk. One option is to add alloying elements (such as Cu or Tu) to the aluminum to prevent the movement of the Al ions. Another approach is to control the granularity of the ions. The introduction of new interconnect materials is a big help as well. For instance, the use of Copper interconnect increases the expected lifetime of a wire with a factor of 100 over Al. 9.3.3 Resistance and Performance—RC Delay
In Chapter 4, we established that the delay of a wire grows quadratically with its length. Doubling the length of a wire increases its delay by a factor of four! The signal delay of long wires therefore tends to be dominated by the RC effect. This is becoming an ever larger problem in modern technologies, which feature an increasing average length of the global wires (Figure 4.27)—at the same time that the average delay of the individual gates is going down. This leads to the rather bizar situation that it may take multiple clock cycles to get a signal from one side of a chip to its opposite end [Dally-DAC]. Providing accurate synchronization and correct operation becomes a major challenge under these circumstances. In this section, we discuss a number of design techniques that may help to cope with the delay imposed by the resistance of a wire. Better Interconnect Materials A first option for reducing RC delays is to use better interconnect materials when they are available and appropriate. The introduction of silicides and Copper have helped to reduce the resistance of polysilicon (and diffused) and metal wires, respectively, while the adoption of dielectric materials with a lower permittivity lowers the capacitance. Both Copper and low-permittivity dielectrics have become common in advanced CMOS technologies (starting from the 0.18 m technology generation). Yet, the designer should be aware that these new materials only provide a temporary respite of one or two generations, and do not solve the fundamental problem of the delay of long wires. Innovative design techniques are often the only way of coping with the latter.
chapter9.fm Page 424 Friday, April 5, 2002 4:15 PM
424
COPING WITH INTERCONNECT
Chapter 9
Example 9.4 Impact of Advanced Interconnect Materials Copper offers a resistivity that is 1.6 times lower than that of Aluminum (Table 4.4) from a pure material perspective. Cladding and other manufacturing artifacts may increase the effective resistivity of on-chip Cu wires to approximately 2.2 10-8 -m.
Sometimes, it is hard to avoid the use of long polysilicon wires. A good example of such circumstance are the address lines in memories, which must connect to a large number of transistor gates. Keeping the wires in polysilicon increases the memory density substantially by avoiding the overhead of the extra metal contacts. The polysilicon-only option unfortunately leads to an excessive propagation delay. One possible solution is to drive the word line from both ends, as shown in Figure 9.17a. This effectively reduces the worst-case delay by a factor of four. Another option is to provide an extra metal wire, called a bypass, which runs parallel to the polysilicon one, and connects to it every k cells (Figure 9.17b). The delay is now dominated by the much shorter polysilicon segments between the contacts. Providing contacts only every k cells helps to preserve the implementation density.
Driver WL Polysilicon word line
Metal word line
(a) Driving the word line from both sides Metal bypass
WL
K cells (b) Using a metal bypass
Polysilicon word line
Figure 9.17
Approaches to reduce the word-line delay.
Better Interconnect Strategies With the length of the wire being a prime factor in both the delay and the energy consumption of an interconnect wire, any approach that helps to reduce the wire length is bound to have an essential impact. It was pointed out earlier that the addition of interconnect layers tends to reduce the average wire length, as routing congestion is reduced and interconnections can pretty much follow a direct path between source and destination. Yet, the "Mahattan-style" wiring approach that is typical in todays routing tools brings with it a substantial amount of overhead that is often overlooked. In the Manhattan-style routing, interconnections are routed first along one of two preferred directions, followed by a connection in the other direction (Figure 9.18a). It seems obvious that routing along the diagonal direction would yield a sizable reduction in wirelength—of up to 29% in the best case. Ironically, 45° lines were very popolar in the early days of integrated circuits
chapter9.fm Page 425 Friday, April 5, 2002 4:15 PM
Section 9.3
Resistive Parasitics
425
designs, but got of out of vogue because of complexity issues, impact on tools, and maskmaking concerns. Recently, it has been demonstrated that these concerns can be addressed adequately, and that 45° lines are perfectly feasible [Simplex01]. The impact on wiring is quite tangible: a reduction of 20% in wirelength! This in turn results in higher performance, lower power dissipation, and smaller chip area. The density of wiring structures that go beyond pure Manhattan directions, is demonstrated clearly in a sample layout, shown in Figure 9.18b. destination
go di a na l
y
source x
Manhattan
(a)
Figure 9.18 Manhattan versus diagonal routing. (a) Manhattan routing uses preferential routing along orthogonal axis, while diagonal routing allows for 45° lines. (b) example of layout using 45° lines.
(b)
Introducing Repeaters The most popular design approach to reducing the propagation delay of long wires is to introduce intermediate buffers, also called repeaters, in the interconnect line (Figure 9.19). Making an interconnect line m times shorter reduces its propagation delay quadratically, and is sufficient to offset the extra delay of the repeaters when the wire is sufficiently long. Assuming that the repeaters have a fixed delay tpbuf , we can derive the delay of the partitioned wire. L tp = 0.38 rc -- m + mt pbuf - m
tpbuf R/m V in C/m C/m C/m C/m R/m R/m R/m V out
2
(9.6)
Figure 9.19
Reducing RC interconnect delay by introducing repeaters.
第三章、器件 一、超深亚微米工艺条件下MOS 管主要二阶效应： 1、速度饱和效应：主要出现在短沟道NMOS 管，PMOS 速度饱和效应不显著。主要原因是 TH G S V V -太大。在沟道电场强度不高时载流子速度正比于电场强度（μξν=） ，即载流子迁移率是常数。但在电场强度很高时载流子的速度将由于散射效应而趋于饱和，不再随电场 强度的增加而线性增加。此时近似表达式为：μξυ=（c ξξ<），c s a t μξυυ==（c ξξ≥） ，出现饱和速度时的漏源电压D SAT V 是一个常数。线性区的电流公式不变，但一旦达到DSAT V ，电流即可饱和，此时DS I 与GS V 成线性关系（不再是低压时的平方关系）。 2、Latch-up 效应：由于单阱工艺的NPNP 结构，可能会出现VDD 到VSS 的短路大电流。 正反馈机制：PNP 微正向导通，射集电流反馈入NPN 的基极，电流放大后又反馈到PNP 的基极，再次放大加剧导通。 克服的方法：1、减少阱/衬底的寄生电阻，从而减少馈入基极的电流，于是削弱了正反馈。 2、保护环。 3、短沟道效应：在沟道较长时，沟道耗尽区主要来自MOS 场效应，而当沟道较短时，漏衬结（反偏）、源衬结的耗尽区将不可忽略，即栅下的一部分区域已被耗尽，只需要一个较小的阈值电压就足以引起强反型。所以短沟时VT 随L 的减小而减小。 此外，提高漏源电压可以得到类似的效应，短沟时VT 随VDS 增加而减小，因为这增加了反偏漏衬结耗尽区的宽度。这一效应被称为漏端感应源端势垒降低。
4、漏端感应源端势垒降低（DIBL）： VDS增加会使源端势垒下降，沟道长度缩短会使源端势垒下降。VDS很大时反偏漏衬结击穿，漏源穿通，将不受栅压控制。 5、亚阈值效应（弱反型导通）：当电压低于阈值电压时MOS管已部分导通。不存在导电沟道时源（n+）体（p）漏（n+）三端实际上形成了一个寄生的双极性晶体管。一般希望该效应越小越好，尤其在依靠电荷在电容上存储的动态电路，因为其工作会受亚阈值漏电的严重影响。 绝缘体上硅（SOI） 6、沟长调制：长沟器件：沟道夹断饱和；短沟器件：载流子速度饱和。 7、热载流子效应：由于器件发展过程中，电压降低的幅度不及器件尺寸，导致电场强度提高，使得电子速度增加。漏端强电场一方面引起高能热电子与晶格碰撞产生电子空穴对，从而形成衬底电流，另一方面使电子隧穿到栅氧中，形成栅电流并改变阈值电压。 影响：1、使器件参数变差，引起长期的可靠性问题，可能导致器件失效。2、衬底电流会引入噪声、Latch-up、和动态节点漏电。 解决：LDD（轻掺杂漏）：在漏源区和沟道间加一段电阻率较高的轻掺杂n-区。缺点是使器件跨导和IDS减小。 8、体效应：衬底偏置体效应、衬底电流感应体效应（衬底电流在衬底电阻上的压降造成衬偏电压）。 二、MOSFET器件模型 1、目的、意义：减少设计时间和制造成本。 2、要求：精确；有物理基础；可扩展性，能预测不同尺寸器件性能；高效率性，减少迭代次数和模拟时间 3、结构电阻：沟道等效电阻、寄生电阻 4、结构电容： 三、特征尺寸缩小 目的：1、尺寸更小；2、速度更快；3、功耗更低；4、成本更低、 方式： 1、恒场律（全比例缩小），理想模型，尺寸和电压按统一比例缩小。 优点：提高了集成密度 未改善：功率密度。 问题：1、电流密度增加；2、VTH小使得抗干扰能力差；3、电源电压标准改变带来不便；4、漏源耗尽层宽度不按比例缩小。 2、恒压律，目前最普遍，仅尺寸缩小，电压保持不变。 优点：1、电源电压不变；2、提高了集成密度 问题：1、电流密度、功率密度极大增加；2、功耗增加；3、沟道电场增加，将产生热载流子效应、速度饱和效应等负面效应；4、衬底浓度的增加使PN结寄生电容增加，速度下降。 3、一般化缩小，对今天最实用，尺寸和电压按不同比例缩小。 限制因素：长期使用的可靠性、载流子的极限速度、功耗。
专升本《数字电路与逻辑设计》作业练习题6 解析与答案 一、单选题（选择最合适的答案） 1. 哪种逻辑门“只有在所有输入均为0时，输出才是1”? （） A．或非门B．与非门C．异或门D．与或非门 答案：A 解析: 或非门 2．设两输入“与非”门的输入为x和y，输出为z，当z＝1时，x和y的取值一定是（） A. 至少有一个为1 B. 同时为1 C. 同时为0 D. 至少有一个为0 答案：D 解析: 与非逻辑 3. 两输入与非门输出为0时，输入应满足（）。 A．两个同时为1 B．两个同时为0 C．两个互为相反D．两个中至少有一个为0 答案：A 解析:输入全为1 4. 异或门的两个输入为下列哪—种时，其输出为1？ A．1，l B．0，1 C．0，0 D．以上都正确 答案：B 解析: 输入不同 5. 下列逻辑门中哪一种门的输出在任何条件下都可以并联使用？（）A．具有推拉式输出的TTL与非门B．TTL集电级开路门(OC门) C．普通CMOS与非门D．CMOS三态输出门 答案：B 解析: A,C普通与非门不能并联使用； D三态输出门并联使用是有条件的：它们的使能端(控制端)必须反向，即只能有一个门处于非高阻态
ADABB 二、多选题（选择所有合适的答案） 用TTL 与非门、或非门实现反相器功能时，多余输入端应该( ) A ．与非门的多余输入端应接低电平 B. 或非门的多余输入端应接低电平 C. 与非门的多余输入端应接高电平 D. 或非门的多余输入端应接低高平 答案：BC 解析: 多余输入端对与逻辑要接1，对或逻辑要接0 三、简答题 1. 分析如下两个由或非门、异或门、非门以及与非门构成的逻辑电路，请你：①写出F1和F2的逻辑表达式；②当输入变量A ，B 取何值时，两个电路等效? 答案:{ ① 根据图可写出两个电路的输出函数表达式分别为： 12()F A A B A A B A A B A A B A AB AB A A B F AB A B =⊕+=?++?+=??+++=+==+ = ②列出两个电路的真值表： 可见，无论A,B 取任何值，两个电路都等效。 }
(此文档为word格式，下载后您可任意编辑修改！) 1.1将下列各式写成按权展开式： （352.6）10=3×102+5×101+2×100+6×10-1 （101.101）2=1×22+1×20+1×2-1+1×2-3 （54.6）8=5×81+54×80+6×8-1 （13A.4F）16=1×162+3×161+10×160+4×16-1+15×16-2 1.2按十进制0~17的次序，列表填写出相应的二进制、八进制、十六进制数。 解：略 解：分别代表28=256和210=1024个数。 （1750）8=（1000）10 （3E8）16=（1000）10 1.5将下列各数分别转换为二进制数：（210）8，（136）10，（88）16 1.6将下列个数分别转换成八进制数：（111111）2，（63）10，（3F）16 解：结果都为（77）8 解：结果都为（FF）16 1.8转换下列各数，要求转换后保持原精度： （0110.1010）余3循环BCD码=（1.1110）2 1.9用下列代码表示（123）10，（1011.01）2： 解：（1）8421BCD码： （123）10=（0001 0010 0011）8421BCD （1011.01）2=（11.25）10=（0001 0001.0010 0101）8421BCD （2）余3 BCD码 （123）10=（0100 0101 0110）余3BCD （1011.01）2=（11.25）10=（0100 0100.0101 1000）余3BCD （1）按二进制运算规律求A+B，A-B，C×D，C÷D， （2）将A、B、C、D转换成十进制数后，求A+B，A-B，C×D，C÷D，并将结果与（1）进行比较。 A-B=（101011）2=（43）10 C÷D=（1110）2=（14）10 （2）A+B=（90）10+（47）10=（137）10 A-B=（90）10-（47）10=（43）10 C×D=（84）10×（6）10=（504）10 C÷D=（84）10÷（6）10=（14）10 两种算法结果相同。
《数字集成电路基础》试题D （考试时间：120分钟） 班级： 姓名： 学号： 成绩： 一、填空题（共30分） 1. 当PN 结外加正向电压时，PN 结中的多子＿＿＿＿＿＿形成较大的正向电流。 2. NPN 型晶体三极管工作在饱和状态时，其发射结和集电结的外加电压分别处于 ＿＿＿＿＿＿偏置和＿＿＿＿＿＿＿偏置。 3. 逻辑变量的异或表达式为：_____________________B A =⊕。 4. 二进制数A=1011010；B=10111，则A-B=＿＿＿＿＿＿＿。 5. 组合电路没有＿＿＿＿＿＿功能，因此，它是由＿＿＿＿＿＿组成。 6. 同步RS 触发器的特性方程为：Q n+1=＿＿＿＿＿＿,其约束方程为：＿＿＿＿＿ ＿。 7. 将BCD 码翻译成十个对应输出信号的电路称为＿＿＿＿＿＿＿＿，它有＿＿＿ 个输入端，＿＿＿＿输出端。 8. 下图所示电路中，Y 1 ＝＿＿＿＿＿＿；Y ＝＿＿＿＿＿＿；Y 3 ＝＿＿＿＿＿ 二、选择题(共 20分) 1. 四个触发器组成的环行计数器最多有＿＿＿＿个有效状态。 A.4 B. 6 C. 8 D. 16 2. 逻辑函数D C B A F +=，其对偶函数F *为＿＿＿＿＿＿＿＿。 A ．()()D C B A ++ B. ()()D C B A ++ C. ()() D C B A ++ 1 A B 3
3. 用8421码表示的十进制数65，可以写成＿＿＿＿＿＿。 A ．65 B. [1000001]BCD C. [01100101]BCD D. [1000001]2 4. 用卡诺图化简逻辑函数时，若每个方格群尽可能选大，则在化简后的最简表达式 中 。 A ．与项的个数少 B. 每个与项中含有的变量个数少 C. 化简结果具有唯一性 5. 已知某电路的真值表如下，该电路的逻辑表达式为 。 A ．C Y = B. A B C Y = C ．C AB Y += D ．C C B Y += 三、化简下列逻辑函数，写出最简与或表达式：（共20分） 1． 证明等式:AB B A B A B A +?=+ 2． Y 2＝Σm （0，1，2，3，4，5，8，10，11，12） 3． Y 3＝ABC C AB C B A C B A +++?
1、解释基本概念：集成电路，集成度，特征尺寸 参考答案： A、集成电路（IC：integrated circuit）是指通过一系列特定的加工工艺，将晶体管、二极管等有源器件和电阻、电容等无源器件，按照一定的电路互连，“集成”在一块半导体晶片（如硅或砷化镓）上，封装在一个外壳内，执行特定电路或系统功能的集成块。 B、集成度是指在每个芯片中包含的元器件的数目。 C、特征尺寸是代表工艺光刻条件所能达到的最小栅长（L）尺寸。 2、写出下列英文缩写的全称：IC，MOS，VLSI，SOC，DRC，ERC，LVS，LPE 参考答案： IC：integrated circuit；MOS：metal oxide semiconductor；VLSI：very large scale integration；SOC：system on chip；DRC：design rule check；ERC：electrical rule check；LVS：layout versus schematic；LPE：layout parameter extraction 3、试述集成电路的几种主要分类方法 参考答案： 集成电路的分类方法大致有五种：器件结构类型、集成规模、使用的基片材料、电路功能以及应用领域。根据器件的结构类型，通常将其分为双极集成电路、MOS集成电路和Bi-MOS 集成电路。按集成规模可分为：小规模集成电路、中规模集成电路、大规模集成电路、超大规模集成电路、特大规模集成电路和巨大规模集成电路。按基片结构形式，可分为单片集成电路和混合集成电路两大类。按电路的功能将其分为数字集成电路、模拟集成电路和数模混合集成电路。按应用领域划分，集成电路又可分为标准通用集成电路和专用集成电路。 4、试述“自顶向下”集成电路设计步骤。 参考答案： “自顶向下”的设计步骤中，设计者首先需要进行行为设计以确定芯片的功能；其次进行结构设计；接着是把各子单元转换成逻辑图或电路图；最后将电路图转换成版图，并经各种验证后以标准版图数据格式输出。 5、比较标准单元法和门阵列法的差异。 参考答案：
1-1将下列二进制数转换成等值的十进制数和十六进制数。 （1）（1101010.01）2； （3）（11.0101）2； （2）（111010100.011）2； （4）（0.00110101）2； 解：二进制数按位权展开求和可得等值的十进制数；利用进制为2k数之间的特点可以直接将二进制数转换为等值的十六进制数。 （1）（1101010.01）2＝1×26＋1×25＋1×23＋1×21＋1×2－2 ＝（106.25）10＝（6A.4）16 （2）（111010100.011）2＝1×28＋1×27＋1×26＋1×24＋1×22＋1×2－2＋ 1×2－3＝（468.375）10＝（1D4.6）16 （3）（11.0101）2＝1×21＋1×20＋1×2－2＋1×2－4 ＝（3.3125）10＝（3.5）16 （4）（0.00110101）2＝1×2－3＋1×2－4＋1×2－6＋1×2－8 ＝（0.20703125）10＝（0.35）16 1-2将下列十进制数转换成等值的二进制数、八进制数和十六进制数。要求二进制数保留小数点后4位有效数字。 （1）（378.25）10； （3）（56.7）10； （2）（194.5）10； （4）（27.6）10； 解法1：先将十进制数转换成二进制数，再用进制为2k数之间的特点可以直接将二进制数转换为等值的八进制数和十六进制数。 （1）（378.25）10＝（101111010.0100）2＝（572.2）8＝（17A.4）16 （2）（194.5）10＝（11000010.1000）2＝（302.4）8＝（C2.8）16
（3）（56.7）10 ＝（111000.1011）2＝（70.54）8＝（38.B ）16 （4）（27.6）10 ＝（11011.1001）2＝（33.44）8＝（1B.9）16 解法 2：直接由十进制数分别求二进制、八进制和十六进制数。由于二进制 数在解法 1 已求出，在此以（1）为例，仅求八进制数和十六进制数。
设计目的： 1.掌握CMOS反相器和两级CMOS运算放大器的电路图基本原理。 2.熟练掌握并运用tanner作图软件。 3. 基本能根据仿真图对电路进行基本分析 一．CMOS反相器 1.工作原理 1）.基本电路结构 2）.开启电压|UTP|=UTN，且小于VDD。当uI= UIL=0V时，VTN截止，VTP导通， uO = UOH≈VDD当uI =UIH = VDD ，VTN导 通，VTP截止，uO =UOL≈0V 3.）工作特点 VTP和VTN总是一管导通而另一管截止，流过 VTP和VTN的静态电流极小（纳安数量级），因而 CMOS反相器的静态功耗极小。这是CMOS电路最 突出的优点之一。 2.用Tanner仿真 1）cmos反相器电路图
2）反相器 瞬时分析 生成t-spice文件如下： 进行仿真： 仿真状态窗口：
仿真结果报告文件：
3）反 相器 瞬时 分析 在 W-Ed it中 观看 仿真 结果 4）反相 器直流 分析在 W-Edit 中观看 仿真结 果 3.用Tanner画CMOS反相器版图
二．两级CMOS运算放大器设计 设计原理分析： 单级有源负载差动放大器的增益一般可达几十到几百倍左右。但作为运算放大器，这个增益是不够的，因此还需要多级级联。下面我们来分析两级CMOS运算放大器。 两级CMOS运算放大器的基本电路图如下：
V 9 V 3U r I D3 I D1 V 1 V 4U i I D4I D2V 2 V 5 U DD ?à??213￥C c A U o I SS V 8 V 7 V 6 U SS 图一 电路图 下面我们根据题设指标，tanner 下进行仿真，并进行分析： 已知: K N=μn C ox=25 μA /V2， K P=μpCox=12.5 μA /V2， Cc=5 pF ，功耗Pm ≤10 mW ，U DD=9 V ， λN=0.01 Ｖ-1,λP=0.015 V-2,U TH=1V 。 要求：Aud>5000，单位增益带宽GB=3MHz ，压摆率SR=2V/us 。 1. 根据总功率Pm=10mW ，Udd=9V ，可求出允许总电流I=Pm/Udd=1100uA 2. 根据压摆率SR=2V/us,算出第一级偏置电流Iss. SR=Io1(max)/Cc ，Io1=Id4-Id2=Id1-Id2,Id1最大值为Iss,Id2最小值为0，故Io1(max)=Iss 。Iss=SR*Cc=10uA 。 区Iss=100uA,Id1q=Id2=50uA.
数字电路与系统设计实验报告 学院： 班级： 姓名：
实验一基本逻辑门电路实验 一、实验目的 1、掌握TTL与非门、与或非门和异或门输入与输出之间的逻辑关系。 2、熟悉TTL中、小规模集成电路的外型、管脚和使用方法。 二、实验设备 1、二输入四与非门74LS00 1片 2、二输入四或非门74LS02 1片 3、二输入四异或门74LS86 1片 三、实验内容 1、测试二输入四与非门74LS00一个与非门的输入和输出之间的逻辑关系。 2、测试二输入四或非门74LS02一个或非门的输入和输出之间的逻辑关系。 3、测试二输入四异或门74LS86一个异或门的输入和输出之间的逻辑关系。 四、实验方法 1、将器件的引脚７与实验台的“地（GND）”连接，将器件的引脚１４与实验台的十5Ｖ连接。 2、用实验台的电平开关输出作为被测器件的输入。拨动开关，则改变器件的输入电平。 3、将被测器件的输出引脚与实验台上的电平指示灯(LED)连接。指示灯亮表示输出低电平（逻辑为０），指示灯灭表示输出高电平（逻辑为1）。 五、实验过程 1、测试74LS00逻辑关系 （1）接线图（图中Ｋ1、Ｋ2接电平开关输出端，LED0是电平指示灯） （2）真值表 2、测试74LS02逻辑关系
（1）接线图 （2）真值表 3、测试74LS86逻辑关系接线图 （1）接线图 （2）真值表 六、实验结论与体会 实验是要求实践能力的。在做实验的整个过程中，我们首先要学会独立思考，出现问题按照老师所给的步骤逐步检查，一般会检查处问题所在。实在检查不出来，可以请老师和同学帮忙。
实验二逻辑门控制电路实验 一、实验目的 1、掌握基本逻辑门的功能及验证方法。 2、掌握逻辑门多余输入端的处理方法。 3、学习分析基本的逻辑门电路的工作原理。 二、实验设备 1、基于CPLD的数字电路实验系统。 2、计算机。 三、实验内容 1、用与非门和异或门安装给定的电路。 2、检验它的真值表，说明其功能。 四、实验方法 按电路图在Quartus II上搭建电路，编译，下载到实验板上进行验证。 五、实验过程 1、用３个三输入端与非门IC芯片74LS10安装如图所示的电路。 从实验台上的时钟脉冲输出端口选择两个不同频率（约7khz和14khz）的脉冲信号分别加到X0和X1端。对应B和S端数字信号的所有可能组合，观察并画出输出端的波形，并由此得出S和B（及/Ｂ）的功能。 2、实验得真值表
Digital IC：数字集成电路是将元器件和连线集成于同一半导体芯片上而制成的数字逻辑电路或系统 第一章引论 1、数字IC芯片制造步骤 设计：前端设计（行为设计、体系结构设计、结构设计）、后端设计（逻辑设计、电路设计、版图设计） 制版：根据版图制作加工用的光刻版 制造：划片：将圆片切割成一个一个的管芯（划片槽） 封装：用金丝把管芯的压焊块（pad）与管壳的引脚相连 测试：测试芯片的工作情况 2、数字IC的设计方法 分层设计思想：每个层次都由下一个层次的若干个模块组成，自顶向下每个层次、每个模块分别进行建模与验证 SoC设计方法：IP模块（硬核（Hardcore)、软核（Softcore)、固核（Firmcore））与设计复用Foundry（代工）、Fabless（芯片设计）、Chipless（IP设计）“三足鼎立”——SoC发展的模式 3、数字IC的质量评价标准（重点：成本、延时、功耗，还有能量啦可靠性啦驱动能力啦之类的） NRE (Non-Recurrent Engineering) 成本 设计时间和投入，掩膜生产，样品生产 一次性成本 Recurrent 成本 工艺制造（silicon processing），封装（packaging），测试（test） 正比于产量 一阶RC网路传播延时：正比于此电路下拉电阻和负载电容所形成的时间常数 功耗：emmmm自己算 4、EDA设计流程 IP设计系统设计（SystemC）模块设计（verilog） 综合 版图设计(.ICC) 电路级设计（.v 基本不可读）综合过程中用到的文件类型(都是synopsys)： 可以相互转化 .db（不可读）.lib（可读） 加了功耗信息
课程设计说明书 课程设计名称数字电路与逻辑设计 专业计算机科学与技术 班级150403班 学生姓名陆文祥 指导教师宋宇 2016 年12 月19 日
课程设计任务书
题目：1.简易数字电子钟的设计与制作 2.简易数字频率计的设计与制作 3.简易智力竞赛抢答器的设计与制作 4.简易玩具电子琴的设计与制作 5.自选题目：自动电子钟 目录 设计实验一 (4) 设计实验二 (8) 设计实验三 (11) 设计实验四 (15) 自选题目 (20)
设计实验一 一、实验题目： 简易数字电子钟的设计与制作 二、设计目的 1、了解计时器主体电路的组成及工作原理； 2、掌握组合逻辑电路、时序逻辑电路及数字逻辑电路系统的设计、安装、测试方法； 3、熟悉集成电路及有关电子器件的使用； 三、实验要求 要求设计一个能显示两位秒信号的数字电子钟，分电路设计、电路安装、电路调测三个阶段完成。 四、实验内容 （一）.设计原理思路： 本次设计以数字电子为主，分别对时钟信号源、秒计时显示、分计时显示、小时计时显示进行设计，然后将它们组合，来完成时、分、秒的显示并通过本次设计加深对数字电子技术的理解以及更熟练使用计数器、触发器和各种逻辑门电路的能力。电路主要使用集成计数器，如74ls90、74ls48，LED数码管及各种门电路和基本的触发器等，电路使用直流电源供电，很适合在日常生活中使用数字钟实际上是一个对标准频率（1HZ）进行计数的计数电路。数字电子钟由以下几部分组成：六十进制秒、分计数器、二十进制时计数器；以及秒、分、时的译码显示部分等。 （二）实验电路图 图1 数字电子钟
数字集成电路设计 实验报告 实验名称二输入与非门的设计 一．实验目的 a)学习掌握版图设计过程中所需要的仿真软件
b)初步熟悉使用Linux系统 二．实验设备与软件 PC机，RedHat,Candence 三．实验过程 Ⅰ电路原理图设计 1.打开虚拟机VMware Workstation，进入Linux操作系统RedHat。 2.数据准备，将相应的数据文件拷贝至工作环境下，准备开始实验。 3.创建设计库，在设计库里建立一个schematic view，命名为，然后进入电路 图的编辑界面。 4.电路设计 设计一个二输入与非门，插入元器件，选择PDK库（xxxx35dg_XxXx）中的nmos_3p3、 pmos_3p3等器件。形成如下电路图，然后check and save，如下图。 图1.二输入与非门的电路图 5.制作二输入与非门的外观symbol Design->Create Cellview -> From Cellview，在弹出的界面，按ok后出现symbol Generation options，选择端口排放顺序和外观，然后按ok出现symbol编辑界面。按照需 要编辑成想要的符号外观，如下图。保存退出。
图2.与非门外观 6.建立仿真电路图 方法和前面的“建立schemtic view”的方法一样，但在调用单元时除了调用analogL 库中的电压源、（正弦）信号源等之外，将之前完成的二输入与非门调用到电路图中，如下图。 图3.仿真电路图 然后设置激励源电压输出信号为高电平为3.5v，低电平为0的方波信号。 7.启动仿真环境 在ADE中设置仿真器、仿真数据存放路径和工艺库，设置好后选择好要检测的信号在电路中的节点，添加到输出栏中，运行仿真得到仿真结果图。
1、1将下列各式写成按权展开式: (352、6)10=3×102+5×101+2×100+6×10-1 (101、101)2=1×22+1×20+1×2-1+1×2-3 (54、6)8=5×81+54×80+6×8-1 (13A、4F)16=1×162+3×161+10×160+4×16-1+15×16-2 1、2按十进制0~17的次序,列表填写出相应的二进制、八进制、十六进制数。 解:略 1、3二进制数00000000~11111111与0000000000~1111111111分别可以代表多少个数？解:分别代表28=256与210=1024个数。 1、4将下列个数分别转换成十进制数:(1111101000)2,(1750)8,(3E8)16 解:(1111101000)2=(1000)10 (1750)8=(1000)10 (3E8)16=(1000)10 1、5将下列各数分别转换为二进制数:(210)8,(136)10,(88)16 解:结果都为:(10001000)2 1、6将下列个数分别转换成八进制数:(111111)2,(63)10,(3F)16 解:结果都为(77)8 1、7将下列个数分别转换成十六进制数:(11111111)2,(377)8,(255)10 解:结果都为(FF)16 1、8转换下列各数,要求转换后保持原精度: 解:(1、125)10=(1、0010000000)10——小数点后至少取10位 (0010 1011 0010)2421BCD=(11111100)2 (0110、1010)余3循环BCD码=(1、1110)2 1、9用下列代码表示(123)10,(1011、01)2: 解:(1)8421BCD码: (123)10=(0001 0010 0011)8421BCD (1011、01)2=(11、25)10=(0001 0001、0010 0101)8421BCD (2)余3 BCD码 (123)10=(0100 0101 0110)余3BCD (1011、01)2=(11、25)10=(0100 0100、0101 1000)余3BCD 1、10已知A=(1011010)2,B=(101111)2,C=(1010100)2,D=(110)2 （1）按二进制运算规律求A+B,A-B,C×D,C÷D, （2）将A、B、C、D转换成十进制数后,求A+B,A-B,C×D,C÷D,并将结果与(1)进行比较。解:(1)A+B=(10001001)2=(137)10 A-B=(101011)2=(43)10 C×D=(111111000)2=(504)10 C÷D=(1110)2=(14)10 (2)A+B=(90)10+(47)10=(137)10 A-B=(90)10-(47)10=(43)10 C×D=(84)10×(6)10=(504)10 C÷D=(84)10÷(6)10=(14)10 两种算法结果相同。 1、11试用8421BCD码完成下列十进制数的运算。 解:(1)5+8=(0101)8421BCD+(1000)8421BCD=1101 +0110=(1 0110)8421BCD=13
一、选择题 1. 以下表达式中符合逻辑运算法则的是 D 。 A.C ·C=C 2 B.1+1=10 C.0<1 D.A+1=1 2. 一位十六进制数可以用 C 位二进制数来表示。 A . １ B . ２ C . ４ D . 16 3. 当逻辑函数有n 个变量时，共有 D 个变量取值组合？ A. n B. 2n C. n 2 D. 2n 4. 逻辑函数的表示方法中具有唯一性的是 A 。 A .真值表 B.表达式 C.逻辑图 D.状态图 5. 在一个8位的存储单元中，能够存储的最大无符号整数是 D 。 A .（256）10 B .（127）10 C .（128）10 D .（255）10 6.逻辑函数F=B A A ⊕⊕)( = A 。 A.B B.A C.B A ⊕ D. B A ⊕ 7．求一个逻辑函数F 的对偶式，不可将F 中的 B 。 A .“·”换成“+”，“+”换成“·” B.原变量换成反变量，反变量换成原变量 C.变量不变 D.常数中“0”换成“1”，“1”换成“0” 8．A+BC= C 。 A .A+ B B.A+ C C.（A+B ）（A+C ） D.B+C 9．在何种输入情况下，“与非”运算的结果是逻辑0。 D A ．全部输入是0 B.任一输入是0 C.仅一输入是0 D.全部输入是1 10．在何种输入情况下，“或非”运算的结果是逻辑1。 A A ．全部输入是0 B.全部输入是1 C.任一输入为0，其他输入为1 D.任一输入为1 11．十进制数25用8421BCD 码表示为 B 。 A .10 101 B .0010 0101 C .100101 D .10101 12．不与十进制数（53.5）10等值的数或代码为 C 。 A .(0101 0011.0101)8421BCD B .(35.8)16 C .(110101.11)2 D .(65.4)8 13．以下参数不是矩形脉冲信号的参数 D 。 A.周期 B.占空比 C.脉宽 D.扫描期 14．与八进制数(47.3)
班级：通信二班姓名：赵庆超学号：20071201297 7，版图设计中整体布局有哪些注意事项？ 答：1版图设计最基本满足版图设计准则，以提高电路的匹配性能，抗干扰性能和高频工作性能。 2 整体力求层次化设计，即按功能将版图划分为若干子单元，每个子单元又可能包含若干子单元，从最小的子单元进行设计，这些子单元又被调用完成较大单元的设计，这种方法大大减少了设计和修改的工作量，且结构严谨，层次清晰。 3 图形应尽量简洁，避免不必要的多边形，对连接在一起的同一层应尽量合并，这不仅可减小版图的数据存储量，而且版图一模了然。 4 在构思版图结构时，除要考虑版图所占的面积，输入和输出的合理分布，较小不必要的寄生效应外，还应力求版图与电路原理框图保持一致（必要时修改框图画法），并力求版图美观大方。 8，版图设计中元件布局布线方面有哪些注意事项？ 答：1 各不同布线层的性能各不相同，晶体管等效电阻应大大高于布线电阻。高速电路，电荷的分配效应会引起很多问题。 2 随器件尺寸的减小，线宽和线间距也在减小，多层布线层之间的介质层也在变薄，这将大大增加布线电阻和分布电阻。 3 电源线和地线应尽可能的避免用扩散区和多晶硅布线，特别是通过
较大电流的那部分电源线和地线。因此集成电路的版图设计电源线和地线多采用梳状布线，避免交叉，或者用多层金属工艺，提高设计布线的灵活性。 4 禁止在一条铝布线的长信号霞平行走过另一条用多晶硅或者扩散区布线的长信号线。因为长距离平行布线的两条信号线之间存在着较大的分布电容，一条信号线会在另一条信号线上产生较大的噪声，使电路不能正常工作。、 5 压点离开芯片内部图形的距离不应少于20um，以避免芯片键和时，因应力而造成电路损坏。
数字电路与逻辑设计1_3试卷和答案 一、填空（每空1分，共45分） 1．Gray码也称循环码，其最基本的特性是任何相邻的两组代码中，仅有一位数码不同，因而又叫单位距离码。 2．二进制数转换成十进制数的方法为：按权展开法。 3．十进制整数转换成二进制数的方法为：除2取余法，直到商为 0 止。4．十进制小数转换成二进制数的方法为：乘2取整法，乘积为0或精度已达到预定的要求时，运算便可结束。 5．反演规则：对于任意一个逻辑函数式F，如果将其表达式中所有的算符“·”换成“ + ”，“ + ”换成“·”，常量“0”换成“ 1 ”，“ 1 ”换成“0”，原变量换成反变量，反变量换成原变量，则所得到的结果就是。称为原函数F的反函数，或称为补函数 6．n个变量的最小项是n个变量的“与项”，其中每个变量都以原变量或反变量的形式出现一次。对于任何一个最小项，只有一组变量取值使它为 1 ，而变量的其余取值均使它为 0 。 7．n个变量的最大项是n个变量的“或项”，其中每一个变量都以原变量或反变量的形式出现一次。对于任何一个最大项，只有一组变量取值使它为 0 ，而变量的其余取值均使它为 1 。 8．卡诺图中由于变量取值的顺序按格雷码排列，任何几何位置相邻的两个最小项，在逻辑上都是相邻的。，保证了各相邻行(列)之间只有一个变量取值不同。 9．卡诺图化简逻辑函数方法：寻找必不可少的最大卡诺圈，留下圈没有变化的那些变量。求最简与或式时圈 1 、变量取值为0对应反变量、变量取值为1对应原变量；求最简或与式时圈 0 、变量取值为0对应原变量、变量取值为1对应反变量。 10．逻辑问题分为完全描述和非完全描述两种。如果对于输入变量的每一组取值，逻辑函数都有确定的值，则称这类函数为完全描述逻辑函数。如果对于输入变量的某些取值组合逻辑函数值不确定，即函数值可以为0，也可以为1(通常将函数值记为?或×)，那么这类函数称为非完全描述的逻辑函数。 11．数字集成电路按其部有源器件的不同可以分为两大类：双极型晶体管集成电路和MOS(Metal Oxide Semiconductor)集成电路。 12．TTL集成电路工作速度高、驱动能力强，但功耗大、集成度低； MOS 集成电路集成度高、静态功耗低。 13．按集成电路部包含的等效门个数可分为：小规模集成电路(SSI-Small Scale Integration)，中规模集成电路(MSI-Medium Scale Integration)，大规模集成电路(LSI-Large Scale Integration)，超大规模集成电路(VLSI-Very Large Scale Integration) 二、判断题（在括号中打×或√；每题3分，共15分） 1．集电极开路门和三态门是不允许输出端直接并联在一起的两种TTL门。（×）2.用集电极开路门可以构成线与逻辑。 ( √ ) 3．普通TTL门的输出只有两种状态——逻辑 0 和逻辑 1，这两种状态都是高阻输出。三态逻辑(TSL)输出门除了具有这两个状态外，还具有低阻输出的第三状态(或称禁止状态)，这时输出端相当于短路。(× ) 4．TTL电路和CMOS电路接口时，无论是用TTL电路驱动CMOS电路还是用CMOS电路驱动TTL 电路，驱动门都必须为负载门提供合乎标准的高、低电平和足够的电流（√）5．若F的对偶式为G；则G的对偶式为F。（√）
IC设计基础（流程、工艺、版图、器件）笔试集锦 1、我们公司的产品是集成电路，请描述一下你对集成电路的认识，列举一些与集成电路 相关的内容（如讲清楚模拟、数字、双极型、CMOS、MCU、RISC、CISC、DSP、ASIC、FPGA 等的概念）。（仕兰微面试题目） 什么是MCU？ MCU(Micro Controller Unit)，又称单片微型计算机(Single Chip Microcomputer)，简称单片机，是指随着大规模集成电路的出现及其发展，将计算机的CPU、RAM、ROM、定时数器和多种I/O接口集成在一片芯片上，形成芯片级的计算机。 MCU的分类 MCU按其存储器类型可分为MASK(掩模)ROM、OTP(一次性可编程)ROM、FLASH ROM等类型。MASK ROM的MCU价格便宜，但程序在出厂时已经固化，适合程序固定不变的应用场合；FALSH ROM的MCU程序可以反复擦写，灵活性很强，但价格较高，适合对价格不敏感的应用场合或做开发用途；OTP ROM的MCU价格介于前两者之间，同时又拥有一次性可编程能力，适合既要求一定灵活性，又要求低成本的应用场合，尤其是功能不断翻新、需要迅速量产的电子产品。 RISC为Reduced Instruction Set Computing的缩写，中文翻译为精简执令运算集，好处是CPU核心 很容易就能提升效能且消耗功率低，但程式撰写较为复杂；常见的RISC处理器如Mac的Power PC 系列。 CISC就是Complex Instruction Set Computing的缩写,中文翻译为复杂指令运算集,它只是CPU分类的一种,好处是CPU所提供能用的指令较多、程式撰写容易,常见80X86相容的CPU即是此类。 DSP有两个意思，既可以指数字信号处理这门理论，此时它是Digital Signal Processing的缩写；也可以是Digital Signal Processor的缩写，表示数字信号处理器，有时也缩写为DSPs，以示与理论的区别。 2、FPGA和ASIC的概念，他们的区别。（未知） 答案：FPGA是可编程ASIC。 ASIC:专用集成电路，它是面向专门用途的电路，专门为一个用户设计和制造的。根据一 个用户的特定要求，能以低研制成本，短、交货周期供货的全定制，半定制集成电路。与 门阵列等其它ASIC(Application Specific IC)相比，它们又具有设计开发周期短、设计 制造成本低、开发工具先进、标准产品无需测试、质量稳定以及可实时在线检验等优点 3、什么叫做OTP片、掩膜片，两者的区别何在？（仕兰微面试题目）otp是一次可编程（one time programme）,掩膜就是mcu出厂的时候程序已经固化到里面去了，不能在写程序进去！( 4、你知道的集成电路设计的表达方式有哪几种？（仕兰微面试题目） 5、描述你对集成电路设计流程的认识。（仕兰微面试题目） 6、简述FPGA等可编程逻辑器件设计流程。（仕兰微面试题目） 7、IC设计前端到后端的流程和eda工具。（未知） 8、从RTL synthesis到tape out之间的设计flow,并列出其中各步使用的tool.（未知） 9、Asic的design flow。（威盛VIA 2003.11.06 上海笔试试题） 10、写出asic前期设计的流程和相应的工具。（威盛） 11、集成电路前段设计流程，写出相关的工具。（扬智电子笔试） 先介绍下IC开发流程： 1.）代码输入（design input) 用vhdl或者是verilog语言来完成器件的功能描述，生成hdl代码 语言输入工具：SUMMIT VISUALHDL MENTOR RENIOR 图形输入: composer(cadence); viewlogic (viewdraw) 2.）电路仿真（circuit simulation) 将vhd代码进行先前逻辑仿真，验证功能描述是否正确 数字电路仿真工具： Verolog：CADENCE Verolig-XL SYNOPSYS VCS MENTOR Modle-sim VHDL : CADENCE NC-vhdl SYNOPSYS VSS MENTOR Modle-sim 模拟电路仿真工具： AVANTI HSpice pspice，spectre micro microwave: eesoft : hp 3.）逻辑综合（synthesis tools) 逻辑综合工具可以将设计思想vhd代码转化成对应一定工艺手段的门级电路；将初级仿真 中所没有考虑的门沿（gates delay）反标到生成的门级网表中,返回电路仿真阶段进行再 仿真。最终仿真结果生成的网表称为物理网表。 12、请简述一下设计后端的整个流程？（仕兰微面试题目） 13、是否接触过自动布局布线？请说出一两种工具软件。自动布局布线需要哪些基本元 素？（仕兰微面试题目） 14、描述你对集成电路工艺的认识。（仕兰微面试题目）
数字电路与逻辑设计复习资料 一、单项选择题 1. 十进制数53转换成八进制数应为（ B ）。 A. 64 B.65 C. 66 D. 110101 2.将十进制数(18)10 转换成八进制数是（B ）。 A. 20 B.22 C. 21 D. 23 3. 十进制数53转换成八进制数应为（ D ）。 A. 62 B.63 C. 64 D. 65 4. 当逻辑函数有n 个变量时，共有（ D ）种取值组合。 A. n B. 2n C. 2n D. 2n 5. 为了避免干扰，MOS 与门的多余输入端不能（ A ）处理。 A. 悬空 B. 接低电平 C. 与有用输入端并接 D. 以上都不正确 6. 以下电路中可以实现“线与”功能的有（ C ）。 A. TTL 与非门 B. TTL 或非门 C. OC 门 D. TTL 异或门 7. 用6264型RAM 构成一个328K ?位的存储器，需要（ D ）根地址线。 A. 12 B. 13 C. 14 D. 15 8. 同步时序电路和异步时序电路比较，其差异在于后者（ B ）。 A. 没有触发器 B. 没有统一的时钟脉冲控制 C. 没有稳定状态 D. 输出只与内部状态有关 9. 用6264型RAM 构成3232K ?位的存储器，需要（ D ）片进行扩展。 A. 4 B.8 C. 14 D.16 10. 逻辑函数()F A A B =⊕⊕ =（ D ）。 A. A B e B. A C. A B ⊕ D. B 11. 函数F ABC ABCD =+的反函数为（ C ）。 A. ()()F A B C A B C D =+++++ B. ()()F ABC ABCD =
集成电路设计基础复习要点 第一章集成电路设计概述 1、哪一年在哪儿发明了晶体管？发明人哪一年获得了诺贝尔奖？ 2、世界上第一片集成电路是哪一年在哪儿制造出来的？发明人哪一 年为此获得诺贝尔奖？ 3、什么是晶圆？晶圆的材料是什么？ 4、晶圆的度量单位是什么？当前主流晶圆尺寸是多少？目前最大晶 圆尺寸是多少？ 5、摩尔是哪个公司的创始人？什么是摩尔定律？ 6、什么是SoC？英文全拼是什么？ 7、说出Foundry、Fabless和Chipless的中文含义。 8、什么是集成电路的一体化(IDM)实现模式？ 9、什么是集成电路的无生产线(Fabless)设计模式？ 10、目前集成电路技术发展的一个重要特征是什么？ 11、一个工艺设计文件(PDK)包含哪些内容？ 12、什么叫“流片”？ 13、什么叫多项目晶圆(MPW) ？MPW英文全拼是什么？ 14、集成电路设计需要哪些知识范围？ 15、著名的集成电路分析程序是什么？有哪些著名公司开发了集成电 路设计工具？
16、SSI、MSI、LSI、VLSI、ULDI的中文含义是什么？英文全拼是 什么？每个对应产品芯片上大约有多少晶体管数目？ 17、国内近几年成立的集成电路代工厂家或转向为代工的厂家主要有 哪些？ 18、境外主要代工厂家和主导工艺有哪些？ 第二章集成电路材料、结构与理论 1、电子系统特别是微电子系统应用的材料有哪些？ 2、常用的半导体材料有哪些？ 3、半导体材料得到广泛应用的原因是什么？ 4、为什么市场上90%的IC产品都是基于Si工艺的？ 5、砷化镓(GaAs) 和其它III/V族化合物器件的主要特点是什么？ 6、GaAs晶体管最高工作频率f T可达多少？最快的Si晶体管能达到多 少？ 7、GaAs集成电路主要有几种有源器件？ 8、为什么说InP适合做发光器件和OEIC？ 9、IC系统中常用的几种绝缘材料是什么？ 10、什么是欧姆接触和肖特基接触？ 11、多晶硅有什么特点？ 12、什么是材料系统？