安捷伦 信号完整性分析 PPT

5

5.接收性能测试分析2

3

PCI-E 1/2/3、RapidIO

PCI-E 1/2/3

AGP x8

DDR2/3、FBD

10/100 Ethernet

Gig Ethernet

10 Gig E

SCSI SAS1/2Fiber Channel

SAS1/2SATA2/3

SATA

4

’97 ’98 ’99 ‘00 ’01 ’02 ’03 ’

Parallel Serial

Proprietary

IBA

Datacenter Clusters

10 Gig E

所有的I/O 总线都向串行发展

数据速率越来越快（>1Gbps）

上升时间越来越快

反射越来越大5

要在频域进行数据的分析

6

+5 Volt

Supply

Ground

+5 Volt

Supply

Ground

7

。。。。。。?过孔；

8?电磁辐射；

?。。。。。。

可见，信号完整性设计的考虑因素是多方面的，设计中应把握主要方面，减少不确定性。

9 10

典型信号完整性现象3：串行信号眼图问题

原因很多：

阻抗不连续，损耗

阻抗不连续，损耗 (11)

眼图概念

12

串行数据的软件时钟恢复方式

13

8参考: Bell Communications Research, Inc (Bellcore), “Synchrouous Optical Network (SONET) Transport Systems: Common Generic Criteria, TR-253-CORE”, Issue 2, Rev No. 1, December

1997

14

15?热噪声(RJ)

?占空比失真(DCD)

?电源噪声(RJ, PJ)

?芯片内部耦合(PJ, ISI)

?匹配错误(ISI)另外一个含义是指数字信号的上升与下降（或称信号的跳变）非常之快

16，当信号的上升时间小于6倍（有说4倍）信号传输延时（电长度）时即认为信号是高速信号，而与信号的频率无关。

t rise

17

安捷伦信号完整性测试分析全套解决方案18

Receiver M tl b V il A

20

Card

Package

?Matlab, Verilog_A

结果测量

?TDR and TDT

?2-port and 4-port VNA

?Eye Diagram

?Advanced Jitter

Decoder Receiver

Equalizer

Signal Recovery

建模——传输线

Account for impedance, delay, conductor loss, dielectric loss, and coupling

Multilayer Interconnect Models use a built-in field-solver, and have both layout and schematic representations

Momentum EM simulator for arbitrary planar structures. Has layout and schematic representations

Analytic models are fast,

and have a layout and

schematic representation

21

?2D Via model vertical current

?3D Via model vertical and horizontal currents ?Advanced Slot Via modeling

22

频域通道仿真

?S-Parameter Measurements

?Z-Parameters Measurements

?Y-Parameter Measurements

?Group Delay

23Monte Carlo Simulation Dielectric Constant variation (10%) High Frequency Response Degradation Rise/Fall Performance is Effected

TDR/TDT仿真24

I/O驱动+ 互连仿真

For illustration purpose we used Virtex-II Pro I/O simulation in this example

25

Allegro PCB Design Environment ADS design and simulation environment 26

2D/3D电磁场仿真

isolated trace

port 1 port 2harmonic signal 0.4 GHz

output

27

S(1,1)

isolated trace

S(1,2)

isolated trace 仿真结果查看——眼图和模板

28

081000

1E-31

29

-400-2000200400

-600600

0.2

0.4

0.6

0.8

0.0

Time, fsec

D

D

J

H

i

s

t

D

D

J

F

H

i

s

t

D

D

J

R

H

i

s

t

-6-4-20246

-88

200

400

600

800

Time, psec

T

J

H

i

s

t

R

J

P

J

H

i

s

t

D

D

J

H

i

s

t

0.20.40.60.8

0.0 1.0

UI

30

8参考: Bell Communications Research, Inc (Bellcore), “Synchrouous Optical Network (SONET) Transport Systems: Common Generic Criteria, TR-253-CORE”, Issue 2, Rev No. 1, December

1997

31

32

Periodic

Jitter (PJ)

Data Dependent

Jitter (DDJ)

Inter-symbol

Interference (ISI)

Duty Cycle

Distortion (DCD)

Sub Rate Jitter

(SRJ)

Uncorrelated

PJ

33

?热噪声(RJ)

?占空比失真(DCD)

?电源噪声(RJ, PJ)

?芯片内部耦合(PJ, ISI)

?匹配错误(ISI) 86100C 一键式抖动测试和分析

34

EZJIT+：基本抖动分析

Signal

Trend

Histogram

Spectrum 35

EZJIT+：高级抖动分析

36

s

37

75

050100150200250

Actual TJ (ps)

F

a

数字信号的眼图

38

眼图模板

39

串行数据的时钟恢复方式40