SR1018 – GSM/GPRS/EDGE Transceiver The Spreadtrum SR1018 is a single-chip radio transceiver for quad-band GSM/GPRS/EDGE cellular applications. The SR1018 has been implemented in bulk CMOS and the design has been optimized to meet the challenges of integrated handset design.
The performance of the transmit chain requires no additional RF filters to meet the specification for out-of-band emissions. The SR1018 exceeds all ETSI radio design requirements and its enhanced transmit architecture permits the rapid design of stable, high performance handsets only requiring a single radio shield.
SR1018 Functional Block Diagram
SR1018 Product Feature Summary
●Transceiver Functions
○Integrated radio transceiver fully supporting GSM, GPRS and EGPRS
○GPRS and E-GPRS class 12 supported
○True quad-band GSM operation (USGSM850, EGSM900, DCS1800, PCS1900)
○Direct LO modulator in GMSK mode
●General Features
○Mixed signal interface to a cellular base band
○Digital tuning of reference crystal
○ 2.7V to 3.3V single supply range
○-40°C to +85°C operation
Table 1: Absolute Maximum Ratings
Parameter Min Max Unit Supply voltage (VDD pins) 3.6 V
Ambient operating temperature -40 85 °C
Storage temperature -50 125 °C
Total power dissipation 475 mW
Input voltage range, any pin GND VDD V
ESD, MM 100 V
ESD, CDM 500 V
ESD, HBM (Digital interface pins) 2 kV
ESD, HBM (All other pins) 1 kV
Note: Stresses above these absolute maximum ratings may cause permanent damage.
These are stress ratings only and functional operation at these conditions is not implied.
Exposure to maximum rating conditions for extended periods may reduce device reliability.
Spreadtrum believes the furnished information is correct and accurate at the time of this printing.
However, Spreadtrum Communications reserves the right to make changes to its products without notice.
Spreadtrum Communications does not assume responsibility for the use of the described product(s).
Table 2: Operating Conditions
Parameter Min Typ Max Unit Condition
Operating Range
Supply voltage (all VDD pins) 2.7 2.8 3.3 V
Operating ambient temperature -40 25 85 °C
Storage temperature -50 125 °C
Table 3: Supply Current
All VDD pins = 2.8V, T ambient = 25°C, unless otherwise noted
Parameter Min Typ Max Unit Condition
Total Supply Current
Total receive Reg 0x00[11:0]=0x7CF
USGSM850, EGSM900 65 75 mA
DCS1800, PCS1900 65 75 mA
Total transmit Reg 0x00[11:0]=0x0FF
Low Band 120 136 mA
High Band 106 127 mA
Low power modes VDD DIG/IO=2.8V, REF2 EN=0
Idle mode 3.5 5.5 mA DCXO is on
Doze mode 14 30 μA DCXO is off
Isolated Supply Currents
Receive mode Reg 0x00[11:0]=0x7CF
VDD1 33 38 mA RF IC circuitry positive supply
VDD2 27 30 mA Synthesizer and BB circuitry positive supply VDD DIG IO 5 7 mA DCXO, Digital, and RCB positive supply Transmit mode Reg 0x00[11:0]=0x0FF
VDD1 83 90 mA RF IC circuitry positive supply
VDD2 24 29 mA Synthesizer and BB circuitry positive supply VDD DIG IO 13 17 mA DCXO, Digital, and RCB positive supply Interface only
VDD DIG IO 3.5 5.5 mA DCXO, Digital, and RCB positive supply
Table 4: DC Parameters
All VDD pins = 2.8V, T ambient = 25°C, unless otherwise noted
These parameters are not tested in mass production
Parameter Min Typ Max Unit Condition
Baseband Analog Ports ? RX Output Pins 15-18
Output common mode
DC level 8/25 x VDD 12/25 x VDD 16/25 x VDD V
DC resolution 1/25 x VDD 1/25 x VDD mV / LSB
Current load -100 0 +100 μA
Source resistance 500 1000 Ω (se)
Differential load impedance
Resistive 3 20 kΩ (dif)
Reactive 1 15 pF (dif)
'Off' resistance
Differential 20 24 kΩ (dif)
Common mode 100 120 kΩ
Baseband Analog Ports ? TX Input Pins 15-18
Input common mode 1.26 1.4 1.54 V
Input voltage range GND + 350mV VDD ÷ 2 VDD - 350mV
Input impedance
Resistive 10 12 kΩ (dif)
Reactive 1 2 pF (dif)
'Off' resistance
Differential 20 24 kΩ (dif)
Common mode 100 120 kΩ
Digital DC Parameters ? RCB Port Pins 21-23
Logic levels
Input logic low 0 0.1 0.5 V
Input logic high 1.45 1.8 VDD + 0.2 V
Input current 0.001 0.5 μA
"TEMP OUT" Output Pin 4
Absolute accuracy -3 3 °C
Voltage output (VTEMP)
T DIE = -40?C 57 83 109 mV
T DIE = +25?C 947 973 999 mV
T DIE = +85?C 1772 1798 1824 mV
Source resistance 900 1200 Ω
Current consumption 0.8 1 mA Drawn from "VDD2"
Temperature equation Temp=0.0695*m-45.326 m=temp sensor reading
in mV
Table 5: AC Parameters: RF Input Ports
All VDD pins = 2.8V, T ambient = -40°C to +85°C, unless otherwise noted
Measured in a 50Ω impedance system, including external balun (~1dB IL) and required matching components unless otherwise noted
Parameter Min Typ Max Unit Condition
RF Input Ports
USGSM850 869 894 MHz
EGSM900 925 960 MHz
DCS1800 1805 1880 MHz
PCS1900 1930 1990 MHz
Characteristic input impedance
USGSM850 150 || 1 Ω || pF
EGSM900 150 || 1 Ω || pF
DCS1800 150 || 1 Ω || pF
PCS1900 150 || 1 Ω || pF
Table 6: GSM Receiver RF Specifications
All VDD pins = 2.8V, T ambient = -40°C to +85°C, unless otherwise noted
Parameter Min Typ Max Unit Condition
Cascaded noise figure @ 25°C Reg 0x00[11:0]=0x7CF
USGSM850 2.5 3 dB
EGSM900 2.5 3 dB Excludes SAW/PCB losses (~1.5dB)
DCS1800 2.5 3 dB
PCS1900 2.5 3 dB
Maximum cascaded voltage gain Reg 0x00[11:0]=0x7CF
USGSM850 91 94 97 dB
EGSM900 91 94 97 dB
DCS1800 91 94 97 dB
PCS1900 91 94 97 dB
Minimum cascaded voltage gain Reg 0x00[11:0]=0x141
USGSM850 11 14 17 dB
EGSM900 11 14 17 dB
DCS1800 5 9 12 dB
PCS1900 5 9 12 dB
Baseband step Minimum step size ±0.75 ±1 ±1.25 dB
Cascaded gain control linearity
Integrated -0.5 0 0.5 dB
Differential Over any 20dB step -0.5 0 0.5 dB
Differential Over any 2dB step -0.5 0 0.5 dB
Table 7: RF Front End
All VDD pins = 2.8V, T ambient = -40°C to +85°C, unless otherwise noted
Parameter Min Typ Max Unit Condition
RF front end voltage gain (high gain) Reg 0x00[10]=1
USGSM850 3.5 4 4.5 dB
EGSM900 3.5 4 4.5 dB
DCS1800 3.5 4 4.5 dB
PCS1900 3.5 4 4.5 dB
RF front end voltage gain (low gain) Reg 0x00[10]=0
USGSM850 -23.5 -23 -22.5 dB
EGSM900 -23.5 -23 -22.5 dB
DCS1800 -26.5 -26 -25.5 dB
PCS1900 -26.5 -26 -25.5 dB
Input P1dB high gain Reg 0x00[11:0]=0x770
USGSM850 -18 dBm
EGSM900 -18 dBm
DCS1800 -18 dBm
PCS1900 -18 dBm
Input P1dB low gain Reg 0x00[11:0]=0x141
USGSM850 -8 dBm
EGSM900 -8 dBm
DCS1800 -8 dBm
PCS1900 -8 dBm
Input IP3 Reg 0x00[11:0]=0x770
USGSM850 -12 dBm
EGSM900 -12 dBm
DCS1800 -12 dBm
PCS1900 -12 dBm
Input IP2 Reg 0x00[11:0]=0x770
USGSM850 40 44 dBm
EGSM900 40 44 dBm
DCS1800 40 44 dBm
PCS1900 40 44 dBm
Image rejection Reg 0x00[11:0]=0x7CF
USGSM850 40 48 dB
EGSM900 40 48 dB
DCS1800 40 48 dB
PCS1900 40 48 dB
Quadrature gain mismatch -0.5 0 0.5 dB
Table 8: TX Specification
All VDD pins = 2.8V, T ambient = -40°C to +85°C, unless otherwise noted
Parameter Min Typ Max Unit Condition
TX Baseband Input Ports
Input signal level voltage swing 0.5 1 2 Vpp (dif)
Differential input offset voltage 16 32 63 mV
Table 9: GSM Transmitter RF Modulation Specification
All VDD pins = 2.8V, T ambient = -40°C to +85°C, unless otherwise noted
Parameter Min Typ Max Unit Condition
TX RF Output Ports
RF output frequency Reg 0x00[11:0]=0x0FF
USGSM850 824 849 MHz
EGSM900 880 915 MHz
DCS1800 1710 1785 MHz
PCS1900 1850 1910 MHz
GMSK programmable output power Reg 0x00[11:0]=0x0FF
USGSM/EGSM port -2 0 6 dBm
DCS/PCS port -2 0 6 dBm
GMSK saturated output power Reg 0x00[11:0]=0x0FF
USGSM/EGSM port 6 7 dBm
DCS/PCS port 6 7 dBm
8PSK maximum output power
USGSM/EGSM port -2 0 2 dBm RF attenuator set to 0dB
DCS/PCS port -2 0 2 dBm RF attenuator set to 0dB 8PSK minimum output power
USGSM/EGSM port -46 -44 -42 dBm RF attenuator set to 44dB
DCS/PCS port -46 -44 -42 dBm RF attenuator set to 44dB 8PSK RF Attenuator
Total attenuation range 0 25 45
Attenuator step size 0.4 0.5 0.6
Differential attenuation accuracy -0.25 0 0.25
Integrated attenuation accuracy -0.3 0 0.4
Output power variation Reg 0x00[11:0]=0x0FF
USGSM/EGSM port -2 0 2 dB
DCS/PCS port -2 0 2 dB
Table 10: GSM Transmitter RF Modulation Specification (Part 2)
All VDD pins = 2.8V, T ambient = -40°C to +85°C, unless otherwise noted
Parameter Min Typ Max Unit Condition
TX Modulated
RMS phase error Reg 0x00[11:0]=0x0FF
USGSM850 1 1.5 ?
EGSM900 1 1.5 ?
DCS1800 1.5 2 ?
PCS1900 1.5 2 ?
Peak phase error Reg 0x00[11:0]=0x0FF
USGSM850 4 6 ?
EGSM900 4 6 ?
DCS1800 5 8 ?
PCS1900 5 8 ?
RF modulation spectrum (GMSK) Reg 0x00[11:0]=0x0FF USGSM850 band fc ± 400kHz -67 -63 dBc
EGSM900 band fc ± 400kHz -67 -63 dBc
DCS1900 band fc ± 400kHz -65 -63 dBc
PCS1900 band fc ± 400kHz -65 -63 dBc
RMS error vector magnitude
USGSM850 2.5 4 %
EGSM900 2.5 4 %
DCS1800 2.5 6 %
PCS1900 2.5 6 %
Peak error vector magnitude
USGSM850 4 10 %
EGSM900 4 10 %
DCS1800 5 10 %
PCS1900 5 10 %
RF modulation spectrum (8PSK)
USGSM850 band fc ± 400kHz -63 -60 dBc
EGSM900 band fc ± 400kHz -63 -60 dBc
DCS1900 band fc ± 400kHz -63 -60 dBc
PCS1900 band fc ± 400kHz -63 -60 dBc
USGSM850 band fc ± 600kHz -70 -65 dBc
EGSM900 band fc ± 600kHz -70 -65 dBc
DCS1900 band fc ± 600kHz -69 -65 dBc
PCS1900 band fc ± 600kHz -69 -65 dBc
Output harmonics level Reg 0x00[11:0]=0x0FF
USGSM/EGSM 2 x fc -26 -20 dBc
USGSM/EGSM 3 x fc -16 -10 dBc
DCS/PCS 2 x fc -26 -20 dBc
DCS/PCS 3 x fc -26 -20 dBc
Output load Impedance 50 Ω
Table 11: LO Synthesizer Specification
All VDD pins = 2.8V, T ambient = -40°C to +85°C, unless otherwise noted
Parameter Min Typ Max Unit Condition
LO Synthesizer
Lock time
Receive mode 100 150 μs Settling to within 0.1ppm of target frequency referenced Transmit mode 100 150 μs
Synthesizer frequency range 3292 3600 3984 MHz VCO frequency
Spurious levels -74 -71 dBc Foffset > 400kHz
Table 12: DCXO Specification
All VDD pins = 2.8V, T ambient = -40°C to +85°C, unless otherwise noted
Parameter Min Typ Max Unit Condition
DCXO Reference Configuration (Crystal Reference, "REF IN-" & "REF IN+" Ports) Pins 25 & 26
Capacitive step size (coarse)
Reg 0x3A[3:0] = 0000 3 pF
Reg 0x3A[3:0] = 0001 2.8 pF
: : pF
Reg 0x3A[3:0] = 1111 0 pF
Capacitive tuning range (fine tuning)
Reg0x39[13:0] = 0x3FFF 3.9 4 4.4 pF
Reg0x39[13:0] = 0x0000 7.35 7.65 8.05 pF
Capacitive step size (fine) 0.21 0.22 0.24 fF/LSB
Oscillation startup
Input resistance -1000 -450 -150 Ω
Transconductance 9.5 mS
Nominal voltage swing
"REF IN+" terminal 1.35 1.8 Vpp
"REF IN-" terminal 1.36 1.6 Vpp
Reference Crystal Requirements
Frequency tolerance -10 0 10 ppm
Temperature stability -10 0 10 ppm –20?C < T ambient < +85?C
Aging -1 0 1 ppm/year
Drive level 100 200 μW
Pulling sensitivity 14 25 ppm/pF
Load capacitance (CL) 6.5 8 9 pF No external capacitor required.
Use coarse setting to adjust for crystal
CL value
Motional series resistance (RS) 20 60 Ω
TCXO Reference Configuration (External Reference, "REF IN+" Port) Pin 26
Input coupling requirement AC
Input impedance
Resistive 12 15 kΩ
Reactive 8 10 pF
Input voltage swing 650 1000 mVpp
Input duty cycle 40 50 60 %
Phase noise
1kHz offset -132 -129 dBc/Hz
Table 13: Reference Output Specification
All VDD pins = 2.8V, T ambient = -40°C to +85°C, unless otherwise noted
Parameter
Min Typ Max Unit Condition
Reference Clock Output Pins 27 & 28 Reference frequency
26 MHz Frequency compensation range ±27 ±40 ppm Frequency compensation resolution 0.005 0.02 ppm/LSB
Output duty cycle 40 50 60 % Amplitude (Ref Out)
Note:
For Ref2 Out control, the register location is x38[9:8] Reg0x38[13:12] = 11 1200 mVpp Reg0x38[13:12] = 10 950 mVpp Reg0x38[13:12] = 01 750 mVpp Reg0x38[13:12] = 00
600 mVpp Clock jitter 10 20 ps rms Drive capacity
10 pF Power-up settling time
2
3
ms
Functional Description:
Overview
The SR1018 is an integrated solution for multi-band GSM/GPRS/EDGE applications. It integrates a complete quad-band wireless receiver, transmitter, and a fractional-N frequency synthesizer including the voltage controlled oscillator (VCO) and loop filter. The RF portion of the receiver consists of a four band integrated Low Noise Amplifier (LNA) and a quadrature down-converter. The receive chain is fully differential resulting in improved noise rejection during operation. The receive channel filter is implemented in an RX filter strip. It comprises a blocker-reject low-pass channel filter (LPF) and two digitally controlled variable gain amplifiers (VGA).
crystal
operation
The RX blockers.
In order to minimize the set-up of the SR1018, extensive on-chip automatic calibration has been implemented. All DC offsets are automatically calibrated out. Internal DC calibration ensures that externally generated DC offsets do not overload the receive chain. An on-chip state machine generates the timing control signals for this DC calibration and the calibration routine is initiated via the RCB. In normal operation the state machine is started, the RX filter strip is powered up and any inherent DC offsets are removed. These correction signals are then held constant as the RF front end is powered up for the receive chain to process the incoming signal. None of these calibrations require any interaction with the baseband sub-system.
Transmit Chain
Figure 2: SR1018 Transmit Chain
For
For
Frequency Sources
There are two frequency sources on the SR1018. The first is the RF frequency synthesizer, which serves as the LO for both receive and transmit chains. The VCO for the synthesizer is fully integrated and no calibration is required as this is all performed automatically on the SR1018. During reception or transmission in normal operation, the frequency synthesizer is operated at twice the desired frequency of operation in PCS and DCS modes and at four times the desired frequency of operation in EGSM and USGSM modes. On-chip dividers (÷2 for PCS/DCS and ÷4 EGSM/USGSM) then reduce to actual the frequency of the operation. The outputs of these dividers are buffered before being applied to the up or down converters. The loop filter of the frequency synthesizer is fully integrated. This reduced component count and form factor minimizes the number of sensitive components in the design.
crystal continues
output is
Radio Configuration Bus (RCB)
A radio configuration bus is used to control the various modes of operation within the SR1018. This bus is implemented as a 3-wire serial interface. The signals are Data, Clock and Latch Enable (DATA, CLK, and LE). Power must be applied to the SR1018 to program the registers but none of the radio circuitry needs to be active. This minimizes current consumption and also allows pre-programming during normal operation to minimize clock interference.
Figure 4: RCB Format
Figure 5: SR1018 Radio Configuration Bus Timing
Figure 6: RCB Clock Rising & Falling Edges
(T amb = 25°C, All VDD = 2.8V, unless otherwise noted)
Parameter
Description Min Typ Max Unit t RISE CLK rise time 100 ns t FALL
CLK fall time
100
ns
(T amb = 25o
C, All VDD = 2.8V, unless otherwise noted)
Parameter Description Min Typ Max Unit F CLK CLK Frequency 5 26 80 MHz t CPH CLK pulse high 5 ns t CPL CLK pulse low
5 ns t CLH CLK low period before rising edge
5 ns t LC LE to CLK setup
5 ns t LCS LE rising edge past CLK rising edge
10 ns t LPH Latch pulse high
5 ns T DCRS DATA to CLK rising edge setup 5 ns T DCRH
DATA pas CLK rising edge hold
5
ns
Package Options:
There are four types of packages, all are compatible with each. The only difference is the “pin 1” marking. Please note each package type and its pin 1 marking.
Figure 7: SR1018 28-pin QFN package (Option 1)
Figure 8 SR1018 28-pin QFN package (Option 2)