UTMI+ULPI

基于FPGA的U盘主控架构与验证设计毕业论文基于FPGA的U盘主控架构与验证设计院 (系):电子与信息工程学院专业年级:08级电子信息科学与技术姓名: 学号:80514073 指导老师:讲师 2012年5月13日基于FPGA的U盘主控架构与验证设计摘要随着市场对U盘的需求越来越大,价格与功能成为各生产商的竞争主力。

对于单价差异不大的U盘,消费者往往更关心的是功能的多元性。

因此,如何让U盘控制器更具兼容性与扩展性,已成为当前各主控厂商最关注的问题。

然而由于商业技术保密,加上研发人员对该领域很少问津等原因,导致U盘的性能难以得到快速更新。

本文从U盘的核心出发,深入研究主控制器芯片内部结构与设计方案。

通过研究分析,该结构主要由USB收发器、USB串行引擎、8位/16位专用处理器、FIFO控制器、NAND FLASH与ECC控制器组成。

本文重点讲述专用处理器的架构与设计流程,根据计算机内存管理机制和任务调度机制,基于FPGA 设计ASIC的方法,实现数字前端设计,并在USB2.0开发套件EP1C6Q240N+CY7C68013上得到验证。

关键词:,FPGA,U盘主控,ASIC,专用处理器,USB,NAND FLASHmaseter of architercture and verification of design based on FPGA UdiskAbstractwith the growing market demand for U disk,the price and function asthe main competition of the manufacturers,U disk unit price difference is small consumers are oftern more concerned with the diversity of functions.Therefore,how to make aUdisk controller more compatibility and scalability,has become the greatest concern of the current master manufacturers.However,due to the confidentiality of commercial technology,coupled with R&D personnel in this area rarely cares and other reasons,leading to U disk erformance is difficult to get quick updates.Deparature from the core of the U disk,in-depth study of the internal structure and design of the main controller chip.Through research amd analysis of the structure by the USB transceiver,USB serial engine,8/16 a dedicated processor ,FIFO controller,NAND Flash ECC controller composition.KEY words;FPGA,Udisk master,ASIC,dedicated processor,USB,nand flash摘要 21 U盘 41.1 U盘概要 41.2 U盘主控方案 51.3 FLASH晶片类型 52 协议概要 52.1 ULPI协议 52.1.1 ULPI主要功能及原理 62.1.2工作模式82.1.3 UMTI+特性82.1.4 传输与接收命令92.2 USB Mass storage协议102.2.1命令块数据包(CBW) 102.2.2命令状态包(CSW) 122.2.3 19种指令132.2.4 U盘初始化流程命令: 143 U盘系统架构153.1系统架构对比15由于USB接口流程复杂,且涉及很多电气规范,本文则不讨论XCVR和SIE。

UTMI+ Low Pin Interface (ULPI)SpecificationRevision 1.1October 20, 2004Revision HistoryDate CommentRevision Issue0.9 November 12, 2003 Pre-release.1.0rc1 January 3, 2004 Introduce PHY interface “modes”.Update interface timings. Clarify 4-bit data clocking.Clarify sending of RX CMD’s and interrupts.Introduce AutoResume feature.Route int pin to data(3) during 6-pin Serial Mode.Explain VBUS thresholds.Add T&MT diagram and updated text.Add new section to explain how PHY is aborted by Link.Various clarifications.1.0rc2 January 13, 2004 Add block diagram.Tighten interface timing.Modify suspend protocol to more closely resemble UTMI.Add SPKR_L and SPKR_MIC to signal list and T&MTconnector.Various clarifications.1.0rc3 January 19, 2004 Specify that PHY must send RX CMD after Reset.Link + PHY clock startup time of no more than 5.6ms for aperipheral is now mandatory.PHY output delay reduced from 10ns to 9ns.Added link decision time numbers for low speed.Various Clarifications.1.0 February 2, 2004 1.0rc3 adopted as 1.0 release.1.1rc1 September 1, 2004 Various clarifications and fixes to hold time numbers, sendingRXCMDs, FsLsSerialMode, Vbus control and monitoring,Test_J and Tesk_K signalling, Low Power Mode,Hostdisconnect, ID detection, HS SOF packets, interrupts,Carkit Mode, interface protection, No SYNC/EOP mode,linestate filtering, and AutoResume.1.1rc2 October 4, 2004 Re-arranged text in section 3.8.7.3. Updated contributors list.1.1 October 20, 2004 1.1rc2 adopted as 1.1 release.The present Specification has been circulated for the sole benefit of legally-recognized Promoters, Adopters and Contributors of the Specification. All rights are expressly reserved, including but not limited to intellectual property rights under patents, trademarks, copyrights and trade secrets. The respective Promoter's, Adopter's or Contributor's agreement entered into by Promoters, Adopters and Contributors sets forth their conditions of use of the Specification.iiPromotersARC International Inc.Conexant Systems, Inc.Mentor Graphics CorporationPhilipsSMSCTransDimension, Inc.ContributorsVertenten PhilipsBartOkur PhilipsBatuhanBillAnderson MotorolaMcInerney TransDimensionBillBooker CypressBrianARCBelangerChrisKolb ARCChrisChrisSchell PhilipsChung Wing Yan PhilipsSrokaPhilipsDaveWang PhilipsDavidWooten TransDimensionDavidSMSCEricKawamotoPhilipsMackayFarranFrazier ConexantFrankFredRoberts SynopsysFarooqConexantHassanLee TransDimensionHyunParr MentorIanStandiford TransDimensionJayPhilipsTjiaJeromeMentorSaundersMarkMohamed Benromdhane ConexantSMSCMorganMonksISINabilTaklaTengstrand ARCPeterRamanand Mandayam ConexantDouglas MentorRobSaleemMohamed Synopsys(Author)ShaunReemeyer PhilipsCypressSimonNguyenSubramanyam Sankaran PhilipsTexasInstrumentsViningSueRemple QualcommTerryChen ConexantTimothyConexantChangVincentQuestions should be emailed to lpcwg@.iiiTable of Contents1.Introduction (1)1.1General (1)1.2Naming Convention (1)1.3Acronyms and Terms (1)1.4References (1)2.Generic Low Pin Interface (2)2.1General (2)2.2Signals (2)2.3Protocol (3)2.3.1Bus Ownership (3)2.3.2Transferring Data (3)2.3.3Aborting Data (4)3.UTMI+ Low Pin Interface (5)3.1General (5)3.2Signals (6)3.3Block Diagram (7)3.4Modes (9)3.5Power On and Reset (10)3.6Interrupt Event Notification (10)3.7Timing (11)3.7.1Clock (11)3.7.2Control and Data (13)3.8Synchronous Mode (15)3.8.1ULPI Command Bytes (15)3.8.2USB Packets (18)3.8.3Register Operations (30)3.8.4Aborting ULPI Transfers (37)3.8.5USB Operations (39)3.8.6Vbus Power Control (internal and external) (52)3.8.7OTG Operations (52)3.9Low Power Mode (55)3.9.1Data Line Definition For Low Power Mode (55)3.9.2Entering Low Power Mode (55)3.9.3Exiting Low Power Mode (56)3.9.4False Resume Rejection (57)3.10Full Speed / Low Speed Serial Mode (Optional) (58)3.10.1Data Line Definition For FsLsSerialMode (58)3.10.2Entering FsLsSerialMode (59)3.10.3Exiting FsLsSerialMode (60)3.11Carkit Mode (Optional) (61)3.12Safeguarding PHY Input Signals (62)4.Registers (65)4.1Register Map (65)4.2Immediate Register Set (67)4.2.1Vendor ID and Product ID (67)4.2.2Function Control (68)4.2.3Interface Control (69)4.2.4OTG Control (71)4.2.5USB Interrupt Enable Rising (72)4.2.6USB Interrupt Enable Falling (73)4.2.7USB Interrupt Status (74)4.2.8USB Interrupt Latch (75)4.2.9Debug (76)4.2.10Scratch Register (76)4.2.11Carkit Control (77)4.2.12Carkit Interrupt Delay (77)iv4.2.13Carkit Interrupt Enable (78)4.2.14Carkit Interrupt Status (78)4.2.15Carkit Interrupt Latch (79)4.2.16Carkit Pulse Control (79)4.2.17Transmit Positive Width (80)4.2.18Transmit Negative Width (80)4.2.19Receive Polarity Recovery (80)4.2.20Reserved (81)4.2.21Access Extended Register Set (81)4.2.22Vendor-specific (81)4.3Extended Register Set (81)4.4Register Settings for all Upstream and Downstream signalling modes (81)5.T&MT Connector (83)5.1General (83)5.2Daughter-card (UUT) Specification (83)vFiguresFigure 1 – LPI generic data bus ownership (3)Figure 2 – LPI generic data transmit followed by data receive (3)Figure 3 – Link asserts stp to halt receive data (4)Figure 4 – Creating a ULPI system using wrappers (5)Figure 5 – Block diagram of ULPI PHY (7)Figure 6 – Jitter measurement planes (12)Figure 7 – ULPI timing diagram (13)Figure 8 – Clocking of 4-bit data interface compared to 8-bit interface (14)Figure 9 – Sending of RX CMD (17)Figure 10 – USB data transmit (NOPID) (18)Figure 11 – USB data transmit (PID) (19)Figure 12 – PHY drives an RX CMD to indicate EOP (FS/LS LineState timing not to scale) (20)Figure 13 – Forcing a full/low speed USB transmit error (timing not to scale) (21)Figure 14 – USB receive while dir was previously low (22)Figure 15 – USB receive while dir was previously high (23)Figure 16 – USB receive error detected mid-packet (24)Figure 17 – USB receive error during the last byte (25)Figure 18 – USB HS, FS, and LS bit lengths with respect to clock (26)Figure 19 – HS transmit-to-transmit packet timing (29)Figure 20 – HS receive-to-transmit packet timing (29)Figure 21 – Register write (30)Figure 22 – Register read (31)Figure 23 – Register read or write aborted by USB receive during TX CMD byte (31)Figure 24 – Register read turnaround cycle or Register write data cycle aborted by USB receive (32)Figure 25 – USB receive in same cycle as register read data. USB receive is delayed (33)Figure 26 – Register read followed immediately by a USB receive (33)Figure 27 – Register write followed immediately by a USB receive during stp assertion (34)Figure 28 – Register read followed by a USB receive (34)Figure 29 – Extended register write (35)Figure 30 – Extended register read (35)Figure 31 – Extended register read aborted by USB receive during extended address cycle (36)Figure 32 – PHY aborted by Link asserting stp. Link performs register write or USB transmit (37)Figure 33 – PHY aborted by Link asserting stp. Link performs register read (38)Figure 34 – Link aborts PHY. Link fails to drive a TX CMD. PHY re-asserts dir (38)Figure 35 – Hi-Speed Detection Handshake (Chirp) sequence (timing not to scale) (40)Figure 36 – Preamble sequence (D+/D- timing not to scale) (41)Figure 37 – LS Suspend and Resume (timing not to scale) (43)Figure 38 – FS Suspend and Resume (timing not to scale) (44)Figure 39 – HS Suspend and Resume (timing not to scale) (46)Figure 40 – Low Speed Remote Wake-Up from Low Power Mode (timing not to scale) (47)Figure 41 – Full Speed Remote Wake-Up from Low Power Mode (timing not to scale) (48)Figure 42 – Hi-Speed Remote Wake-Up from Low Power Mode (timing not to scale) (49)Figure 43 – Automatic resume signalling (timing not to scale) (50)Figure 44 – USB packet transmit when OpMode is set to 11b (51)Figure 45 – RX CMD V A_VBUS_VLD ≤Vbus indication source (54)Figure 46 – Entering low power mode (55)Figure 47 – Exiting low power mode when PHY provides output clock (56)Figure 48 – Exiting low power mode when Link provides input clock (56)Figure 49 – PHY stays in Low Power Mode when stp de-asserts before clock starts (57)Figure 50 – PHY re-enters Low Power Mode when stp de-asserts before dir de-asserts (57)Figure 51 – Interface behaviour when entering Serial Mode and clock is powered down (59)Figure 52 – Interface behaviour when entering Serial Mode and clock remains powered (59)Figure 53 – Interface behaviour when exiting Serial Mode and clock is not running (60)Figure 54 – Interface behaviour when exiting Serial Mode and clock is running (60)Figure 55 – PHY interface protected when the clock is running (62)Figure 56 – Power up sequence when PHY powers up before the link. Interface is protected (63)Figure 57 – PHY automatically exits Low Power Mode with interface protected (63)Figure 58 – Link resumes driving ULPI bus and asserts stp because clock is not running (64)viFigure 59 – Power up sequence when link powers up before PHY (ULPI 1.0 compliant links) (64)Figure 60 – Recommended daughter-card configuration (not to scale) (83)viiTablesTable 1 – LPI generic interface signals (2)Table 2 – PHY interface signals (6)Table 3 – Mode summary (9)Table 4 – Clock timing parameters (11)Table 5 – ULPI interface timing (13)Table 6 – Transmit Command (TX CMD) byte format (15)Table 7 – Receive Command (RX CMD) byte format (16)Table 8 – USB specification inter-packet timings (26)Table 9 – PHY pipeline delays (27)Table 10 – Link decision times (28)Table 11 – OTG Control Register power control bits (52)Table 12 – Vbus comparator thresholds (52)Table 13 – RX CMD VbusValid over-current conditions (53)Table 14 – Vbus indicators in the RX CMD required for typical applications (54)Table 15 – Interface signal mapping during Low Power Mode (55)Table 16 – Serial Mode signal mapping for 6-pin FsLsSerialMode (58)Table 17 – Serial Mode signal mapping for 3-pin FsLsSerialMode (58)Table 18 – Carkit signal mapping (61)Table 19 – Register map (66)Table 20 – Register access legend (67)Table 21 – Vendor ID and Product ID register description (67)Table 22 – Function Control register (68)Table 23 – Interface Control register (70)Table 24 – OTG Control register (71)Table 25 – USB Interrupt Enable Rising register (72)Table 26 – USB Interrupt Enable Falling register (73)Table 27 – USB Interrupt Status register (74)Table 28 – USB Interrupt Latch register (75)Table 29 – Rules for setting Interrupt Latch register bits (75)Table 30 – Debug register (76)Table 31 – Scratch register (76)Table 32 – Carkit Control Register (77)Table 33 – Carkit Interrupt Delay register (77)Table 34 – Carkit Interrupt Enable register (78)Table 35 – Carkit Interrupt Status Register (78)Table 36 – Carkit Interrupt Latch register (79)Table 37 – Carkit Pulse Control (79)Table 38 – Transmit Positive Width (80)Table 39 – Transmit Negative Width (80)Table 40 – Receive Polarity Recovery (81)Table 41 – Upstream and downstream signalling modes (82)Table 42 – T&MT connector pin view (84)Table 43 – T&MT connector pin allocation (84)Table 44 – T&MT pin description (85)viii1. Introduction1.1 GeneralThis specification defines a generic PHY interface in Chapter 2.In Chapter 3, the generic interface is applied to the UTMI+ protocol, reducing the pin count for discrete USB transceiver implementations supporting On-The-Go, host, and peripheral application spaces.Convention1.2 NamingEmphasis is placed on normal descriptive text using underlined Arial font, e.g. must.Signal names are represented using the lowercase bold Arial font, e.g. clk.Registers are represented using initial caps, bold Arial font, e.g. OTG Control.Register bits are represented using initial caps, bold italic Arial font, e.g. USB Interrupt Enable Falling. 1.3 Acronyms and TermsA-device Device with a Standard-A or Mini-A plug inserted into its receptacleB-device Device with a Standard-B or Mini-B plug inserted into its receptacleDeviceDRD Dual-RoleFPGA Field Programmable Gate ArraySpeedFS FullHNP Host Negotiation ProtocolHS Hi-SpeedLink ASIC, SIE, or FPGA that connects to an ULPI transceiverLPI Low Pin InterfaceSpeedLS LowOTG On-The-GoPHY Physical Layer (Transceiver)PLL Phase Locked LoopSE0 Single Ended ZeroSIE Serial Interface EngineSRP Session Request ProtocolT&MT Transceiver and Macrocell TesterULPI UTMI+ Low Pin InterfaceUSB Universal Serial BusUSB-IF USB Implementers ForumUTMI USB 2.0 Transceiver Macrocell InteraceUUT Unit Under Test1.4 References[Ref 1] Universal Serial Bus Specification, Revision 2.0[Ref 2] On-The-Go Supplement to the USB 2.0 Specification, Revision 1.0a[Ref 3] USB 2.0 Transceiver Macrocell Interface (UTMI) Specification, v1.05[Ref 4] UTMI+ Specification, Revision 1.0[Ref 5] CEA-2011, OTG Transceiver Specification[Ref 6] CEA-936A, Mini-USB Analog Carkit Interface Specification[Ref 7] USB 2.0 Transceiver and Macrocell Tester (T&MT) Interface Specification, Version 1.212. Generic Low Pin Interface2.1 GeneralThis section describes a generic low pin interface (LPI) between a Link and a PHY. Interface signals are defined and the basic communication protocol is described. The generic interface can be used as a common starting point for defining multiple application-specific interfaces.Chapter 3 defines the UTMI+ Low Pin Interface (ULPI), which is based on the generic interface described here. For ULPI implementations, the definitions in chapter 3 over-ride anything defined in chapter 2.2.2 SignalsThe LPI transceiver interface signals are described in Table 1. The interface described here is generic, and can be used to transport many different data types. Depending on the application, the data stream can be used to transmit and receive packets, access a register set, generate interrupts, and even redefine the interface itself. All interface signals are synchronous when clock is toggling, and asynchronous when clock is not toggling. Data stream definition is application-specific and should be explicitly defined for each application space for inter-operability.Control signals dir, stp, and nxt are specified with the assumption that the PHY is the master of the data bus. If required, an implementation can define the Link as the master. If the Link is the master of the interface, the control signal direction and protocol must be reversed.Signal Direction DescriptionPHY Interfaceclock I/O Interface clock. Both directions are allowed. All interface signals are synchronous to clock.data I/O Bi-directional data bus, driven low by the Link during idle. Bus ownership is determined by dir. The Link and PHY initiate data transfers by driving a non-zero pattern onto the data bus. LPI defines interface timing for single-edge data transfers with respect to rising edge of clock. An implementation may optionally define double-edge data transfers with respect to both rising and falling edges of clock.dir OUT Direction. Controls the direction of the data bus. When the PHY has data to transfer to the Link, it drives dir high to take ownership of the bus. When the PHY has no data to transfer it drives dir low and monitors the bus for Link activity. The PHY pulls dir high whenever the interface cannot accept data from the Link. For example, when the internal PHY PLL is not stable.stp IN Stop. The Link asserts this signal for 1 clock cycle to stop the data stream currently on the bus. If the Link is sending data to the PHY, stp indicates the last byte of data was on the bus in the previous cycle. If the PHY is sending data to the Link, stp forces the PHY to end its transfer, de-assert dir and relinquish control of the the data bus to the Link.nxt OUT Next. The PHY asserts this signal to throttle the data. When the Link is sending data to the PHY, nxt indicates when the current byte has been accepted by the PHY. The Link places the next byte on the data bus in the following clock cycle. When the PHY is sending data to the Link, nxt indicates when a new byte is available for the Link to consume.Table 1 – LPI generic interface signals22.3 ProtocolOwnership2.3.1 BusThe PHY is the master of the LPI bi-directional data bus. Ownership of the data bus is determined by the dir signal from the PHY, as shown in Figure 1. When dir is low, the Link can drive data on the bus. When dir is high, the PHY can drive data on the bus. A change in dir causes a turnaround cycle on the bus during which, neither Link nor PHY can drive the bus. Data during the turnaround cycle is undefined and must be ignored by both Link and PHY.The dir signal can be used to directly control the data output buffers of both PHY and Link.Figure 1 – LPI generic data bus ownershipData2.3.2 TransferringAs shown in the first half of Figure 2, the Link continuously drives the data bus to 00h during idle. The Link transmits data to the PHY by driving a non-zero value on the data bus. To signal the end of data transmission, the Link asserts stp in the cycle following the last data byte.In the second half of Figure 2, the Link receives data when the PHY asserts dir. The PHY asserts dir only when it has data to send to the Link, and keeps dir low at all other times. The PHY drives data to the Link after the turnaround cycle.The nxt signal can be used by the PHY to throttle the data during transmit and receive. During transmit, nxt may be asserted in the same cycle that the Link asserts stp.Figure 2 – LPI generic data transmit followed by data receive2.3.3 AbortingDataThe PHY can assert dir to interrupt any data being transmitted by the Link. If the Link needs to interrupt data being received from the PHY, it asserts stp for one clock cycle, as shown in Figure 3. This causes the PHY to unconditionally1 de-assert dir and accept a complete data transmit from the Link. The PHY may re-assert dir again only when the data transmit from the Link has completed.Figure 3 – Link asserts stp to halt receive data1 The PHY will not de-assert dir if the ULPI interface is not usable. For example, if the internal PLL is not stable.3. UTMI+ Low Pin Interface3.1 GeneralThis section describes how any UTMI+ core can be wrapped to convert it to the smaller LPI interface. The generic interface described in chapter 2 is used as a starting point. This section always over-rides anything stated in chapter 2. While this specification details support of UTMI+ Level 3, PHY implementers may choose to support any of the Levels defined in UTMI+.ULPI defines a PHY to Link interface of 8 or 12 signals that allows a lower pin count option for connecting to an external transceiver that may be based on the UTMI+ specification. The pin count reduction is achieved by having relatively static UTMI+ signals be accessed through registers and by providing a bi-directional data bus that carries USB data and provides a means of accessing register data on the ULPI transceiver.This specification relies on concepts and terminology that are defined in the UTMI+ specification [Ref 4]. Specifically, if a ULPI PHY design is based on an internal UTMI+ core, then that core must implement the following UTMI+ features.Linestate must accurately reflect D+/D- to within 2-3 clocks. It is up to individual Link designers to use Linestate to time bus events.Filtering to prevent spurious SE0/SE1 states appearing on Linestate due to skew between D+ and D-. Filtering of 14 clock cycles is required in Low Speed, and 2 clock cycles in Full Speed and Hi-Speed modes.The PHY must internally block the USB receive path during transmit. The receive path can be unblocked when the internal Squelch (HS) or SE0-to-J (FS/LS) is seen.TxReady must be used for all types of data transmitted, including Chirp.Due to noise on the USB, it is possible that RxActive asserts and then de-asserts without any valid data being received, and RxValid will not assert. The Link should operate normally with these data-less RxActive assertions.As shown in Figure 4, a PHY or Link based on this specification can be implemented as an almost transparent wrapper around existing UTMI+ IP cores, preserving the original UTMI+ packet timing, while reducing pin count and leaving all functionality intact. This should not be taken to imply that other implementations are not possible.Figure 4 – Creating a ULPI system using wrappers3.2 SignalsTable 2 describes the ULPI interface on the PHY. The PHY is always the master of the ULPI bus. USB and Miscellaneous signals may vary with each implementation and are given only as a guide to PHY designers.Signal Direction DescriptionPHY Interfaceclock I/O Interface clock. The PHY must be capable of providing a 60MHz output clock. Support for an input 60MHz clock is optional. If the PHY supports both clock directions, it must not use the ULPI control and data signals for setting the clock direction.Data bus. Driven to 00h by the Link when the ULPI bus is idle. Two bus widths are allowed:• 8-bit data timed on rising edge of clock.data I/O• (Optional) 4-bit data timed on rising and falling edges of clock.dir OUT Controls the direction of the data bus2. The PHY pulls dir high whenever the interface cannot accept data from the Link. For example, when the internal PLL is not stable. This applies whether Link or PHY is the clock source.stp IN The Link must assert stp to signal the end of a USB transmit packet or a register write operation, and optionally to stop any receive. The stp signal must be asserted in the cycle after the last data byte is presented on the bus.nxt OUT The PHY asserts nxt to throttle all data types, except register read data and the RX CMD. Identical to RxValid during USB receive, and TxReady during USB transmit. The PHY also asserts nxt and dir simultaneously to indicate USB receive activity (RxActive), if dir was previously low. The PHY is not allowed to assert nxt during the first cycle of the TX CMD driven by the Link.USB InterfaceD+ I/O D+ pin of the USB cable. Required.D- I/O D- pin of the USB cable. Required.ID IN ID pin of the USB cable. Required for OTG-capable PHY’s.VBUS I/O V BUS pin of the USB cable. Required for OTG-capable PHY’s. Required for driving V BUS and the V BUS comparators.MiscellaneousXI IN Crystal input pin. Vendors should specify supported crystal frequencies. XO OUT Crystal output pin.C+ I/O Positive terminal of charge pump capacitor.C- I/O Negative terminal of charge pump capacitor.SPKR_L IN Optional Carkit left/mono speaker input signal.SPKR_MIC I/O Optional Carkit right speaker input or microphone output signal.RBIAS I/O Bias current resistor.Table 2 – PHY interface signals2 UTMI+ wrapper developers should note that data bus control has been reversed from UTMI to ensure that USB data reception is not interrupted by the Link.3.3 BlockDiagramAn example block diagram of a ULPI PHY is shown in Figure 5. This example is based on an internal UTMI+ Level 3 core [Ref 4], which can interface to peripheral, host, and On-The-Go Link cores. A description of each major block is given below.ULPI InterfaceUSBCableChargePumpCapacitor Figure 5 – Block diagram of ULPI PHYUTMI+ Level 3 PHY coreThe ULPI PHY may contain a core that is compliant to any UTMI+ level [Ref 4]. Signals for 16-bit data buses are not supported in ULPI. While Figure 5 shows the typical blocks for a Level 3 UTMI+ core, the PHY vendor must specify the intended UTMI+ level, and provide the functionality necessary for compliance to that level.ULPI PHY WrapperThe ULPI PHY wrapper of Figure 5 reduces the UTMI+ interface to the Low Pin Interface described in this document. All signals shown on the UTMI+ Level 3 PHY core are reduced to the ULPI interface signals clock, data, dir, stp, and nxt. The Register Map stores the relatively static signals of the UTMI+ interface. Crystal Oscillator and PLLWhen a crystal is attached to the PHY, the internal clock(s) and the external 60MHz interface clock are generated from the internal PLL. When no crystal is attached, the PHY may optionally generate the internal clock(s) from an input 60MHz clock provided by the Link.General BiasingInternal analog circuits require an accurate bias current. This is typically generated using an external, accurate reference resistor.DrvVbusExternal and ExternalVbusIndicatorThe PHY may optionally control an external VBUS power source via the optional pin DrvVbusExternal. For example, the external supply could be a charge pump or 5V power supply controlled using a power switch. The external supply is controlled by the DrvVbus and the optional DrvVbusExternal bits in the OTG Control register. The polarity of the DrvVbusExternal output pin is implementation dependent.If control of an external VBUS source is provided the PHY may optionally provide for a VBUS power source feed back signal on the optional pin ExternalVbusIndicator. If this pin is provided, the use of the pin is defined by the optional control bits in the OTG Control and Interface Control registers. See Section 3.8.6.3 for further detail.Power-On-ResetA power-on-reset circuit must be provided in the PHY. When power is first applied to the PHY, the power-on-reset will reset all circuitry and leave the ULPI interface in a usable state.Carkit OptionThe PHY may optionally support Carkit Mode [Ref 6]. While in Carkit Mode, the PHY routes speaker and microphone signals between the Link and the USB cable. In carkit mono mode, SPKR_L inputs a mono speaker signal and SPKR_MIC outputs the microphone signal, MIC. In carkit stereo mode, SPKR_L inputs the left speaker signal, and SPKR_MIC inputs the right speaker signal, SPKR_R.3.4 ModesThe ULPI interface can operate in one of five independent modes listed in Table 3. The interface is in Synchronous Mode by default. Other modes are enabled by bits in the Function Control and Interface Control registers. In Synchronous Mode, the data bus carries commands and data. In other modes, the data pins are redefined with different functionality. Synchronous Mode and Low Power Mode are mandatory.Mode Name Mode DescriptionSynchronous Mode This is the normal mode of operation. The clock is running and is stablewith the characteristics defined in section 3.6. The ULPI interface carriescommands and data that are synchronous to clock.Low Power Mode The PHY is powered down with the clock stopped. The PHY keeps dirasserted, and the data bus is redefined to carry LineState and interrupts.See section 3.9 for more information.6-pin FS/LS Serial Mode (optional) The data bus is redefined to 6-pin serial mode, including 6 pins to transmit and receive serial USB data, and 1 pin to signal interrupt events. The clock can be enabled or disabled. This mode is valid only for implementations with an 8-bit data bus. See section 3.10 for more information.3-pin FS/LS Serial Mode (optional) The data bus is redefined to 3-pin serial mode, including 3 pins to transmit and receive serial USB data, and 1 pin to signal interrupt events. The clock can be enabled or disabled. See section 3.10 for more information.Carkit Mode (optional) The data bus is redefined to Carkit mode [Ref 6], including 2 pins for serial UART data, and 1 pin to signal interrupt events. The clock may optionally be stopped. See section 3.11 for more information.Table 3 – Mode summary。

关于攀登珠穆朗玛峰的英语范例Mount Everest, the towering giant of the Himalayas, beckons adventurers from around the globe with its mystique and challenge. The allure of summiting the world's highest peak, standing at a staggering 8,848 meters above sea level, is a dream shared by many, yet achieved by few. Embarking on an expedition to climb Mount Everest is a monumental undertaking, requiring meticulous planning, physical endurance, mental fortitude, and a deep respect for the mountain's formidable power.The journey to the summit of Everest begins long before setting foot on its icy slopes. Months, if not years, of preparation are essential to increase the chances of a successful ascent and ensure the safety of climbers. Physical training is paramount, with climbers focusing on building strength, endurance, and agility to navigate the treacherous terrain of the Himalayas. Cardiovascular exercises, strength training, and high-altitude simulation are all integral components of a climber's fitness regimen.Equally important is mental preparation. Climbing Everest is as much a test of mental resilience as it is physical prowess. The extreme altitude, harsh weather conditions, and inherent risks of high-altitude mountaineering demand unwavering determination and mental discipline. Climbers must cultivate a mindset of adaptability, perseverance, and humility, recognizing that the mountain is ultimately in control.Logistical planning is another critical aspect of preparing for an Everest expedition. From securing permits and organizing logistics to assembling a skilled team of Sherpas, guides, and support staff, every detail must be carefully orchestrated to ensure a smooth and safe ascent. Experienced mountaineering outfitters play a vital role in coordinating the myriad logistics involved in a Himalayan expedition, providing climbers with essential support services, equipment, and expertise.As climbers make their way through the Khumbu Valley and ascend the flanks of Everest, they are greeted by a landscape of breathtaking beauty and unforgiving terrain.The Khumbu Icefall, notorious for its towering seracs and precarious ice bridges, poses one of the most significant challenges of the climb. Navigating this ever-shifting maze of ice requires skill, concentration, and a healthy dose of courage.Above the Icefall lies the Western Cwm, a vast, bowl-shaped valley of snow and ice flanked by towering peaks. Climbers must carefully pace themselves as they ascend through the thin air of the high Himalayas, acclimatizing to the altitude and conserving their energy for the final push to the summit.The final leg of the ascent takes climbers along the Southeast Ridge, a narrow and exposed route that teststheir endurance and resolve. Battling fatigue, altitude sickness, and the biting cold, climbers inch their way closer to the summit with each arduous step. The infamous Hillary Step, a near-vertical rock face just below the summit, presents one last formidable obstacle before reaching the rooftop of the world.Standing atop the summit of Mount Everest is a moment of unparalleled triumph and humility. Surrounded by the vast expanse of the Himalayas, with the world spread out below, climbers experience a profound sense of awe and reverence. Yet, the summit is only half the journey, and the descent presents its own set of challenges and dangers.Descending safely from the summit is imperative, as fatigue and altitude-related illnesses can pose significant riskson the descent. Climbers must carefully monitor their physical and mental condition, pacing themselves as they make their way back down the mountain. The support and expertise of Sherpas and guides are invaluable during this critical phase of the expedition, providing assistance and guidance to ensure a safe return to base camp.Reaching the safety of base camp marks the end of an epic journey, but the memories and lessons learned on Everestwill endure a lifetime. The mountain has a way of leavingan indelible mark on those who dare to challenge its slopes, instilling a profound respect for the power and majesty of the natural world. As climbers reflect on their journey,they are reminded that true greatness lies not in conquering mountains, but in the humility and reverence with which we approach them.。

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UTMI+ SpecificationRevision 1.0Revision HistoryRevision Issue Date Comment0.7 April 24th, 2002 Initial version0.71 April 29th, 2002 Reworked the different levels0.72 June 4th, 2002 Extended definition of OpModeAdded outline on how to implement multi-port host controllers usingUTMI+0.8 June 17th, 2002 Promoted to version 0.8 to allow review by OTG workgroup members0.81 July 3rd, 2002 Clarified Optional charge pump, rewording for grammer and clarity0.82 July 22nd, 2002 Added signal IdPullupAdded signal FsSerialMode and legacy interface signalsAdded signal TxBitstuffEnable / TxBitstuffEnableHRemoved signal SessEnd0.83 October 23rd, 2002 Changed FsSerialMode into FsLsSerialModeAdded SessEnd signal back because there is still uncertainty that anOTG system will work without this signal in all conditions.Added clarifications0.9rc January 8th, 2003 Added clarification of long EOP generationModified suspend/resume behaviour in host modeChanged IdPullup timingAdded chapter on T&MT connector0.9rc2 January 17th, 2003 Added section on ambiguities in UTMI v1.05 specAdded clarification on HostDisconnect signal when PHY is in suspend0.9rc3 February 7th, 2003 Changed TermSelect definition for LS devicesChanged clarification for RxActive/RxValid during transmitAdded clarification for LineState0.9 February 21st, 2003 Added more clarification to LineStatePromoted to version 0.9 by OTG workgroup0.91 October 13th, 2003 Changed time between IdPullup being asserted and IdDig having a validvalue.Updated LineState tablesChanged behaviour of OpMode during chirp sequenceUpdated disclaimer0.92 November 13th, 2003 Changed time T1 during resume to be minimum 16 LS bit times. Thisallows the transceiver to complete the resume signaling in a correctway.1.0 February 25th, 2004 Version approved by the Promoters and Adopters of UTMI+/ULPI"The present Specification has been circulated for the sole benefit of legally-recognized Promoters, Adopters and Contributors of the Specification. All rights are expressly reserved, including but not limited to intellectual property rights under patents, trademarks, copyrights and trade secrets. The respective Promoter's, Adopter'sor Contributor's agreement entered into by Promoters, Adopters and Contributors sets forth their conditions of use of the Specification."Table of Contents1.Introduction (6)1.1Purpose (6)1.2Audience (6)1.3Disclaimers (6)1.4Relevant Documents (6)2.Definition of Different levels (7)2.1UTMI+ level 0 : USB2.0 peripherals (7)2.1.1Additional requirements and clarifications on top of UTMI (8)2.2UTMI+ level 1 : USB2.0 peripherals, host controllers and On-the-Go devices (HS and FS only) (9)2.2.1Additional signals for UTMI+ level 1 (9)2.2.2Generation of long EOP (15)2.2.3Data line pulsing (16)2.2.4HS keep-alive generation (16)2.2.5UTMI+ level 1 transceiver core used in a USB2.0 peripheral (17)2.3UTMI+ level 2 : USB2.0 peripherals, host controllers and On-the-Go devices (HS / FS / LS / no hubsupport) (17)2.3.1XcvrSelect(1:0) (18)2.3.2LS keep-alive generation (19)2.3.3LineState (19)2.4UTMI+ level 3 : USB2.0 peripherals, host controllers and On-the-Go devices (HS / FS / LS / preamble)202.4.1XcvrSelect(1:0) (20)2.4.2Multi-port host controllers (21)3.Explanation of different signaling modes (22)3.1Chirp sequence (22)3.2Suspend / Resume signaling for downstream facing ports (22)3.3Transmit error reporting for downstream facing ports (24)3.4Selection of different signaling modes for upstream and downstream facing ports (25)4.T&MT Connector (26)FiguresFigure 1 : UTMI+ levels (7)Figure 2 : UTMI+ level 0 entity diagram (16-bit interface) (8)Figure 3 : UTMI+ level 1 entity diagram (10)Figure 4 : HostDisconnect behaviour (signals are not on scale) (14)Figure 5 : Data line pulsing for a Dual-Role B-device (16)Figure 6 : HS keep-alive generation (16)Figure 7 : UTMI+ level 2 entity diagram (18)Figure 8 : LS keep-alive generation (19)Figure 9 : Reset sequence for a HS peripheral connected to a HS Host Controller (22)Figure 10 : Resume signaling on downstream facing ports (23)Figure 11 : Transmit error reporting for downstream facing ports (24)TablesTable 1 : Filtering of LineState (9)Table 2 : UTMI+ level 1 transceiver core used in a USB2.0 peripheral (17)Table 3 : LineState for upstream facing ports (DpPulldown and DmPulldown = 0) (20)Table 4 : LineState for downstream facing ports(DpPulldown and DmPulldown = 1) (20)Table 5 : Different signaling modes for upstream and downstream facing ports (25)Table 6 : T&MT connector pinning[1] (26)Acronyms and TermsFS Full-SpeedHS High-SpeedIC Integrated CircuitLS Low-SpeedOTG On-The-GoSE0 Single Ended ZeroUSB Universal Serial BusUSB-IF USB Implementers ForumUTMI USB 2.0 Transceiver Macrocell InterfaceContributorsBart Vertenten PhilipsSrinivas Pattamatta PhilipsJerome Tjia PhilipsChung Wing Yan PhilipsFarran Mackay PhilipsChris Kolb ARCChristopher Meyers ARCDavid Cobbs CypressDavid Wooten CypressEric Huang SynopsysRavikumar Govindaraman SynopsysSaleem Mohammad SynopsysMichael Pennell SMSCNabil Takla InnovativePaul Berg MCCIPeter Hirt ST MicroelectronicsAlok Kaushik ST MicroelectronicsRob Douglas Mentor GraphicsAndy King Mentor GraphicsZong Liang Wu TransDimensionHemal Doshi Portalplayer Inc1. Introduction1.1 PurposeThe purpose of this document is to specify an interface to which USB 2.0 ASIC, ASSP, discrete PHY, system peripherals and IP vendors can develop USB2.0 products. The existing UTMI specification describes an interface only for USB2.0 peripherals. The UTMI specification can not be used to develop USB 2.0 host or On-The-Go peripherals. The intention of this UTMI+ specification is to extend the UTMI specification to standardize the interface for USB 2.0 hosts and USB 2.0 On-The-Go peripherals. The UTMI+ specification defines and standardizes the interoperability characteristics with existing USB 2.0 hosts and peripherals.1.2 AudienceThis document is intended for developers and vendors of USB 2.0 ASIC, ASSP, discrete PHY, system, peripheral and IP products.1.3 DisclaimersThis document is a recommendation of the contributors indicated in the title pages. It does not necessarily reflect the position of their respective companies, the OTG working group, or the position of the USB-IF.1.4 Relevant Documents• USB 2.0 Transceiver Macrocell Interface Specification, version 1.05, Steve McGowan, March 29th, 2001• USB 2.0 Transceiver and Macrocell Tester(T&MT) Interface Specification, Wes Talarek, version 1.2, April 4th, 2001• On-The-Go Supplement to the USB 2.0 Specification (/developers/onthego)• USB 2.0 Specification (/developers/docs.html)• OTG Certification Specification Revision 0.7• ECN_27%_ Resistor (/app/members/ecn_html)• OTG Labeling Specification Revision 0.632. Definition of Different levelsThe level of complexity needed for a high-speed USB On-The-Go peripheral can be very different. Especially the complexity needed for the host controller part is very dependent on the targeted peripheral list. Therefore the UTMI+ specification is built up in progressive levels. The base (level 0) for UTMI+ is the UTMI specification version 1.05[1]. Level 1 is targeted for USB On-The-Go Dual-Role-Devices that must be capable of generating HS and FS traffic. Level 2 adds the possibility of generating LS traffic towards LS devices that are directly connected to the USB On-The-Go DRD. Finally, Level 3 adds the possibility to have also USB 2.0 FS hubs in the USB tree and let the host controller part of the USB On-The-Go DRD communicate with LS devices that are connected to the USB FS hub controller.Any transceiver core that is developed to a given level shall be compliant with all levels below that level.In Figure 1, a general overview is given on how the different levels layer on each other.Figure 1 : UTMI+ levels2.1 UTMI+ level 0 : USB2.0 peripheralsThe base of the UTMI+ specification is the UTMI specification version 1.05. This is defined as UTMI+ level 0. The transceiver cores that pretend to be UTMI+ level 0 compliant can be used in a USB2.0 peripheral design. These cores cannot be used to implement USB2.0 Hosts or On-the-Go peripherals without additional logic.Figure 2 : UTMI+ level 0 entity diagram (16-bit interface)During the implementation of UTMI+, it was found that some parts of the UTMI spec were not clearly specified or could be interpreted in different ways. This caused that integration of UTMI transceiver from one vendor with the USB device core from another vendor was not always working. To remove these problems from future designs any core that is UTMI+ compliant must implement the requirements described in section 2.1.1.For more details on how to implement a UTMI+ level 0 transceiver see also the UTMI spec[1]. In Figure 2 a general overview is given of all interface signals needed for UTMI+ level 0 transceiver with 16-bit interface. For a UTMI+ level 0 transceiver with 8-bit interface the TXValidH, RXValidH, DataBus16_8, DataIn(15:8) and DataOut(15:8) signals are not needed.2.1.1 Additional requirements and clarifications on top of UTMI2.1.1.1 Use of LineState for timersThe UTMI spec mentions several times that LineState is the most accurate signal to be used for timing a certain state on the USB bus. It is not a hard requirement for the USB device core designer to use this signal. He can use whatever method he wants as long as correct behavior on the USB bus is guaranteed without forcing additional constraints on the PHY design.2.1.1.2 LineState filteringMinimal filtering should be applied to LineState to ensure that skew on the DP/DM signals does not generate unwanted SE0 or SE1 states between J and K states. For instance, for FS mode Table 7-9 of the USB 2.0 Specification identifies the “Width of SE0 interval during differential transition” to be 14ns max. These SE0 states are noise to the SIE and shouldnot be propagated by LineState. To be able to filter worst case SE0 noise, the transceiver should implement filtering as indicated in Table 1.Filtering should only occur on an SE0. If during filtering the SE0 a non-SE0 event occurs then the filtering should stop and linestate behaviour continues as previously.Bus speed 8-bit interface (CLK = 60MHz) 16-bit interface (CLK = 30 MHz) Low-speed mode filtering 14 CLK cycles 7 CLK cyclesFull-speed mode filtering 2 CLK cycles 1 CLK cycleHigh-speed mode filtering 2 CLK cycles 1 CLK cycleTable 1 : Filtering of LineState2.1.1.3 RxActive/RxValid during transmitThe UTMI PHY must internally block the USB receive path once a USB transmit has begun. The receive path can be unblocked when the internal Squelch (HS) or SE0-to-J (FS/LS) is seen.2.1.1.4 TxReady behavior when not bitstuffingTxReady must be used in chirp mode. If TxReady is not asserted by the UTMI PHY when the USB device core was sending a chirp, it can cause the device core to lock-up if the device core is holding the transmit data on the bus until it sees TxReady asserted. By explicitly requiring that TxReady must be asserted for all transmit data including chirp data, this problem can be avoided.2.1.1.5 Receive End DelayAt the end of page 59 of the UTMI spec v.1.05 there is a contradiction between the number of bit times and the number of clock cycles for Total Receive End Delay for an interface running at 30MHz. 6 30 MHz clock cycles is actually 96 bit times. For a 16 bit transceiver interface, the Total Receive End Delay must be between 32-96 bit times or 2-6, 30 MHz CLKs2.2 UTMI+ level 1 : USB2.0 peripherals, host controllers and On-the-Go devices (HSand FS only)Any transceiver core that has an interface compliant with UTMI+ level 1, has all signals compliant with UTMI+ level 0. A transceiver core with UTMI+ level 1 interface can be used for USB2.0 peripheral, host or On-the-Go device designs that support only HS and FS traffic. If a host controller needs to be able to communicate with a LS device some additional functions are required that are not part of level1 (cfr section 2.3).Transceivers implementing level 1 may optionally include an integrated charge pump to supply VBUS current to the On-The-Go connector. If the charge pump is integrated within the transceiver macrocell then a description of the charge pump must be given in the transceiver datasheet to allow integrators to build a complete USB On-The-Go peripheral. If the charge pump is not integrated within the transceiver macrocell then the optional DrvVbus signal may be omitted from the macrocell.2.2.1 Additional signals for UTMI+ level 1.USB On-The-Go peripherals have some additional capabilities and therefore some new signals need to be implemented.1. A USB On-The-Go dual role peripheral needs to be capable to distinguish between a mini-A and mini-B plug.2. A USB On-The-Go peripheral has to know if Vbus is below or above a certain voltage level.3. A USB On-The-Go peripheral must be able to drive Vbus and charge or discharge Vbus.4. A USB On-The-Go dual role peripheral needs to be able to switch the pull-up resistor on DP and the pull-downresistor on both DP and DM.5. The downstream facing port of a host controller must have 15 kOhm pull-down resistors on both DP and DM lines.Some signals are needed to do the correct switching of the resistors6. The host controller must be able to detect a disconnect of a peripheral. This is possible for a FS peripheral by usingLineState, but it is not possible for HS peripherals using the current UTMI specification. Therefore an additional signal needs to be implemented. To make the design of the digital SIE easier, this new disconnect signal will be used in both speeds (HS/FS) to indicate if there is a device connected or not.In Figure 3 an overview is given of all signals needed for the UTMI+ level 1 interface.Figure 3 : UTMI+ level 1 entity diagram2.2.1.1 IdDig / IdPullupThe id signal is indicating the state of the ID pin on the USB mini receptacle. This pin makes it able to determine which kind of plug is connected. To save power, there is also an IdPullup signal. Only when this IdPullup signal is high, the analog Id line will be sampled and the IdDig signal will indicate the correct value.IdPullup Signal that enables the sampling of the analog Id line.0b : Sampling of Id pin is disabled. IdDig is not valid1b : Sampling of Id pin is enabled.IdDig Indicates whether the connected plug is a mini-A or mini-B. This is only valid when IdPullup is set to 1b. It must be valid within 50ms after IdPullup is set to 1b.0b : connected plug is a mini-A1b : connected plug is a mini-B2.2.1.2 AValidThe AValid signal is used to indicate if the session for an A-peripheral is valid. This signal is 1b when Vbus is above 2V. Avalid Indicates if the session for an A-peripheral is valid (0.8V < Vth < 2V).0b : Vbus < 0.8V1b : Vbus > 2V2.2.1.3 BValidThe BValid signal is used to indicate if the session for a B-peripheral is valid. This signal is 1b when Vbus is above 4V. Bvalid Indicates if the session for an B-peripheral is valid (0.8V < Vth < 4V).0b : Vbus < 0.8V1b : Vbus > 4V2.2.1.4 VbusValidThe VbusValid signal is used to determine whether or not the voltage on Vbus is at a valid level for operation. The minimum threshold for the Vbus comparator is 4.4VVbusValid Indicates if the voltage on Vbus is at a valid level for operation (4.4V < Vth < 4.75V).0b : Vbus < 4.4V1b : Vbus > 4.75V2.2.1.5 SessEndThe SessEnd signal is used to determine if the voltage on Vbus is below its B-Device Session End threshold. SessEnd Indicates if the voltage on Vbus (0.2V < Vth < 0.8V).1b : Vbus < 0.2V0b : Vbus > 0.8VAccording to the definition in the OTG supplement of the USB 2.0 specification, it must be possible to build a USB OTG DRD without the SessEnd signal. The detection can be done in the digital controller section. 50ms after Vbus is discharged, the voltage on Vbus must be below the B-device Session End Threshold. This is correct in a normal working environment. However it is always possible that in systems for some reason the Vbus does not go down to levels less than SessEnd (e.g. standard host, short circuit on the charge pump so that Vbus is always on, etc). Therefore it is seen that this signal is a must and is preferred to be used in order to have a correct working system in all cases.2.2.1.6 DrvVbusThe DrvVbus is an enable signal to drive 5V on Vbus. The DrvVbus signal is optional for transceiver implementations,depending on whether an integrated charge pump is implemented. The DrvVbus signal is mandatory for SIE implementing an interface that is compliant with level 2 of UTMI+.DrvVbus This signal enables to drive 5V on Vbus0b : do not drive Vbus1b : drive 5V on Vbus2.2.1.7 DischrgVbusIf DischrgVbus is active then Vbus will be pulled down through a resistor to ground. This is needed to discharge Vbus before initiating SRP. B-peripherals use this signal to ensure that Vbus is at a low enough voltage before starting SRP. The minimum time that DischrgVbus needs to be asserted is 50 ms.DischrgVbus The signal enables discharging Vbus.1b : discharge Vbus through a resistor (this has to be active for at least 50 ms)0b : do not discharge Vbus through a resistor2.2.1.8 ChrgVbusIf ChrgVbus is active then Vbus will be pulled up through a resistor. This is done to initiate SRP.The minimum time that ChrgVbus needs to be asserted is 30 ms.ChrgVbus The signal enables charging Vbus.1b : charge Vbus through a resistor (this has to be active for at least 30 ms)0b : do not charge Vbus through a resistor2.2.1.9 DpPulldown / DmPulldownDpPulldown This signal enables the 15k Ohm pull-down resistor on the DP line.0b : Pull-down resistor not connected to DP1b : Pull-down resistor connected to DPDmPulldown This signal enables the 15k Ohm pull-down resistor on the DM line.0b : Pull-down resistor not connected to DM1b : Pull-down resistor connected to DMThese two signals are used to switch on the 15k Ohm pull-down resistors on both DP and DM for a host.These signals should not been toggled during normal operation.Using the TermSelect signal can do switching the pull-up resistor for a peripheral.For a peripheral both signals should been set to 0b. For a host controller both signals should been set to 1b.2.2.1.10 HostDisconnectHostDisconnect This signal is used for all types of peripherals connected to it. It is only valid whenDpPulldown and DmPulldown are 1b. If DpPulldown and DmPulldown are not 1b then thebehaviour of HostDisconnect is undefined.As long as there is no peripheral connected, this signal will be 1b. If a peripheral isconnected, then the value of this signal will be 0b.Internally there are two disconnect signals, one that detects disconnect in HS mode and one that detects connect/disconnect in FS mode. Depending on XcvrSelect one of these signals is routed to the actual output port HostDisconnect. If in HS mode a disconnect is detected, the HostDisconnect signal will be set to 1b. At that moment the Macrocell will be switched to FS mode (XcvrSelect = 01b).In FS/LS mode, a disconnect condition occurs if the transceiver detects a SE0 signaling f or 2.5 us and a connect condition occurs if the transceiver detects non-SE0 signaling for 2.5 us. If a disconnect is detected, hostdisconnect is asserted and if a connect is detected it is deasserted.In HS mode, a disconnect condition is evaluated every time a HS SOF packet is sent. If a disconnect is detected, hostdisconnect is asserted.When hostdisconnect is asserted in high-speed mode the transceiver is placed into full-speed mode by the host core. Also when the host core wants to put the USB bus (which has a hi-speed device connected) into suspend mode, it switches the transceiver from hi-speed mode into full-speed mode. At that moment the connected hi-speed device is still in hi-speed and the USB bus state is still in SE0. To prevent false full-speed connect/disconnects, the hostdisconnect signal cannot be updated for 4 ms from the transition into full-speed. After the 4 ms recovery time the status of the full-speed connect/disconnect can be determined and the hostdisconnect signal updated accordingly. The 4 ms of recovery time allows the peripheral device connected to the host to detect the suspend signaling on the USB bus, move into the FS suspend mode and bring the USB bus to the Full Speed Idle state (Jstate).However if the transceiver is put into power down (which can happen for power consumption reasons), the hostdisconnect signal is deasserted immediately (in both cases : device connected or not) and the 4 ms recovery time is not required. The core attached must look at LineState to see if the state of the USB bus changes. If it does, the core should bring the transceiver out of power down and look at the hostdisconnect signal. When the transceiver comes out of power down the hostdisconnect signal must have the correct value within 1 ms after the clock is back up and running.Disconnect of HS peripheralTransition from operational to suspendHS disconnectSOF tokens on USB busHi-speed device Device goes into suspendFigure 4 : HostDisconnect behaviour (signals are not on scale)2.2.1.11 OpModeOpMode(1:0)These signals select between various operational modes :00b : Normal operation (The UTMI+ transceiver automatically appends the SYNC and EOP pattern)01b : Non-driving10b : Disable bit stuffing and NRZI encoding11b : Normal operation without automatic generation of SYNC and EOP. NRZI encoding is always enabled. Bit stuffing depends on the value of TxBitstuffEnable andTxBitstuffEnableH. This is only valid when XcvrSelect is set to 00b. If OpMode is set to 11b together with XcvrSelect not equal to 00b, the behavior of the transceiver is undefined.The extension of OpMode is done to have control on all bits that are sent on the USB bus. This mode has to be used in order to send a HS keep-alive packet on the USB bus (cfr. section 2.2.4).2.2.1.12 TxBitstuffEnable / TxBitstuffEnableHThese signals is only used when Opm ode is set to 11b. While OpMode is set to 11b the automatic generation of SYNC and EOP is disabled. However if for some reason somebody wants to have control over generation the SYNC and EOP pattern, there must be a way to indicate to the transceiver that a Bitstuff error must be generated on the bus for the EOP. These signals make it also possible to transmit high-speed USB packets while the transceiver is put into OpMode = 11b. TxBitstuffEnable Indicates if the data on the DataOut(7:0) lines needs to be bitstuffed or not.0b : Bitstuffing is disabled1b : Bitstuffing is enabledTxBitstuffEnableH Indicates if the data on the DataOut(15:8) lines needs to be bitstuffed or not.0b : Bitstuffing is disabled1b : Bitstuffing is enabledThis signal is only required when the 16 bit mode is selected.2.2.1.13 FsLsSerialModeThe FsLsSerialMode signal indicates how the digital core signals the FS and LS packets to the transceiver. If this signal is set to 0b, the packets are communicated via the parallel interface as defined in the UTMI spec.If the signal is set to 1b, the packets are communicated using the serial interface as indicated below.The reason to add this to the interface is to make it possible to reuse existing FS/LS host controller IP without changing its interface. This also makes that if this interface is used for the host controller part, it is possible to implement complete host controller functionality using a UTMI+ level 1 compliant interface. This could be seen as a contradiction with the actual naming of the levels. However the leveling naming is referring to the situation where only the parallel interface is used.FsLsSerialMode 0b : FS and LS packets are sent using the parallel interface.1b : FS and LS packets are sent using the serial interface.Tx_Enable_N Active low output enable signal.Tx_DAT Differential data at D+/D- outputTx_Se0 Force Single-Ended ZeroRx_DP Single-ended receive data, positive terminal.The data is only valid if FsLsSerialMode is set to 1bRx_DM Single-ended receive data, negative terminalThe data is only valid if FsLsSerialMode is set to 1bRx_RCV Receive dataThe data is only valid if FsLsSerialMode is set to 1b2.2.2 Generation of long EOPMost of the HS USB packets that are generated consist of an 8-bit EOP. Only when a SOF has to be sent on the USB bus, the EOP must be 40 bits. To generate the correct packets on the USB bus, the transceiver must check the PID value of every packet that is transmitted in HS mode. When the PID is equal to SOF, the transceiver m ust generate a 40-bit EOP. In all other HS cases the transceiver generates an 8-bit EOP on the USB bus2.2.3 Data line pulsingData line pulsing can be implemented by using the XcvrSelect, DpPullDown, DmPullDown and TermSelect signals. In the figure 5 the period T has to be between 5 and 10 ms.Figure 5 : Data line pulsing for a Dual-Role B-device2.2.4 HS keep-alive generationIn certain cases the debug port of an EHCI compliant host controller needs to be able to transmit a HS keep-alive SYNC packet. This is a SYNC pattern without any other data or EOP. The figure underneath indicates how this HS keep-alive can be generated.TxValid DataIn(7:0)OpMode(1:0)XcvrSelect(1:0)TxReady CLK 00h00b11b80hFigure 6 : HS keep-alive generation2.2.5 UTMI+ level 1 transceiver core used in a USB2.0 peripheralA transceiver core that is compliant to UTMI+ level 1 can be used together with a SIE that is compliant with the UTMI specification to develop a USB 2.0 peripheral. To be able to do some signals have to be tied off or can be left open. This is indicated in Table 1.Signal Direction Value when used in USB2.0 peripheralDpPulldown In 0bDmPulldown in 0bHostDisconnect out OpenIdDig out OpenIdPullup in 0bAValid out OpenBValid out OpenVbusValid out same use as defined in UTMI+ level 20b : Vbus < 4.4V1b : Vbus > 4.75VSessEnd out OpenDrvVbus in 0bDischrgVbus in 0bChrgVbus in 0bTxBitStuffEnable in 0bTxBitStuffEnableH in 0bFsLsSerialMode in 0bTx_Enable_N in 1bTx_DAT in 0bTx_SE0 in 0bRx_DP out OpenRx_DM out OpenRx_RCV out OpenTable 2 : UTMI+ level 1 transceiver core used in a USB2.0 peripheral2.3 UTMI+ level 2 : USB2.0 peripherals, host controllers and On-the-Go devices (HS/ FS / LS / no hub support)If a host controller must be able to handle LS traffic some more extensions are needed. This level covers all USB 2.0 traffic described in the USB specification except a host sending a LS packet to a USB LS device that is connected through a FS hub (PRE PID handling). This is covered in the next level.• The host controller must be able to transmit packets at LS.• The host controller must be able to send LS keep-alive packets on a low-speed bus. A LS keep-alive packet is equal to a LS EOP.Figure 7 gives an overview of all signals.。

From: 1. UTMI USB2.0 Transceiver Macrocell Interacedefines an interface between two IP blocks: the USB Tran sceiver Macrocell (IP) and the USB Link layer (SIE). The UTM I interface provides functionality for USB peripherals only, not f or USB hosts or On-The-Go.2. UTMI+adds host and On-The-Go capabilities to the USB system.UTMI+ incrementally adds new functionality and interface si gnals to the Link and PHY.UL PI: UTMI+ Low3. ULPI: UTMI+ Low Pin InterfaceThe ULPI specification reduces the Link to PHY interface t o 12 or 8 signals, with support for all the features needed byUSB peripherals, hosts, and OTG. The result is a package si ze as small as 32 pins or less, compared with 64 to 80 pins for UTMI+.4. ULPI PHY Register SetThere are four main types of registers:ID Registers These registers provide a unique identifier to the USB system. If necessary,system software can change b ehavior based on different PHY attachment. This is not genera lly needed because PHY capabilities are chosen at hardware design time.Mode Registers These registers control how the PHY beh aves. Many signals from UTMI+ are changed only when the U SB is idle, so they are placed in registers that are accessed only when the ULPI bus is idle. Several new features have al so been introduced, including Carkit Mode.Interrupt Registers These registers inform the Link of stat us changes in the PHY. Many signals in UTMI+ convey inform ation to the Link that is not timing critical. Those signals have been replaced with status bytes and interrupt signaling. Statu s information is sent only when the ULPI bus is idle.Extra Registers Additional register space is provided for t wo reasons. Some addresses have been reserved for future u se, while other registers are available for vendorspecific use.。

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