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IC datasheet pdf-TAS5615,Pdf,160 W STEREO_300W MONO PurePath HD Analog-Input Power Stage

PurePath Digital

ANALOG

AUDIO

INPUT

TAS5615 https://www.doczj.com/doc/1f12364558.html,.................................................................................................................................................SLAS595A–JUNE2009–REVISED SEPTEMBER2009 160W STEREO/300W MONO PurePath?HD Analog-Input Power Stage

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FEATURES

DESCRIPTION

?Active Enabled Integrated Feedback Provides:

(PurePath?HD)The TAS5615is a high-performance analog input

CLass D amplifier with integrated closed loop –Signal Bandwidth up to80kHz for High

feedback technology(known as PurePath?HD).It Frequency Content From High Definition

has the ability to drive up to160W(1)Stereo into8?Sources

speakers from a single50V supply.

–Ultra Low0.03%THD at1W into8?

PurePath?HD technology enables traditional –0.03%THD Across all Frequencies for

AB-Amplifier performance(<0.03%THD)levels while Natural Sound at1W

providing the power efficiency of traditional class D –80dB PSRR(BTL,No Input Signal)amplifiers.

–>100dB(A weighted)SNR

Ultra Low0.03%THD+N is flat across all frequencies,–Click and Pop Free Startup ensuring that the amplifier doesn’t add uneven

distortion characteristics,and helps maintain a natural –Minimal External Components Compared to

sound.

Discrete Solutions

?Multiple Configurations Possible on the Same The efficiency of this Class-D amplifier is greater than

90%.Undervoltage Protection,Overtemperature, PCB:

clipping,Short Circuit and Overcurrent Protection are –Mono Parallel Bridge Tied Load(PBTL)

all integrated,safeguarding the device and speakers – 2.1Single Ended(SE)Stereo Pair and against fault conditions that could damage the Bridge Tied Load(BTL)Subwoofer system.

–Quad Single Ended(SE)Outputs

?Total Output Power at10%THD+N

–300W in Mono PBTL Configuration

–160W per Channel in Stereo BTL

–80W per Channel in Quad Single Ended

?High Efficiency Power Stage(>90%)With120

m?Output MOSFETs

?Two Thermally Enhanced Package Options:

–PHD(64-pin QFP)

–DKD(44-pin PSOP3)

?Self-Protection Design(Including

Undervoltage,Overtemperature,Clipping,and

Short Circuit Protection)With Error Reporting

?EMI Compliant When Used With

Recommended System Design

APPLICATIONS

?Mini Combo System

(1)Achievable output power levels are dependent on the thermal

configuration of the target application.A high performance ?AV Receivers

thermal interface material between the package exposed ?DVD Receivers

heatslug and the heat sink should be used to achieve high ?Active Speakers output power levels

Please be aware that an important notice concerning

availability,standard warranty,and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.Copyright?2009,Texas Instruments Incorporated Products conform to specifications per the terms of the Texas

Instruments standard warranty.Production processing does not

necessarily include testing of all parameters.

Pin 1 Marker White Dot

P P G G N C N C N C N C P S U _R E F V D D GND_D

GND_C GND_C OUT_C OUT_C PVDD _C PVDD _C BST_C BST_B PVDD_B OUT_B GND_B GND_A G N D G N D G V D D _B G V D D _A B S T _A O U T _A O U T _A P V D D _A P V D D _A G N D _A

PVDD_B OUT_B GND_B DKD PACKAGE (TOP VIEW)

M3OC_ADJ VDD PSU_REF

M2M1READY

OTW SD OSC_IO-OSC_IO+FREQ_ADJ INPUT_D INPUT_C VREG AGND GND VI_CM INPUT_B INPUT_A C_STARTUP

RESET GND_C OUT_A BST_A OUT_B BST_B PVDD_B PVDD_A BST_C PVDD_C OUT_C GND_A GND_B OUT_D PVDD_D BST_D GND_D GVDD_AB GVDD_CD

PVDD_A PVDD_D OUT_D OUT_A PHD PACKAGE (TOP VIEW)

TAS5615

SLAS595A –JUNE 2009–REVISED SEPTEMBER https://www.doczj.com/doc/1f12364558.html,

This integrated circuit can be damaged by ESD.Texas Instruments recommends that all integrated circuits be handled with appropriate precautions.Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure.Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

DEVICE INFORMATION

Terminal Assignment

The TAS5615is available in two thermally enhanced packages:?64-Pin QFP (PHD)Power Package ?44-Pin PSOP3package (DKD)

The package type contains a heat slugs that is located on the top side of the device for convenient thermal coupling to the heat sink.

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MODE SELECTION PINS

MODE PINS OUTPUT

ANALOG

DESCRIPTION

INPUT CONFIGURATION

M3M2M1

000Differential2×BTL AD mode

001——Reserved

010Differential2×BTL BD mode

Differential

0111×BTL+2×SE AD mode,BTL Differential

Single Ended

100Single Ended4×SE AD mode

INPUT_C(1)INPUT_D(1)

101Differential1×PBTL00AD mode

10BD mode

110

Reserved

111

(1)INPUT_C and D are used to select between a subset of AD and BD mode operations in PBTL mode(1=VREG and0=AGND).

PACKAGE HEAT DISSIPATION RATINGS(1)

PARAMETER TAS5615PHD TAS5615DKD RθJC(°C/W)–2BTL or4SE channels 3.63 2.52

RθJC(°C/W)–1BTL or2SE channel(s) 5.95 3.22 RθJC(°C/W)–1SE channel9.9 6.9

Pad Area(2)49mm280mm2

(1)J C is junction-to-case,CH is case-to-heat sink

(2)RθH is an important consideration.Assume a2-mil thickness of typical thermal grease between the pad area and the heat sink and both

channels active.The RθCH with this condition is1.22°C/W for the PHD package and and1.02°C/W for the DKD package.

Table1.ORDERING INFORMATION(1)

T A PACKAGE DESCRIPTION 0°C–70°C TAS5615PHD64pin HTQFP

0°C–70°C TAS5615DKD44pin PSOP3

(1)For the most current package and ordering information,see the Package Option Addendum at the end of this document,or see the TI

website at https://www.doczj.com/doc/1f12364558.html,.

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SLAS595A–JUNE2009–REVISED https://www.doczj.com/doc/1f12364558.html,

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range unless otherwise noted(1)

TAS5615UNIT VDD to AGND–0.3to13.2V GVDD to AGND–0.3to13.2V PVDD_X to GND_X(2)–0.3to69.0V

OUT_X to GND_X(2)–0.3to69.0V

BST_X to GND_X(2)–0.3to82.2V

BST_X to GVDD_X(2)–0.3to69.0V VREG to AGND–0.3to4.2V

GND_X to GND–0.3to0.3V

GND_X to AGND–0.3to0.3V

OC_ADJ,M1,M2,M3,OSC_IO+,OSC_IO–,FREQ_ADJ,VI_CM,C_STARTUP,–0.3to4.2V

PSU_REF to AGND

INPUT_X–0.3to5V RESET,SD,OTW1,OTW2,CLIP,READY to AGND–0.3to7.0V Continuous sink current(SD,OTW1,OTW2,CLIP,READY)9mA Operating junction temperature range,T J0to150°C Storage temperature,T stg–40to150°C

Human-Body Model(3)(all pins)±2kV Electrostatic discharge

Charged-Device Model(3)(all pins)±500V

(1)Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.These are stress ratings

only,and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied.Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2)These voltages represents the DC voltage+peak AC waveform measured at the terminal of the device in all conditions.

(3)Failure to follow good anti-static ESD handling during manufacture and rework will contribute to device malfunction.Make sure the

operators handling the device are adequately grounded through the use of ground straps or alternative ESD protection. RECOMMENDED OPERATING CONDITIONS

over operating free-air temperature range(unless otherwise noted)

MIN NOM MAX UNIT PVDD_x Half-bridge supply DC supply voltage255052.5V

Supply for logic regulators and gate-drive

GVDD_x DC supply voltage10.81213.2V circuitry

VDD Digital regulator supply voltage DC supply voltage10.81213.2V

R L(BTL)78.0

Output filter according to schematics in

R L(SE)Load impedance 3.5 4.0?

the application information section.

R L(PBTL) 3.5 4.0

L OUTPUT(BTL)1415

L OUTPUT(SE)Output filter inductance Minimum output inductance at I OC1415μH

L OUTPUT(PBTL)1415

Nominal350400450 PWM frame rate selectable for AM interference

F PWM AM1310340350kHz

avoidance;1%Resistor tolerance

AM2260300320

Nominal;Master mode9.51010.5

R FREQ_ADJ PWM frame rate programming resistor AM1;Master mode19.82020.2k?

AM2;Master mode29.73030.3

Voltage on FREQ_ADJ pin for slave mode

V FREQ_ADJ Slave mode 3.3

operation

T J Junction temperature0150°C

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PIN FUNCTIONS

FUNCTION(1)DESCRIPTION

NAME PHD NO.DKD NO.

AGND810P Analog ground

BST_A5443P HS bootstrap supply(BST),external0.033μF capacitor to OUT_A required. BST_B4134P HS bootstrap supply(BST),external0.033μF capacitor to OUT_B required. BST_C4033P HS bootstrap supply(BST),external0.033μF capacitor to OUT_C required. BST_D2724P HS bootstrap supply(BST),external0.033μF capacitor to OUT_D required. /CLIP18–O Clipping warning;open drain;active low

C_STARTUP35O Startup ramp requires a charging capacitor of4.7nF to AGND

FREQ_ADJ1214I PWM frame rate programming pin requires resistor to AGND

7,23,24,57,

GND9P Ground

GND_A48,4938P Power ground for half-bridge A

GND_B46,4737P Power ground for half-bridge B

GND_C34,3530P Power ground for half-bridge C

GND_D32,3329P Power ground for half-bridge D

GVDD_A55–P Gate drive voltage supply requires0.1μF capacitor to GND_A

GVDD_B56–P Gate drive voltage supply requires0.1μF capacitor to GND_B

GVDD_C25–P Gate drive voltage supply requires0.1μF capacitor to GND_C

GVDD_D26-P Gate drive voltage supply requires0.1uF capacitor to GND_D

GVDD_AB–44P Gate drive voltage supply requires0.22μF capacitor to GND_A/GND_B GVDD_CD–23P Gate drive voltage supply requires0.22μF capacitor to GND_C/GND_D INPUT_A46I Input signal for half bridge A

INPUT_B57I Input signal for half bridge B

INPUT_C1012I Input signal for half bridge C

INPUT_D1113I Input signal for half bridge D

M12020I Mode selection

M22121I Mode selection

M32222I Mode selection

NC59-62––No connect,pins may be grounded.

OC_ADJ13O Analog over current programming pin requires resistor to ground:

64pin QFP package(PHD)=22k?

44pin PSOP3Package(DKD)=24k?

OSC_IO+1315I/O Oscillaotor master/slave output/input.

OSC_IO–1416I/O Oscillaotor master/slave output/input.

/OTW-18O Overtemperature warning signal,open drain,active low.

/OTW116–O Overtemperature warning signal,open drain,active low.

/OTW217–O Overtemperature warning signal,open drain,active low.

OUT_A52,5339,40O Output,half bridge A

OUT_B44,4536O Output,half bridge B

OUT_C36,3731O Output,half bridge C

OUT_D28,2927,28O Output,half bridge D

PSU_REF631P PSU Reference requires close decoupling of330pF to AGND

Power supply input for half bridges A requires close decoupling of2.2-μF PVDD_A50,5141,42P

capacitor to GND_A.

Power supply input for half bridges B requires close decoupling of2.2-μF PVDD_B42,4335P

capacitor to GND_B.

Power supply input for half bridges C requires close decoupling of2.2-μF PVDD_C38,3932P

capacitor to GND_C.

(1)I=Input,O=Output,P=Power

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PIN FUNCTIONS(continued)

FUNCTION(1)DESCRIPTION

NAME PHD NO.DKD NO.

Power supply input for half bridges D requires close decoupling of2.2-μF PVDD_D30,3125,26P

capacitor to GND_D.

READY1919O Normal operation;open drain;active high

RESET24I Device reset Input;active low,requires47k?pull up resistor to VREG

SD1517O Shutdown signal,open drain,active low

Power supply for internal voltage regulator requires a10-μF capacitor with a VDD642P

0.1-μF capacitor to GND for decoupling.

VI_CM68O Analog comparator reference node requires close decoupling of1nF to GND VREG911P Internal regulator supply filter pin requires0.1-μF capacitor to GND

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TYPICAL SYSTEM BLOCK DIAGRAM

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AGND

OC_ADJ

VREG VDD

GVDD_A

GND

OUT_A

GND_A PVDD_A

BST_A GVDD_B

OUT_B GND_B

PVDD_B BST_B

GVDD_C OUT_C GND_C PVDD_C

BST_C GVDD_D

OUT_D

GND_D

PVDD_D

BST_D TAS5615

SLAS595A –JUNE 2009–REVISED SEPTEMBER https://www.doczj.com/doc/1f12364558.html,

FUNCTIONAL BLOCK DIAGRAM

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AUDIO CHARACTERISTICS(BTL)

PCB and system configuraton are in accordance with recommended guidelines.Audio frequency=1kHz,PVDD_X=50V, GVDD_X=12V,R L=8?,f S=400kHz,R OC=22k?,T C=75°C,Output Filter:L DEM=15μH,C DEM=680nF,mode=010, unless otherwise noted.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

R L=8?,10%THD+N,clipped output signal160

P O Power output per channel W

R L=8?,1%THD+N,unclipped output signal125

THD+N Total harmonic distortion+noise1W0.05%

A-weighted,AES17filter,Input Capacitor

V n Output integrated noise260μV

Grounded

|V OS|Output offset voltage Inputs AC coupled to AGND40150mV SNR Signal-to-noise ratio(1)100dB DNR Dynamic range100dB

P idle Power dissipation due to Idle losses(I PVDD_X)P O=0,4channels switching(2) 2.3W

(1)SNR is calculated relative to1%THD+N output level.

(2)Actual system idle losses also are affected by core losses of output inductors.

AUDIO SPECIFICATION(Single-Ended Output)

PCB and system configuraton are in accordance with recommended guidelines.Audio frequency=1kHz,PVDD_X=50V, GVDD_X=12V,R L=4?,f S=400kHz,R OC=22k?,T C=75°C,Output Filter:L DEM=15μH,C DEM=330nF,MODE=100, unless otherwise noted.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

R L=4?,10%THD+N,clipped output signal75

P O Power output per channel W

R L=4?,1%THD+N,unclipped output signal60

THD+N Total harmonic distortion+noise1W0.05%

V n Output integrated noise A-weighted350μV SNR Signale to noise ratio(1)A-weighted93dB DNR Dynamic range A-weighted93dB

P idle Power dissipation due to idle losses(I PVDD_X)P O=0,4channels switching(2) 1.15W

(1)SNR is calculated relative to1%THD+N output level.

(2)Actual system idle losses are affected by core losses of output inductors.

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SLAS595A–JUNE2009–REVISED https://www.doczj.com/doc/1f12364558.html,

AUDIO SPECIFICATION(PBTL)

PCB and system configuraton are in accordance with recommended guidelines.Audio frequency=1kHz,PVDD_X=50V, GVDD_X=12V,R L=4?,f S=400kHz,R OC=22k?,T C=75°C,Output Filter:L DEM=15μH,C DEM=680nF,MODE=

101-BD,unless otherwise noted.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

R L=4?,10%THD+N,clipped output signal300

R L=6?,10%THD+N,clipped output signal210

R L=8?,10%THD+N,clipped output signal160

P O Power output per channel W

R L=4?,1%THD+N,unclipped output signal240

R L=6?,1%THD+N,unclipped output signal160

R L=8?,1%THD+N,unclipped output signal125

THD+N Total harmonic distortion+noise1W0.05%

V n Output integrated noise A-weighted260μV SNR Signale to noise ratio(1)A-weighted100dB DNR Dynamic range A-weighted100dB

P idle Power dissipation due to idle losses(IPVDD_X)P O=0,4channels switching(2) 2.3W

(1)SNR is calculated relative to1%THD+N output level.

(2)Actual system idle losses are affected by core losses of output inductors.

ELECTRICAL CHARACTERISTICS

PVDD_X=50.0V,GVDD_X=12V,VDD=12V,T C(Case temperature)=75°C,f S=400kHz,unless otherwise specified.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT INTERNAL VOLTAGE REGULATOR AND CURRENT CONSUMPTION

Voltage regulator,only used as reference

VREG VDD=12V3 3.3 3.6V node

VI_CM Analog comparator reference node 1.5 1.75 1.9V

Operating,50%duty cycle22.5

IVDD VDD supply current mA

Idle,reset mode22.5

50%duty cycle8

I GVDD_x Gate-supply current per half-bridge mA

Reset mode 1.5

50%duty cycle without output filter or load7mA

I PVDD_x Half-bridge idle current

Reset mode,No switching610μA ANALOG INPUTS

R IN Input resistance READY=HIGH33k?

V IN Maximum input voltage swing5V

I IN Maximum input current342mA

G Voltage Gain(V OUT/V IN)23dB OSCILLATOR

Nominal,Master Mode 3.54 4.5

f OSC_IO+AM1,Master Mode F PWM×10 3.1 3.4 3.5MHz

AM2,Master Mode 2.63 3.2

V IH High level input voltage 1.86V

V IL Low level input voltage 1.45V OUTPUT-STAGE MOSFETs

Drain-to-source resistance,low side(LS)120200m?

T J=25°C,Includes metallization resistance,

R DS(on)

GVDD=12V

Drain-to-source resistance,high side(HS)120200m?

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ELECTRICAL CHARACTERISTICS(continued)

PVDD_X=50.0V,GVDD_X=12V,VDD=12V,T C(Case temperature)=75°C,f S=400kHz,unless otherwise specified.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT I/O PROTECTION

Undervoltage protection limit,GVDD_x

V uvp,G9.5V and VDD

V uvp,hyst(1)0.6V OTW1(1)Overtemperature warning195100105°C OTW2(1)Overtemperature warning2115125135°C Temperature drop needed below OTW

OTW HYST(1)temperture for OTW to be inactive after25°C OTW event.

OTE(1)Overtemperature error145155165°C

OTE-

OTE-OTW differential30°C OTW differential(1)

A reset needs to occur for SD to be

OTE HYST(1)25°C released following an OTE event

OLPC Overload protection counter f PWM=400kHz 1.3ms

Resistor–programmable,nominal

continious current in1?load,64Pin QFP10A

package(PHD),R OCP=22k?

I OC Overcurrent limit protection

Resistor–programmable,nominal

continious current in1?load,44Pin PSOP310A

package(DKD),R OCP=24k?

Resistor–programmable,continious current

I OC_LATCHED Overcurrent limit protection in1?load,10A

R OCP=47k?

Time from switching transition to flip-state

I OCT Overcurrent response time150ns

induced by overcurrent.

Connected when RESET is active to provide

I PD Output pulldown current of each half3mA

bootstrap charge.Not used in SE mode.

STATIC DIGITAL SPECIFICATIONS

V IH High level input voltage 1.9V

INPUT_X,M1,M2,M3,RESET

V IL Low level input voltage 1.45V Leakage Input leakage current100μA OTW/SHUTDOWN(SD)

Internal pullup resistance,OTW1to

R INT_PU202632k?VREG,OTW2to VREG,SD to VREG

Internal pullup resistor3 3.3 3.6

V OH High level output voltage V

External pullup of4.7k?to5V 4.55

V OL Low level output voltage I O=4mA200500mV

Device fanout OTW1,OTW2,SD,CLIP,

FANOUT No external pullup30devices READY

(1)Specified by design.

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PVDD - Supply Voltage - V

P - O u t p u t P o w e r - W

O P - Output Power - W

O T H D +N - T o t a l H a r m o n i c D i s t o r t i o n + N o i s e

- %

1501020

30405060708090100110120

130140P - O u t p u t P o w e r - W

O PVDD - Supply Voltage - V

2 Channels Output Power - W

010010203040506070

8090E f f i c i e n c y - %

TAS5615

SLAS595A –JUNE 2009–REVISED SEPTEMBER https://www.doczj.com/doc/1f12364558.html,

TYPICAL CHARACTERISTICS,BTL CONFIGURATION

TOTAL HARMONIC+NOISE

OUTPUT POWER

SUPPLY VOLTAGE

Figure 1.

Figure 2.UNCLIPPED OUTPUT POWER

SYSTEM EFFICIENCY

SUPPLY VOLTAGE

OUTPUT POWER

Figure 3.Figure 4.

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020

406080100120140160

180200

T - Case Temperature - °C

C P - O u t p u t P o w e r - W

2 Channels Output Power - W

342468101214161820222426283032P o w e r L o s s

- W

-160

0-140-120-100-80-60-40

-20f - Frequency - kHz N o i s e A m p l i t u d e - d B

TAS5615

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TYPICAL CHARACTERISTICS,BTL CONFIGURATION (continued)

SYSTEM POWER LOSS

OUTPUT POWER

CASE TEMPERATURE

Figure 5.

Figure 6.

NOISE AMPLITUDE

FREQUENCY

Figure 7.

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5101520253035404550

606570758085

PVDD - Supply Voltage - V

P - O u t p u t P o w e r - W

P - Output Power - W

O T H D +N - T o t a l H a r m o n i c D i s t o r t i o n + N o i s e - %

100

51015202530354045505560

70758085

P - O u t p u t P o w e r - W

O T - Case Temperature - °C

C TAS5615

SLAS595A –JUNE 2009–REVISED SEPTEMBER https://www.doczj.com/doc/1f12364558.html,

TYPICAL CHARACTERISTICS,SE CONFIGURATION

TOTAL HARMONIC DISTORTION +NOISE

OUTPUT POWER

SUPPLY VOLTAGE

Figure 8.

Figure 9.

OUTPUT POWER

CASE TEMPERATURE

Figure 10.

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PVDD - Supply Voltage - V

P - O u t p u t P o w e r - W

O T H D +N - T o t a l H a r m o n i c D i s t o r t i o n + N o i s e - %

P - Output Power - W

P - O u t p u t P o w e r - W

O T - Case Temperature - °C

C TAS5615

TYPICAL CHARACTERISTICS,PBTL CONFIGURATION

TOTAL HARMONIC DISTORTION +NOISE

OUTPUT POWER

SUPPLY VOLTAGE

Figure 11.

Figure 12.

OUTPUT POWER

CASE TEMPERATURE

Figure 13.

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APPLICATION INFORMATION

PCB MATERIAL RECOMMENDATION

FR-4Glass Epoxy material with2oz.(70μm)is recommended for use with the TAS5615.The use of this material can provide for higher power output,improved thermal performance,and better EMI margin(due to lower PCB trace inductance.

PVDD CAPACITOR RECOMMENDATION

The large capacitors used in conjunction with each full-bridge,are referred to as the PVDD Capacitors.These capacitors should be selected for proper voltage margin and adequate capacitance to support the power requirements.In practice,with a well designed system power supply,1000μF,63V will support more applications.The PVDD capacitors should be low ESR type because they are used in a circuit associated with high-speed switching.

DECOUPLING CAPACITOR RECOMMENDATIONS

In order to design an amplifier that has robust performance,passes regulatory requirements,and exhibits good audio performance,good quality decoupling capacitors should be used.In practice,X7R should be used in this application.

The voltage of the decoupling capacitors should be selected in accordance with good design practices. Temperature,ripple current,and voltage overshoot must be considered.This fact is particularly true in the selection of the2.2μF that is placed on the power supply to each half-bridge.It must withstand the voltage overshoot of the PWM switching,the heat generated by the amplifier during high power output,and the ripple current created by high power output.A minimum voltage rating of63V is required for use with a50.0V power supply.

SYSTEM DESIGN RECOMMENDATIONS

The following schematics and PCB layouts illustrate"best practices"in the use of the TAS5615.

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I N _L E F T _

I N _L E F T _R _R I G H T _I N _R I G H T /R E S E 2V )

P V D D

G N D TAS5615

Figure 14.Typical Differential Input BTL Application With BD Modulation Filters

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I N

I N /R E S E //O T /O T /C L R E A V D D (+12V )

V D D

O S C _I O S C _I D (+12V )

V D D (+12V D D

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SLAS595A –JUNE 2009–REVISED SEPTEMBER https://www.doczj.com/doc/1f12364558.html,

Figure 15.Typical Differential (2N)PBTL Application With BD Modulation Filters

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PVDD

10nF 10nF TAS5615

Figure 16.Typical SE Application

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I N _C E N T E R _N

I N _C E N T E R _P

I N _R I G H

I N _L E F /R E S E //O T /O T /C L R E 12V )

O S C _I O S C _I V D D (+12TAS5615

SLAS595A –JUNE 2009–REVISED SEPTEMBER https://www.doczj.com/doc/1f12364558.html,

Figure 17.Typical 2.1System Differential Input BTL and Unbalanced Input SE Application

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