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1 A Distributed Safety-Critical System for Real-Time Train Control

1 A Distributed Safety-Critical System for Real-Time Train Control
1 A Distributed Safety-Critical System for Real-Time Train Control

A Distributed Safety-Critical System for Real-Time Train Control

Anup K. Ghosh, Vikram Rana,

and Barry W. Johnson

Center for Semicustom Integrated Systems Department of Electrical Engineering

University of Virginia

Charlottesville, Virginia 22903

Joseph A. Profeta, III Union Switch and Signal, Incorporated

A Member of the Ansaldo Group

1000 Technology Drive

Pittsburgh, Pennsylvania 15237

tolerant applications, hardware redundancy is essential. In addition, the real-time requirements for the different train control applications vary from tens of milliseconds for car-borne functions to full seconds for wayside functions.

Current microprocessor-based train control systems employ different systems at the wayside and on-board trains that are usually incompatible. In addition, ad hoc methodologies to safety-critical design have been imple-mented in these systems to ensure safety and fault-tolerant operation, often without regard to analyzable safety or real-istic assumptions on the nature of faults in digital hardware. Section 2 summarizes current systems used in train control and their shortcomings.

A single open-systems architecture that supports both wayside and carborne train control functions using com-mercial off-the-shelf (COTS) components is presented in Section 3. The time-triggered executive used in this archi-tecture is discussed in Section 4. A concurrent veri?cation technique that enables calculable safety in a distributed system is described in Section 5. Results from modeling and simulating the architecture are presented in Section 6. The experimental prototype of the system architecture that executes a wayside train control application using the con-current veri?cation algorithm is described in Section 7 along with experimental results. The overall contributions of the paper are summarized in Section 8.

2. BACKGROUND

The railroad industry has been actively replacing elec-tromechanical relay-driven safety interlocking systems with microprocessor-controlled interlocking systems. Recent advances in train control applications have sophis-ticated processing requirements that demand fail-safe and sometimes fault-tolerant system architectures.

A safe failure occurs when the failure of a component in a processing system is detected and the effect of the fail-ure emerges as a safe-side operation [1]. In the railway application, the safe-side failures are de?ned for the out-puts of the controller. A safe-side failure for a switch is to leave it in the locked position. The safe-side failure of a sig-nal is to set it to red, so that a train will stop before entering a block. In carborne control applications, most failures can be made safe by stopping the train immediately. Unlike planes that are controlled by computers, stopping the train is a safe failure state. Safety is the probability that the train controller is working correctly or has failed in a safe state. Reliability is the probability that the train controller is operating correctly. In order to have a highly reliable sys-

tem, a fault-tolerant controller with hardware or software redundancy is necessary. A system designed strictly for safety, on the other hand, requires only a single processor architecture with concurrent error detection mechanisms that switch outputs into a safe state upon error detection.

Simplex processing systems for wayside applications are described in the literature [2] [3]. In the MICROLOK system [2], the safety of the controller is dependent upon the diagnostic checks that are executed. One major draw-back inherent in a diagnostic approach to safety is that the level of safety achieved by diagnostics is not easily quanti-?ed. Second, the amount of processing overhead necessary for the diagnostics can often be greater than the amount used for executing the application. This performance factor will ultimately limit its application. The VPI system [3] uses a coded-processor approach to checking the safety-critical interlocking equations of the wayside application. Under the assumption that errors are equally likely, the safety of the system can be quantitatively determined. Aside from this unrealistic assumption, another major drawback of this system is that it lacks a modular architec-ture to allow for expansion into a distributed system. Finally, no provision for fault-tolerance is designed in the architecture, which limits its application to the wayside problem.

Two multiprocessing architectures have also been developed for train control [1] [5] Both use hardware rep-lication for fault tolerance. Two drawbacks are inherent in hardware replication. First, the software is assumed to be correct. An error in the software will not be revealed by majority voting in hardware. Second, the expense of a hardware redundant strategy to safety-critical operation is many times the expense of a single processor solution.

The dependable computing system described in this paper employs information redundancy and a concurrent veri?cation technique to assure safety globally in a distrib-uted system. This approach reduces the hardware overhead associated with majority voting to achieve safety and per-mits quanti?able measures of safety. Furthermore, the modularity of the distributed system enables fault tolerant operation for applications that require high reliability and availability. The open-systems architecture is designed to maximize the use of commercial off the shelf (COTS) com-ponents to reduce developmental costs.

3. SYSTEM ARCHITECTURE

The architecture for the distributed system which exe-cutes a safety-critical train control application is depicted in Figure 1. The basic building blocks of this architecture are the processors, input/output modules, and the network interface unit (NIU), which are co-located in backplane card cages. The parallel bus backplane interconnects pro-cessors with local input/output modules. Processors com-municate with remote processors and I/O over the high-speed serial network via the network interface unit. The input modules are responsible for sensing data from the ?eld such as the state of a switch or presence of a train. The processors are responsible for executing the train control algorithm. Multiple processors can be placed in a single card cage to execute multiprocessing applications. Proces-sors may also be arranged in voting clusters to be used in for fault-tolerant operation.

The Fiber Distributed Data Interface (FDDI) network standard is used for inter-node communication. The latency and response time for data transmissions is bounded to sup-port real-time applications.The FDDI network protocol guarantees media access for all nodes connected to the net-work. In addition, the protocol enforces a bounded response time for each node connected to the network to ensure hang-ups do not disrupt operation.

4. I/O CYCLE CONSIDERATIONS

A software executive which resides on a controlling processor has been designed for this safety critical system [9]. The software executive implements a time-triggered paradigm for the system. System events such as writing outputs, writing input polls, and control equation evalua-tion are activated by the system executive at ?xed periodi-cal intervals of time. An input/output cycle is the basic unit of processing in the system, and the executive is designed around it. The executive is a single tasking kernal in which tasks are executed singly through procedural calls. Upon completing a task, control is returned to the executive ker-nel. The executive also runs non-critical routines until the end of a frame, at which time a context switch takes place, and the I/O cycle is repeated in the next frame [10].

The frame-based timing speci?cation used by the executive is typical in the avionics industry and elsewhere [11]. Tasks may need to execute every frame, every other frame, or at other frequencies. The system cycle represent-ing this scheduling approach for the train control applica-tion appears in Figure 2. Task P1 represents writing outputs and polling inputs at the beginning of each frame. In order to support deterministic updating of actuator devices, out-puts are written at the beginning of each frame. Input cards are also polled at the beginning of each frame. In this para-digm, the actuators and sensors are updated and sensed, respectively, at known periodic intervals. Task P2 repre-sents the time it takes for inputs to be read into the memory of the processor card. The processor begins executing the control equations at the beginning of P3. If all inputs have not arrived by this time, an error will be signaled, and safe shutdown will follow.Non-critical routines (P4) run in vari-able-length subframes determined by the amount of idle time in a frame and are the only processes that can be pre-empted or suspended. These routines include other non-critical functions such as passenger information, train scheduling, data processing, and diagnostic functions for maintenance. It should be noted that the diagram is only descriptive, not speci?c, and the number of frames and the number of tasks per frame vary based on the train control application.

In order to support determinism of system behavior, the system uses a static scheduling algorithm. Static sched-uling is simple to implement and its deterministic schedul-ing allows hard deadlines to be set and enforced through watchdog time-outs. One drawback of static scheduling is that it is not very ?exible in permitting new tasks to be included without re-design. However, the safety achieved from deterministic scheduling outweigh the bene?ts of ?exibility in scheduling.

5. GLOBAL SAFETY ASSURANCE

The primary dependability requirement in the wayside and carborne train control application is safety. In this sec-tion, we present a concept for global safety assurance in a distributed system to be used in safety-critical applications. This concept is currently implemented in an experimental test-bed prototype which is described brie?y in Section 7.

5.1Goals of Global Safety Assurance

A code-based approach to concurrent error detection and control algorithm veri?cation is employed in the sys-tem to implement global safety assurance. The goal of this method is to provide a quanti?able level of safety assur-ance over a distributed system. Unlike highly reliable sys-tems, safety-critical systems have the option of failing-safe, which in the case of this particular application means stopping the train. As a result, a desired approach to safety assurance could take advantage of a simplex controller without resorting to N-modular redundancy. A major dis-advantage of many N-modular redundant approaches, is that identical software is executed on all redundant com-puters. If the software is used for executing safety critical functions, or if it could introduce unsafe errors into the out-put of the system, then the software must be formally veri-?ed or assumed correct. Leveson [12] has concluded that it

is next to impossible to uncover all bugs in complex soft-ware. The safety assurance approach presented here uses a single control algorithm veri?cation methodology to detect errors arising from both hardware and software.

Since the set of all faults that can occur in hardware and software is considered in?nite, we check the manifes-tation of these faults as errors in the information domain [7]. The basic assumption of this approach is that all faults that can lead to system failure will manifest themselves as errors in the data that the computer processes. As a result, the system must be exercised frequently to minimize fault latency times and the data that is processed by the computer must be checked for errors before outputs are set.

5.2Concurrent Veri?cation of the Control Algorithm

Many error detection or voting systems implement bus-level voting mechanisms to vote on data every machine cycle [13]. This methodology requires tight syn-chronization of hardware and intimate knowledge of the hardware platform. V oting systems also assume that the software executing on redundant machines is correct and that design errors in processors that may cause simulta-neous errors do not exist.

In order to detect errors arising out of hardware and software for a generic computing platform, the problem of error detection is abstracted to the control application level. In the method presented here, the error checking mecha-nisms are not concerned with the speci?cs of the hardware platform, but rather with the control algorithm being exe-cuted Figure 3 depicts a distributed system composed of three main elements: inputs, a hardware/software (HW/ SW) computing platform, and outputs. An abstraction of the control algorithm is projected out from the hardware/ software computing platform in the lower box. A subset of the inputs into the system will consist of the input operands into the control algorithm. A subset of the outputs from the computing platform will also be output operands from the control algorithm.

The control algorithm can be described in the para-digm of a ?nite state machine (FSM). The outputs of the state machine which correspond to the outputs of the con-trol algorithm are a function of the input operands and internal state variables. The next states of the FSM are a function of the input operands and the current state of the FSM. For the wayside interlocking application, the control algorithm functions are Boolean operators. In most car-borne applications, the functions are arithmetic. The con-trol algorithm itself is a predetermined sequence of operations on the predetermined set of input operands and state variables. The a priori knowledge of which inputs and state variables are to be used in executing the pre-deter-mined equations permits concurrent veri?cation of algo-rithm execution. The safety assurance method is concerned only with the set of operands, next states, and outputs of the control algorithm. The set of all inputs, outputs and opera-tions in the computing platform is not of concern, unless errors in this superset manifest themselves as errors in the control algorithm subset.

5.3Checking in Safety Assurance Regions

A global approach to safety must consider errors that can arise in all parts of the system. These components include input modules, communication channels, processor units, and output modules. Each component in a distributed system is considered a safety assurance region. All errors that arise in a safety assurance region must be detected by error detection mechanisms and prevented from propagat-ing into other regions. The safety assurance region is anal-ogous to fault containment regions used in some highly reliable systems [13].

Using a code-based approach for error detection allows an upper bound on the probability for undetected errors to be calculated. This calculation is necessary for determining the coverage of all errors and ultimately the safety of the system. Input data to the control algorithm are read by input sensors at the input cards. The input sensor themselves must be vital according to railway standards. Once sensed, the ?eld data is encoded with an identity and time stamp in a cyclic code. The identity and time stamp are used by the concurrent veri?cation algorithm to detect referencing and timing errors. A cyclic code is used in order to assure good random and burst error detection capa-bility. Once encoded, this data can be checked before leav-ing the input module safety assurance region. Checking must be performed at the interfaces of the safety assurance regions.

The communication media of the architecture is also a safety assurance region. Data from input cards and proces-sors are encoded in a cyclic code before being transmitted over the network. Data is checked at the interface to the destination upon arrival. Loss of data is detected by incom-plete data sets and late data error conditions are detected watchdog time-outs. The output cards need only to verify that the output data codeword is uncorrupted, the time stamp is correct for the current cycle, and the identity of the codeword corresponds to the output channel.

Representing the control application as a ?nite state machine allows every state that is calculated by the algo-rithm to be checked concurrently. The concurrent veri?ca-tion algorithm knows a priori the identities of the inputs, the sequence of operations, and the identities of the state variables and outputs for the control algorithm. With this knowledge and the constraint that the processor execute the control algorithm in a predetermined sequential fashion, the control algorithm can verify that the correct input oper-ands for the current cycle were used and uncorrupted, that the correct operation was executed, and the correct output identity was encoded with the output operand. In addition, the concurrent veri?cation algorithm checker must be able to verify that the operation executed correctly. The algo-rithm checker is able to verify that the primary outputs and the next states were calculated correctly by diversely checking that the resulting output is a correct functional map from the inputs and operation type. Other train control applications such as input ?ltering, output ?ltering, and command feedback can be represented and checked simi-larly.

The concurrent veri?cation algorithm outlined for each of the safety assurance regions provides global safety assurance by detecting errors in hardware and software. Once an error is detected, a fail-safe shutdown is required. The safety assurance method is designed to check a single processor unit executing the control application. The checking algorithm can be implemented in a small number of semi-custom integrated circuit chips which will pas-sively monitor the processor-memory bus to capture the necessary operands. Alternatively, the algorithm can be programmed on another processor card which will execute the concurrent veri?cation algorithm on data received from the primary processor card. In these cases, the probability of an error occurring simultaneously in both the primary processor and the checker card that results in an unsafe fail-ure is analyzable through near-coincident fault analysis based on assumed failure rates for both cards.

to the overhead associated with delievering a packet for 256 I/O channels. Therefore, the performance of the I/O subsystem for remote calls will jump on packet boundaries. In this experiment, however, all packets are sent in pairs. As a result, the performance of the I/O subsystem jumps on pairs of packets which can hold enough data for 512 I/O channels. Therefore the I/O response time is approximately constant during each interval of 512 I/O channels and jumps at the next interval.

The main conclusion that can be drawn from this graph is that the I/O response time is much worse for remote transactions over the FDDI network than it is for local transactions over the VME backplane. A performance anal-ysis of the I/O transactions determined that the primary bottleneck in transmitting packets remotely is in the soft-ware driver for the FDDI network [16]. In contrast, local transactions on the VME backplane are performed through simple memory-mapped reads and writes to the local I/O devices.

A hardware fault-injection module for the prototype has been developed and is currently being integrated with the executive processor. The fault-injection unit will inject errors into the 68040 CPU concurrently with execution of the control application. The goal of fault injection is to experimentally determine the effectiveness of the safety assurance methodology in the presence of errors.

8. SUMMARY AND CONCLUSIONS

This paper presented an architecture and safety assur-ance methodology to be used in a distributed control sys-tem executing a safety-critical application. The architecture is designed to support train control applica-tions that require fail-safe and fault-tolerant operation. The architecture and safety assurance methodology de?ned in this paper overcomes many of the current limitations in existing train control systems. The architecture provides ?exibility in terms of expanding the system by adding COTS processors and I/O devices. The safety assurance methodology provides calculable safety for a distributed system controlled by a single processor. This method uses a deterministic timing paradigm for execution and a control algorithm veri?cation method to detect errors arising from hardware and software concurrently. The safety assurance methodology allows signi?cant savings in both redundant hardware costs and software veri?cation.

Results from simulating indicate the impact on net-work latency and response time for larger con?gurations of the system. The system architecture and safety assurance method is currently implemented in an experimental test-bed prototype. The experimental results showed the impact on the I/O response time due to the FDDI driver and pack-etization overhead. Future work will focus on simulated and experimental fault injection for dependability analysis.

9. ACKNOWLEDGMENTS

We would like to acknowledge the contributions of Douglass Lamb to Section 4 on I/O Cycle considerations and Paul Perrone to Section 5 on global safety assurance methodology.

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通止规,是量规的一种。作为度量标准,用于大批量的检验产品。 通止规是量具的一种,在实际生产批量的产品若采取用计量量具(如游标卡尺,千分表等有刻度的量具)逐个测量很费事.我们知道合格的产品是有一个度量围的.在这个围的都合格,所以人们便采取通规和止规来测量. 通止规种类 (一)对统一英制螺纹,外螺纹有三种螺纹等级:1A、2A和3A级,螺纹有三种等级:1B、2B和3B级,全部都是间隙配合。等级数字越高,配合越紧。在英制螺纹中,偏差仅规定1A和2A级,3A级的偏差为零,而且1A和2A级的等级偏差是相等的等级数目越大公差越小,如图所示:1B 2B 3B 螺纹基本中径3A 外螺纹2A 1A 1、1A和1B级,非常松的公差等级,其适用于外螺纹的允差配合。 2、2A和2B级,是英制系列机械紧固件规定最通用的螺纹公差等级。 3、3A和3B级,旋合形成最紧的配合,适用于公差紧的紧固件,用于安全性的关键设计。 4、对外螺纹来说,1A和2A级有一个配合公差,3A级没有。1A级公差比2A级公差大50,比3A级大75,对螺纹来说,2B级公差比2A公差大30。1B级比2B级大50,比3B级大75。 (二)公制螺纹,外螺纹有三种螺纹等级:4h、6h和6g,螺纹有三种螺纹等级:5H、6 H、7H。(日标螺纹精度等级分为I、II、III三级,通常状况下为II级)在公制螺纹中,H 和h的基本偏差为零。G的基本偏差为正值,e、f和g的基本偏差为负值。如图所示:公差G H 螺纹偏差基本中径外螺纹f g h e 1、H是螺纹常用的公差带位置,一般不用作表面镀层,或用极薄的磷化层。G位置基本偏差用于特殊场合,如较厚的镀层,一般很少用。 2、g常用来镀6-9um的薄镀层,如产品图纸要6h的螺栓,其镀前螺纹采用6g的公差带。 3、螺纹配合最好组合成H/g、H/h或G/h,对于螺栓、螺母等精制紧固件螺纹,标准推荐采用6H/6g的配合。 (三)螺纹标记M10×1–5g 6g M10×1–6H 顶径公差代号中径和顶径公差代号(相同)中径公差代号。 通止规是两个量具分为通规和止规.举个例子:M6-7h的螺纹通止规一头为通规(T)如果能顺利旋进被测螺纹孔则为合格,反之不合格需返工(也就是孔小了).然后用止规(Z)如果能顺利旋进被测螺纹孔2.5圈或以上则为不合格反之合格.且此时不合格的螺纹孔应报废,不能进行返工了.其中2.5圈为国家标准,若是出口件最多只能进1.5圈(国际标准).总之通规过止规不过为合格,通规止规都不过或通规止规都过则为不合格。

boring 令人厌烦的

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一、故事引入 杜牧的《清明》一诗“清明时节雨纷纷,路上行人欲断魂。借问酒家何处有,牧童遥指杏花村。”大家都很熟悉,但如果把标点符号改动一下,就成了另一作品。有人巧妙短句将其改成了一首词:“清明时节雨,纷纷路上,行人欲断魂。借问酒家何处?有牧童遥指,杏花村。”还有人改成了一首优美隽永的散文:“清明时节,雨纷纷。路上,行人欲断魂。借问酒家:“何处有牧童?”遥指杏花村。 又如,常有人在一路边大小便,有人就在那立了块牌子:过路人等不得在此大小便。立牌人的本意是:“过路人等,不得在此大小便。”可没有点标点符号,于是被人认为是:“过路人,等不得,在此大小便。” 类似的故事不胜枚举,诸如一客栈“下雨天留客天留我不留”的对联,祝枝山写给一财主的对联“今年正好晦气全无财富进门”。可见,标点符号的作用举足轻重。语文课程标准对小学各阶段学生应该掌握的标点符号作了明确的规定和说明。因此,作为小学语文教师,不但要咬文嚼字,教会学生正确使用标点符号也不容忽视。下面,我就简单谈谈一些易错的标点符号的用法。 二、易错标点符号的用法例谈 (一)问号 1、非疑问句误用问号 如:他问你明天去不去公园。虽然“明天去不去公园”是一个疑问,但这个问句在整个句子中已经作了“问”的宾语,而整个句

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2、大炖盅双重内盖设计 大炖盅采用双重内盖设计,炖汤过程中,能减少炖品温度的散发,避免营养与食品香气的流失。汤汁受热到位,骨酥肉嫩,香气浓郁,口感更好。 3、机身水位显示窗设计 在机身外侧就能观察到机身水箱内的水位情况,能实时了解水箱内水位,更加方便直接。

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螺纹通止规要求螺纹通规通

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只能检测工件螺纹的中径 yg196733456 (2009-4-03 09:15:56)原来是测中径的知道了

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通止规的用法及管理

通止规的用法及管理 令狐采学 1、止规 使用前:应经相关检验计量机构检验计量合格后,方可投入生产现场使用。 使用时:应注意被测螺纹公差等级及偏差代号与环规标识公差等级、偏差代号相同(如M24*1.56h与M24*1.55g两种环规外形相同,其螺纹公差带不相同,错用后将产生批量不合格品)。 检验测量过程:首先要清理干净被测螺纹油污及杂质,然后在环规与被测螺纹对正后,用大母指与食指转动环规,旋入螺纹长度在2个螺距之内为合格,否则判为不合格品。 2、通规 使用前:应经相关检验计量机构检验计量合格后,方可投入生

产现场使用。 使用时:应注意被测螺纹公差等级及偏差代号与环规标识的公差等级、偏差代号相同(如M24*1.56h与M24*1.55g两种环规外形相同,其螺纹公差带不相同,错用后将产生批量不合格品)。 检验测量过程:首先要清理干净被测螺纹塞规油污及杂质,然后在环规与被测螺纹对正后,用大母指与食指转动环规,使其在自由状态下旋合通过螺纹全部长度判定合格,否则以不通判定。 3、注意事项 在用量具应在每个工作日用校对塞规计量一次。经校对塞规计量超差或者达到计量器具周检期限的环规,由计量管理人员收回、标识隔离并作相应的处理措施。 可调节螺纹环规经调整后,测量部位会产生失圆,此现象由计量修复人员经螺纹磨削加工后再次计量鉴定,各尺寸合格后方

可投入使用。 报废环规应标识隔离并及时处理,不得流入生产现场。 4、维护与保养 量具(环规)使用完毕后,应及时清理干净测量部位附着物,存放在规定的量具盒内。生产现场在用量具应摆放在工艺定置位置,轻拿轻放,以防止磕碰而损坏测量表面。 严禁将量具作为切削工具强制旋入螺纹,避免造成早期磨损。可调节螺纹环规严禁非计量工作人员随意调整,确保量具的准确性。环规长时间不用,应交计量管理部门妥善保管。

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