AT89C51外文翻译
Description
The AT89C51 is a low-power, high-performance CMOS 8-bit microcomputer with 4K bytes of Flash Programmable and Erasable Read Only Memory (PEROM). The device is manufactured using Atmel’s high density nonvolatile memory technology and is compatible with the industry standard MCS-51? instruction-set and pinout. The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with Flash on a monolithic chip, the Atmel AT89C51 is a powerful microcomputer which provides a highly flexible and cost effective solution to many embedded control applications.
Features
? Compatible with MCS-51? Products
? 4K Bytes of In-System Reprogrammable Flash Memory
– Endurance: 1,000 Write/Erase Cycles
? Fully Static Operation: 0 Hz to 24 MHz
? Three-Level Program Memory Lock
? 128 x 8-Bit Internal RAM
? 32 Programmable I/O Lines
? Two 16-Bit Timer/Counters
? Six Interrupt Sources
? Programmable Serial Channel
? Low Power Idle and Power Down Modes
The AT89C51 provides the following standard features: 4K bytes of Flash,128 bytes of RAM, 32 I/O lines, two 16-bit timer/counters, a five vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator and clock circuitry. In addition, the AT89C51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port and interrupt system to continue functioning. The Power-down Mode saves the RAM contents but freezes the oscillator disabling all other chip functions until the next hardware reset.
VCC
Supply voltage.
GND
Ground.
Port 0
Port 0 is an 8-bit open-drain bi-directional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high-impedance inputs.
Port 0 may also be configured to be the multiplexed low-order address/data bus during accesses to external program and data memory. In this mode P0 has internal pullups. Port 0 also receives the code bytes during Flash programming, and outputs the code bytes during program verification. External pullups are required during program verification.
Port 1
Port 1 is an 8-bit bi-directional I/O port with internal pullups.The Port 1 output buffers can sink/source four TTL inputs.When 1s are written to Port 1 pins they are pulled high by the internal pullups and can be used as inputs. As inputs,Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pullups.Port 1 also receives the low-order address bytes during Flash programming and verification.
Port 2
Port 2 is an 8-bit bi-directional I/O port with internal pullups.The Port 2 output buffers can sink/source four TTL inputs.When 1s are written to Port 2 pins they are pulled high by the internal pullups and can be used as inputs. As inputs,Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pullups. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @DPTR). In this application, it uses strong internal pullups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives the high-order address bits and some control signals during Flash programming and verification.
Port 3
Port 3 is an 8-bit bi-directional I/O port with internal pullups. The Port 3 output buffers can sink/source four TTL inputs.When 1s are written to Port 3 pins they are
pulled high by the internal pullups and can be used as inputs. As inputs,Port 3 pins that are externally being pulled low will source current (IIL) because of the pullups. Port 3 also serves the functions of various special features of the AT89C51 as listed below:
Port 3 also receives some control signals for Flash programming and verification. RST
Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device.
ALE/PROG
Address Latch Enable output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming. In normal operation ALE is emitted at a constant rate of 1/6 the oscillator frequency, and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external Data Memory.
If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode.
PSEN
Program Store Enable is the read strobe to external program memory. When the AT89C51 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory.
EA/VPP
External Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to
FFFFH.Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset. EA should be strapped to VCC for internal program executions.This pin also receives the 12-volt programming enable voltage (VPP) during Flash programming, for parts that require 12-volt VPP.
XTAL1
Input to the inverting oscillator amplifier and input to the internal clock operating circuit.
XTAL2
Output from the inverting oscillator amplifier.Oscillator Characteristics
XTAL1 and XTAL2 are the input and output, respectively,of an inverting amplifier which can be configured for use as an on-chip oscillator, as shown in Figure 1. Either a quartz crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 2.There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum voltage high and low time specifications must be observed.
Idle Mode
In idle mode, the CPU puts itself to sleep while all the on-chip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the special functions registers remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset. It should be noted that when idle is terminated by a hard ware reset, the device normally resumes program execution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory.
Figure 1. Oscillator Connections
Note: C1, C2 = 30 pF ± 10 pF for Crystals= 40 pF ± 10 pF for Ceramic Resonators
Figure 2. External Clock Drive Configuration
Power-down Mode
In the power-down mode, the oscillator is stopped, and the instruction that invokes power-down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values until the power-down mode is terminated. The only exit from power-down is a hardware reset. Reset redefines the SFRs but does not change the on-chip RAM. The reset should not be activated before VCC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize.
Program Memory Lock Bits
On the chip are three lock bits which can be left unprogrammed (U) or can be programmed (P) to obtain the additional features listed in the table below.When lock bit 1 is programmed, the logic level at the EA pin is sampled and latched during reset.
If the device is powered up without a reset, the latch initializes to a random value, and holds that value until reset is activated. It is necessary that the latched value of EA be in agreement with the current logic level at that pin in order for the device to function properly.
Programming the Flash
The AT89C51 is normally shipped with the on-chip Flash memory array in the erased state (that is, contents = FFH)and ready to be programmed. The programming interface accepts either a high-voltage (12-volt) or a low-voltage (VCC) program enable signal. The low-voltage programming mode provides a convenient way to program the AT89C51 inside t he user’s system, while the high-voltage programming mode is compatible with conventional thirdparty Flash or EPROM programmers.The AT89C51 is shipped with either the high-voltage or low-voltage programming mode enabled. The respective top-side marking and device signature codes are listed in the following table.
The AT89C51 code memory array is programmed byte-by-byte in either programming mode. To program any non-blank byte in the on-chip Flash Memory, the entire memory must be erased using the Chip Erase Mode. Programming Algorithm: Before programming the AT89C51, the address, data and control signals should be set up according to the Flash programming mode table and Figures 3 and 4. To program the AT89C51, take the following steps.
1. Input the desired memory location on the address lines.
2. Input the appropriate data byte on the data lines.
3. Activate the correct combination of control signals.
4. Raise EA/VPP to 12V for the high-voltage programming mode.
5. Pulse ALE/PROG once to program a byte in the Flash array or the lock bits. The byte-write cycle is self-timedand typically takes no more than 1.5 ms. Repeat steps 1 through 5, changing the address and data for the entire array or until the end of the object file is reached.
Data Polling: The AT89C51 features Data Polling to indicate the end of a write cycle. During a write cycle, an
attempted read of the last byte written will result in the complement of the written datum on PO.7. Once the write cycle has been completed, true data are valid on all outputs, and the next cycle may begin. Data Polling may begin any time after a write cycle has been initiated.
Ready/Busy: The progress of byte programming can also be monitored by the RDY/BSY output signal. P3.4 is pulled low after ALE goes high during programming to indicate BUSY. P3.4 is pulled high again when programming is done to indicate READY.
Program Verify: If lock bits LB1 and LB2 have not been programmed, the programmed code data can be read back via the address and data lines for verification. The lock bits cannot be verified directly. Verification of the lock bits is achieved by observing that their features are enabled.
Chip Erase: The entire Flash array is erased electrically by using the proper combination of control signals and by holding ALE/PROG low for 10 ms. The code array is written with all ―1‖s. The chip erase operation must be executed before the code memory can be re-programmed.
Reading the Signature Bytes: The signature bytes are read by the same procedure as a normal verification of locations 030H, 031H, and 032H, except that P3.6 and P3.7 must be pulled to a logic low. The values returned are as follows.
(030H) = 1EH indicates manufactured by Atmel
(031H) = 51H indicates 89C51
(032H) = FFH indicates 12V programming
(032H) = 05H indicates 5V programming
Programming Interface
Every code byte in the Flash array can be written and the entire array can be erased by using the appropriate combination of control signals. The write operation cycle is selftimed and once initiated, will automatically time itself to completion.
All major programming vendors offer worldwide support for the Atmel
microcontroller series. Please contact your local programming vendor for the appropriate software revision.
Flash Programming and Verification Waveforms - High-voltage Mode (VPP = 12V)
Flash Programming and Verification Waveforms - Low-voltage Mode (VPP = 5V)
Flash Programming and Verification Characteristics TA = 0°C to 70°C, VCC = 5.0 ±10%
Absolute Maximum Ratings*
*NOTICE: Str esses beyond those listed under ―Absolute Maximum Ratings‖ may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC Characteristics
TA = -40°C to 85°C, VCC = 5.0V ±20% (unless otherwise noted)
Notes: 1. Under steady state (non-transient) conditions, IOL must be externally limited as follows:
Maximum IOL per port pin: 10 mA
Maximum IOL per 8-bit port: Port 0: 26 mA
Ports 1, 2, 3: 15 mA
Maximum total IOL for all output pins: 71 mA
If IOL exceeds the test condition, VOL may exceed the related specification. Pins are
not guaranteed to sink current greater than the listed test conditions.
2. Minimum VCC for Power-down is 2V.
AC Characteristics
Under operating conditions, load capacitance for Port 0, ALE/PROG, and PSEN = 100 pF; load capacitance for all other outputs = 80 pF.
External Program and Data Memory Characteristics
External Program Memory Read Cycle
External Data Memory Read Cycle
External Data Memory Write Cycle
External Clock Drive Waveforms
External Clock Drive
Serial Port Timing: Shift Register Mode Test Conditions (VCC = 5.0 V ±20%; Load Capacitance = 80 pF)
Shift Register Mode Timing Waveforms
AC Testing Input/Output Waveforms(1)
Note: 1. AC Inputs during testing are driven at VCC - 0.5V for a logic 1 and 0.45V for a logic 0. Timing measurements are made at VIH min. for a logic 1 and VIL max. for a logic 0.Float Waveforms(1)
Note: 1. For timing purposes, a port pin is no longer floating when a 100mV change from load voltage occurs. A port pin begins to float when 100mV change from the loaded VOH/VOL level occurs.
AT89C51中文原文
AT89C51是美国ATMEL公司生产的低电压，高性能CMOS8位单片机，片内含4k bytes的可反复擦写的只读程序存储器（PEROM）和128 bytes的随机存取数据存储器（RAM），器件采用ATMEL公司的高密度、非易失性存储技术生产，兼容标准MCS-51指令系统，片内置通用8位中央处理器（CPU）和Flash存储单元，功能强大AT89C51单片机可为您提供许多高性价比的应用场合，可灵活应用于各种控制领域。
主要性能参数：
·与MCS-51产品指令系统完全兼容
·4k字节可重擦写Flash闪速存储器
·1000次擦写周期
·全静态操作：0Hz－24MHz
·三级加密程序存储器
·128×8字节内部RAM
·32个可编程I／O口线
·2个16位定时／计数器
·6个中断源
·可编程串行UART通道
·低功耗空闲和掉电模式
功能特性概述：
AT89C51 提供以下标准功能：4k 字节
Flash 闪速存储器，128字节内部RAM，32 个I／O 口线，两个16位定时／计数器，一个5向量两级中断结构，一个全双工串行通信口，片内振荡器及时钟电路。同时，AT89C51可降至0Hz的静态逻辑操作，并支持两种软件可选的节电工作模式。空闲方式停止CPU的工作，但允许RAM，定时／计数器，串行通信口及中断系统继续工作。掉电方式保存RAM中的内容，但振荡器停止工作并禁止其它所有部件工作直到下一个硬件复位。
引脚功能说明
·Vcc：电源电压
·GND：地
·P0 口：P0 口是一组8 位漏极开路型双向I／O 口，也即地址／数据总线复用口。作为输出口用时，每位能吸收电流的方式驱动8个TTL逻辑门电路，对端口写―1‖可作为高阻抗输入端用。在访问外部数据存储器或程序存储器时，这组口线分时转换地址（低8位）和数据总线复用，在访问期间激活内部上拉电阻。
在FIash编程时，P0口接收指令字节，而在程序校验时，输出指令字节，校验时，要求外接上拉电阻。
·P1口：P1是一个带内部上拉电阻的8位双向I／O口，P1的输出缓冲级可驱动（吸收或输出电流）4个TTL逻辑
门电路。对端口写―1‖，通过内部的上拉电阻把端口拉到高电平，此时可作输入口。作输入口使用时，因为内部存在上拉电阻，某个引脚被外部信号拉低时会输出一个电流（IIL）。FIash编程和程序校验期间，P1接收低8位地址。
·P2口：P2是一个带有内部上拉电阻的8位双向I／O口，P2的输出缓冲级可驱动（吸收或输出电流）4个TTL逻辑门电路。对端口写―1‖，通过内部的上拉电阻把端口拉到高电平，此时可作输入口，作输入口使用时，因为内部存在上拉电阻，某个引脚被外部信号拉低时会输出一个电流（IIL）。在访问外部程序存储器或16位地址的外部数据存储器（例如执行MOVX@DPTR指令）时，P2口送出高8位地址数据。在访问8 位地址的外部数据存储器（如执行MOVX@RI 指令）时，P2 口线上的内容（也即特殊功能寄存器（SFR）区中R2寄存器的内容），在整个访问期间不改变。
Flash编程或校验时，P2亦接收高位地址和其它控制信号。
·P3口：P3口是一组带有内部上拉电阻的8 位双向I／O 口。P3 口输出缓冲级可驱动（吸收或输出电流）4 个TTL逻辑门电路。对P3 口写入―1‖时，它们被内部上拉电阻拉高并可作为输入端口。作输入端时，被外部拉低的P3 口将用上拉电阻输出电流（IIL）。P3口除了作为一般的I／O口线外，更重要的用途是它的第二功能，如下表所示：
P3口还接收一些用于Flash闪速存储器编程和程序校验的控制信号。
·RST：复位输入。当振荡器工作时，RST引脚出现两个机器周期以上高电平将使单片机复位。
·ALE／PROG：当访问外部程序存储器或数据存储器时，ALE（地址锁存允许）输出脉冲用于锁存地址的低8位字节。即使不访问外部存储器，ALE 仍以时钟振荡频率的l／6 输出固定的正脉冲信号，因此它可对外输出时钟或用于定时目的。要注意的是：每当访问外部数据存储器时将跳过一个ALE脉冲。对Flash 存储器编程期间，该引脚还用于输入编程脉冲（PROG）。如有必要，可通过对特殊功能寄存器（SFR）区中的8EH单元的DO 位置位，可禁止ALE 操作。该位置位后，只有一条MOVX和MOVC指令ALE才会被激活。此外，该引脚会被微弱拉高，单片机执行外部程序时，应设置ALE无效。
·PSEN：程序储存允许（PSEN）输出是外部程序存储器的读选通信号，当AT89C51 由外部程序存储器取指令（或数据）时，每个机器周期两次PSEN有效，即输出两个脉冲。在此期间，当访问外部数据存储器，这两次有效的PSEN信号不出现。
·EA／VPP：外部访问允许。欲使CPU仅访问外部程序存储器（地址为0000H—FFFFH），EA端必须保持低电平（接地）。需注意的是：如果加密位LB1被编程，复位时内部会锁存EA端状态。如EA端为高电平（接VCC端），CPU则执行内部程序存储器中的指令。Flash存储器编程时，该引脚加上+12V的编程允许电源Vpp，当然这必须是该器件是使用12V编程电压Vpp。
·XTAL1：振荡器反相放大器的及内部时钟发生器的输入端。
·XTAL2：振荡器反相放大器的输出端。
·时钟振荡器：AT89C5l 中有一个用于构成内部振荡器的高增益反相放大器，引脚XTAL1 和XTAL2 分别是该放大器的输入端和输出端。这个放大器与作为反馈元件的片外石英晶体或陶瓷谐振器一起构成自激振荡器，振荡电路参见图5。外接石英晶体（或陶瓷谐振器）及电容C1、C2接在放大器的反馈回路中构成并联振荡电路。对外接电容C1、C2虽然没有十分严格的要求，但电容容量的大小
会轻微影响振荡频率的高低、振荡器工作的稳定性、起振的难易程序及温度稳定性，如果使用石英晶体，我们推荐电容使用30pF±10pF，而如使用陶瓷谐振器建议选择40pF±10F。用户也可以采用外部时钟。采用外部时钟的电路如图5右图所示。这种情况下，外部时钟脉冲接到XTAL1端，即内部时钟发生器的输入端，XTAL2则悬空。由于外部时钟信号是通过一个2分频触发器后作为内部时钟信号的，所以对外部时钟信号的占空比没有特殊要求，但最小高电平持续时间和最大的低电平持续时间应符合产品技术条件的要求。
·空闲节电模式：
AT89C51 有两种可用软件编程的省电模式，它们是空闲模式和掉电工作模式。这两种方式是控制专用寄存器PCON（即电源控制寄存器）中的PD（PCON.1）和IDL（PCON.0）位来实现的。PD 是掉电模式，当PD=1 时，激活掉电工作模式，单片机进入掉电工作状态。IDL是空闲等待方式，当IDL=1，激活空闲工作模式，单片机进入睡眠状态。如需同时进入两种工作模式，即PD和IDL同时为1，则先激活掉电模式。
在空闲工作模式状态，CPU保持睡眠状态而所有片内的外设仍保持激活状态，这种方式由软件产生。此时，片内RAM和所有特殊功能寄存器的内容保持不变。空闲模式可由任何允许的中断请求或硬件复位终止。
终止空闲工作模式的方法有两种，其一是任何一条被允许中断的事件被激活，IDL（PCON.0）被硬件清除，即刻终止空闲工作模式。程序会首先响应中断，进入中断服务程序，执行完中断服务程序并紧随RETI（中断返回）指令后，下一条要执行的指令就是使单片机进入空闲模式那条指令后面的一条指令。
其二是通过硬件复位也可将空闲工作模式终止。需要注意的是，当由硬件复位来终止空闲工作模式时，CPU 通常是从激活空闲模式那条指令的下一条指令开始继续执行程序的，要完成内部复位操作，硬件复位脉冲要保持两个机器周期（24个时钟周期）有效，在这种情况下，内部禁止CPU访问片内RAM，而允许访问其它端口。为了避免可能对端口产生意外写入，激活空闲模式的那条指令后一条指令不应是一条对端口或外部存储器的写入指令。
·掉电模式：
在掉电模式下，振荡器停止工作，进入掉电模式的指令是最后一条被执行的指令，片内RAM 和特殊功能寄存器的内容在终止掉电模式前被冻结。退出掉电模式的唯一方法是硬件复位，复位后将重新定义全部特殊功能寄存器但不改变RAM中的内容，在Vcc恢复到正常工作电平前，复位应无效，且必须保持一定时间以使振荡器重启动并稳定工作。
空闲和掉电模式外部引脚状态
·程序存储器的加密：
AT89C51 可使用对芯片上的3 个加密位LB1、LB2、LB3 进行编程（P）或不编程（U）来得到如下表所示的功能加
密位保护功能表：
注：表中的U —表示未编程，P —表示编程
当加密位LB1 被编程时，在复位期间，EA端的逻辑电平被采样并锁存，如果单片机上电后一直没有复位，则锁存起的初始值是一个随机数，且这个随机数会一直保存到真正复位为止。为使单片机能正常工作，被锁存的EA 电平值必须与该引脚当前的逻辑电平一致。此外，加密位只能通过整片擦除的方法清除。·Flash闪速存储器的编程：
AT89C51 单片机内部有4k 字节的Flash PEROM，这个Flash 存储阵列出厂时已处于擦除状态（即所有存储单元的内容均为FFH），用户随时可对其进行编程。编程接口可接收高电压（+12V）或低电压（Vcc）的允许编程信号。低电压编程模式适合于用户在线编程系统，而高电压编程模式可与通用EPROM编程器兼容。
AT89C51单片机中，有些属于低电压编程方式，而有些则是高电压编程方式，用户可从芯片上的型号和读取芯片内的名字节获得该信息，见下表。
AT89C51的程序存储器阵列是采用字节写入方式编程的，每次写入一个字节，要对整个芯片内的PEROM程序存储器写入一个非空字节，必须使用片擦除
的方式将整个存储器的内容清除。
·编程方法：
编程前，须按表6和图6所示设置好地址、数据及控制信号。编程单元的地址加在P1口和P2口的P2.0－P2.3（11位地址范围为0000H－0FFFH），数据从P0口输入，引脚P2.6、P2.7和P3.6、P3.7的电平设置见表6，PSEN为低电平，RST保持高电平，EA／Vpp 引脚是编程电源的输入端，按要求加上编程电压，ALE／PROG 引脚输入编程脉冲（负脉冲）。编程时，可采用4－20MHz的时钟振荡器，AT89C51编程方法如下：
1．在地址线上加上要编程单元的地址信号。
2．在数据线上加上要写入的数据字节。
3．激活相应的控制信号。
4．在高电压编程方式时，将EA／Vpp端加上+12V编程电压。
5．每对Flash存储阵列写入一个字节或每写入一个程序加密位，加上一个ALE／PROG编程脉冲。改变编程单元的地址和写入的数据，重复1—5步骤，直到全部文件编程结束。每个字节写入周期是自身定时的，通常约为1.5ms。
·数据查询：
AT89C51单片机用数据查询方式来检测一个写周期是否结束，在一个写周期中，如需读取最后写入的那个字节，则读出的数据的最高位（P0.7）是原来写入字节最高位的反码。写周期完成后，有效的数据就会出现在所有输出端上，此时，可进入下一个字节的写周期，写周期开始后，可在任意时刻进行数据查询。
·Ready／Busy：字节编程的进度可通过RDY／BSY输出信号监测，编程期间，ALE变为高电平―H‖后P3.4（RDY
／BSY）端电平被拉低，表示正在编程状态（忙状态）。编程完成后，P3.4变为高电平表示准备就绪状态。
·程序校验：如果加密位LB1、LB2没有进行编程，则代码数据可通过地址和数据线读回原编写的数据，采用下图的电路，程序存储器的地址由P1 和P2 口的P2.0－P2.3输入，数据由P0口读出，P2.6、P2.7和P3.6、P3.7的控制信号见表6，PSEN 保持低电平，ALE、EA和RST保持高电平。校验时，P0口须接上10k左右的上拉电阻。
表6 Flash 存储器编程真值表
AT89C51外文翻译 Description The AT89C51 is a low-power, high-performance CMOS 8-bit microcomputer with 4K bytes of Flash Programmable and Erasable Read Only Memory (PEROM). The device is manufactured using Atmel’s high density nonvolatile memory technology and is compatible with the industry standard MCS-51? instruction-set and pinout. The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with Flash on a monolithic chip, the Atmel AT89C51 is a powerful microcomputer which provides a highly flexible and cost effective solution to many embedded control applications. Features ? Compatible with MCS-51? Products ? 4K Bytes of In-System Reprogrammable Flash Memory – Endurance: 1,000 Write/Erase Cycles ? Fully Static Operation: 0 Hz to 24 MHz ? Three-Level Program Memory Lock ? 128 x 8-Bit Internal RAM ? 32 Programmable I/O Lines ? Two 16-Bit Timer/Counters ? Six Interrupt Sources ? Programmable Serial Channel ? Low Power Idle and Power Down Modes The AT89C51 provides the following standard features: 4K bytes of Flash,128 bytes of RAM, 32 I/O lines, two 16-bit timer/counters, a five vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator and clock circuitry. In addition, the AT89C51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port and interrupt system to continue functioning. The Power-down Mode saves the RAM contents but freezes the oscillator disabling all other chip functions until the next hardware reset.
外文文献： Knowledge of the stepper motor What is a stepper motor： Stepper motor is a kind of electrical pulses into angular displacement of the implementing agency. Popular little lesson: When the driver receives a step pulse signal, it will drive a stepper motor to set the direction of rotation at a fixed angle (and the step angle). You can control the number of pulses to control the angular displacement, so as to achieve accurate positioning purposes; the same time you can control the pulse frequency to control the motor rotation speed and acceleration, to achieve speed control purposes. What kinds of stepper motor sub-： In three stepper motors: permanent magnet (PM), reactive (VR) and hybrid (HB) permanent magnet stepper usually two-phase, torque, and smaller, step angle of 7.5 degrees or the general 15 degrees; reaction step is generally three-phase, can achieve high torque output, step angle of 1.5 degrees is generally, but the noise and vibration are large. 80 countries in Europe and America have been eliminated; hybrid stepper is a mix of permanent magnet and reactive advantages. It consists of two phases and the five-phase: two-phase step angle of 1.8 degrees while the general five-phase step angle of 0.72 degrees generally. The most widely used Stepper Motor. What is to keep the torque (HOLDING TORQUE) How much precision stepper motor? Whether the cumulative： The general accuracy of the stepper motor step angle of 3-5%, and not cumulative.
目录 目录 (1) 函数的使用和熟悉 (4) 实例3：用单片机控制第一个灯亮 (4) 实例4：用单片机控制一个灯闪烁：认识单片机的工作频率 (4) 实例5：将P1口状态分别送入P0、P2、P3口：认识I/O口的引脚功能 (5) 实例6：使用P3口流水点亮8位LED (5) 实例7：通过对P3口地址的操作流水点亮8位LED (6) 实例8：用不同数据类型控制灯闪烁时间 (7) 实例9：用P0口、P1 口分别显示加法和减法运算结果 (8) 实例10：用P0、P1口显示乘法运算结果 (9) 实例11：用P1、P0口显示除法运算结果 (9) 实例12：用自增运算控制P0口8位LED流水花样 (10) 实例13：用P0口显示逻辑"与"运算结果 (10) 实例14：用P0口显示条件运算结果 (11) 实例15：用P0口显示按位"异或"运算结果 (11) 实例16：用P0显示左移运算结果 (11) 实例17："万能逻辑电路"实验 (11) 实例18：用右移运算流水点亮P1口8位LED (12) 实例19：用if语句控制P0口8位LED的流水方向 (13) 实例20：用swtich语句的控制P0口8位LED的点亮状态 (13) 实例21：用for语句控制蜂鸣器鸣笛次数 (14) 实例22：用while语句控制LED (15) 实例23：用do-while语句控制P0口8位LED流水点亮 (16) 实例24：用字符型数组控制P0口8位LED流水点亮 (17) 实例25：用P0口显示字符串常量 (18) 实例26：用P0 口显示指针运算结果 (19) 实例27：用指针数组控制P0口8位LED流水点亮 (19) 实例28：用数组的指针控制P0 口8 位LED流水点亮 (20) 实例29：用P0 、P1口显示整型函数返回值 (21) 实例30：用有参函数控制P0口8位LED流水速度 (22) 实例31：用数组作函数参数控制流水花样 (22) 实例32：用指针作函数参数控制P0口8位LED流水点亮 (23) 实例33：用函数型指针控制P1口灯花样 (25) 实例34：用指针数组作为函数的参数显示多个字符串 (26) 实例35：字符函数ctype.h应用举例 (27) 实例36：内部函数intrins.h应用举例 (27) 实例37：标准函数stdlib.h应用举例 (28) 实例38：字符串函数string.h应用举例 (29) 实例39：宏定义应用举例2 (29) 实例40：宏定义应用举例2 (29) 实例41：宏定义应用举例3 (30)
杭州电子科技大学信息工程学院毕业设计（论文）外文文献翻译 毕业设计（论文）题目用单片机实现的数字时钟电路设计文献综述题目单片机控制系统系电子工程 专业电子信息科学与技术 姓名郭筱楠 班级08091911 学号08919115 指导教师王维平
单片机控制系统 广义地说，微型计算机控制系统（单片机控制系统）是用于处理信息的，这种被用于处理的信息可以是电话交谈，也可以是仪器的读数或者是一个企业的帐户，但是各种情况下都涉及到相同的主要操作：信息的处理、信息的存储和信息的传递。在常规的电子设计中，这些操作都是以功能平台方式组合起来的，例如计数器，无论是电子计数器还是机械计数器，都要存储当前的数值，并且按要求将该数值增加1。一个系统例如采用计数器的电子钟之类的任一系统要使其存储和处理能力遍布整个系统，因为每个计数器都能存储和处理一些数字。 现如今，以微处理器为基础的系统从常规的处理方法中分离了出来，它将信息的处理，信息的存储和信息的传输三个功能分离形成不同的系统单元。这种主要将系统分成三个主要单元的分离方法是冯-诺依曼在20世纪40年代所设想出来的，并且是针对微计算机的设想。从此以后基本上所有制成的计算机都是用这种结构设计的，尽管他们包含着宽广的物理形式与物理结构，但从根本上来说他们均是具有相同基本设计的计算机。 在以微处理器为基础的系统中，处理是由以微处理器为基础的系统自身完成的。存储是利用存储器电路，而从系统中输入和输出的信息传输则是利用特定的输入/输出（I/O）电路。要在一个以微处理器为基础的时钟中找出执行具有计数功能的一个特殊的硬件组成部分是不可能的，因为时间存储在存储器中，而在固定的时间间隔下由微处理器控制增值。但是，规定系统运转过程的软件却规定了包含实现计数器计数功能的单元部分。由于系统几乎完全由软件所定义，所以对微处理器结构和其辅助电路这种看起来非常抽象的处理方法使其在应用时非常灵活。这种设计过程主要是软件工程，而且在生产软件时，就会遇到产生于常规工程中相似的构造和维护问题。 图1.1 微型计算机的三个组成部分 图1.1显示出了微型计算机中这三个单元在一个微处理器控制系统中是如何按照机器中的信息通信方式而联接起来的。该系统由微处理器控制，微处理器能够对其自身的存储器和输入/输出单元的信息传输进行管理。外部的连接部分与
16位二进制数转换成BCD码的的快速算法－51单片机2010-02-18 00:43在做而论道上篇博文中，回答了一个16位二进制数转换成BCD码的问题，给出了一个网上广泛流传的经典转换程序。 程序可见： http: 32.html中的HEX2BCD子程序。 .说它经典，不仅是因为它已经流传已久，重要的是它的编程思路十分清晰，十分易于延伸推广。做而论道曾经利用它的思路，很容易的编写出了48位二进制数变换成16位BCD码的程序。 但是这个程序有个明显的缺点，就是执行时间太长，转换16位二进制数，就必须循环16遍，转换48位二进制数，就必须循环48遍。 上述的HEX2BCD子程序，虽然长度仅仅为26字节，执行时间却要用331个机器周期。.单片机系统多半是用于各种类型的控制场合，很多时候都是需要“争分夺秒”的，在低功耗系统设计中，也必须考虑因为运算时间长而增加系统耗电量的问题。 为了提高整机运行的速度，在多年前，做而论道就另外编写了一个转换程序，程序的长度为81字节，执行时间是81个机器周期，（这两个数字怎么这么巧！）执行时间仅仅是经典程序的！.近来，在网上发现了一个链接： ，也对这个经典转换程序进行了改进，话是说了不少，只是没有实质性的东西。这篇文章提到的程序，一直也没有找到，也难辩真假。 这篇文章好像是选自某个著名杂志，但是在术语的使用上，有着明显的漏洞，不像是专业人员的手笔。比如说文中提到的：
“使用51条指令代码，但执行这段程序却要耗费312个指令周期”，就是败笔。51条指令代码，真不知道说的是什么，指令周期是因各种机型和指令而异的，也不能表示确切的时间。 .下面说说做而论道的编程思路。;----------------------------------------------------------------------- ;已知16位二进制整数n以b15~b0表示，取值范围为0~65535。 ;那么可以写成： ; n = [b15 ~ b0] ;把16位数分解成高8位、低8位来写，也是常见的形式： ; n = [b15~b8] * 256 + [b7~b0] ;那么，写成下列形式，也就可以理解了： ; n = [b15~b12] * 4096 + [b11~b0] ;式中高4位[b15~b12]取值范围为0~15，代表了4096的个数； ;上式可以变形为： ; n = [b15~b12] * 4000 + {[b15~b12] * (100 - 4) + [b11~b0]} ;用x代表[b15~b12]，有： ; n =x * 4000 + {x * (100 - 4) + [b11~b0]} ;即： ; n =4*x (千位) + x (百位) + [b11~b0] - 4*x ;写到这里，就可以看出一点BCD码变换的意思来了。 ;;上式中后面的位：
The Introduction of AT89C51 Description The AT89C51 is a low-power, high-performance CMOS 8-bit microcomputer with 4K bytes of Flash programmable and erasable read only memory (PEROM). The device is manufactured using Atmel’s high-density nonvolatile memory technology and is compatible with the industry-standard MCS-51 instruction set. The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with Flash on a monolithic chip, the Atmel AT89C51 is a powerful microcomputer which provides a highly-flexible and cost-effective solution to many embedded control applications. Function characteristic The AT89C51 provides the following standard features: 4K bytes of Flash, 128 bytes of RAM, 32 I/O lines, two 16-bit timer/counters, one 5 vector two-level interrupt architecture, a full duplex serial port, one-chip oscillator and clock circuitry. In addition, the AT89C51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port and interrupt system to continue functioning. The Power-down Mode saves the RAM contents but freezes the oscillator disabling all other chip functions until the next hardware reset. Pin Description VCC：Supply voltage. GND：Ground.
外文文献一单片机简介 单片机是一种集成在电路芯片，是采用超大规模集成电路技术把具有数据处理能力的中央处理器CPU随机存储器RAM、只读存储器ROM、多种I/O口和中断系统、定时器/计时器等功能（可能还包括显示驱动电路、脉宽调制电路、模拟多路转换器、A/D转换器等电路）集成到一块硅片上构成的一个小而完善的计算机系统。单片机也被称为微控制器（Microcontroller），是因为它最早被用在工业控制领域。单片机由芯片内仅有CPU的专用处理器发展而来。最早的设计理念是通过将大量外围设备和CPU集成在一个芯片中，使计算机系统更小，更容易集成进复杂的而对体积要求严格的控制设备当中。INTEL的Z80是最早按照这种思想设计出的处理器，从此以后，单片机和专用处理器的发展便分道扬镳。 二、单片机的发展趋势 现在可以说单片机是百花齐放，百家争鸣的时期，世界上各大芯片制造公司都推出了自己的单片机，从8位、16位到32位，数不胜数，应有尽有，有与主流C51系列兼容的，也有不兼容的，但它们各具特色，互成互补，为单片机的应用提供广阔的天地。 纵观单片机的发展过程，可以预示单片机的发展趋势，大致有： 1.低功耗CMOS MCS-51系列的8031推出时的功耗达630mW，而现在的单片机普遍都在100mW左右，随着对单片机功耗要求越来越低，现在的各个单片机制造商基本都采用了CMOS(互补金属氧化物半导体工艺)。象80C51就采用了HMOS(即高密度金属氧化物半导体工艺)和CHMOS(互补高密度金属氧化物半导体工艺)。CMOS虽然功耗较低，但由于其物理特征决定其工作速度不够高，而CHMOS则具备了高速和低功耗的特点，这些特征，更适合于在要求低功耗象电池供电的应用场合。所以这种工艺将是今后一段时期单片机发展的主要途径。 2.微型单片化 现在常规的单片机普遍都是将中央处理器(CPU)、随机存取数据存储(RAM)、只读程序存储器(ROM)、并行和串行通信接口，中断系统、定时电路、时钟电路集成在一块单一的芯片上，增强型的单片机集成了如A/D转换器、PMW(脉宽调制电路)、WDT(看门狗)、有些单片机将LCD(液晶)驱动电路都集成在单一的芯片上，这样 单片机包含的单元电路就更多，功能就越强大。甚至单片机厂商还可以根据用户的要求量身定做，制造出具有． 自己特色的单片机芯片。此外，现在的产品普遍要求体积小、重量轻，这就要求单片机除了功能强和功耗低外，还要求其体积要小。现在的许多单片机都具有多种封装形式，其中SMD(表面封装)越来越受欢迎，使得由单片机构成的系统正朝微型化方向发展。 3.主流与多品种共存 现在虽然单片机的品种繁多，各具特色，但仍以80C51为核心的单片机占主流，兼容其结构和指令系统的有PHILIPS公司的产品，ATMEL公司的产品和中国台湾
51 单片机实用程序库 4.1 流水灯 程序介绍：利用P1 口通过一定延时轮流产生低电平 输出，以达到发光二极管轮流亮的效果。实际应用中例如：广告灯箱彩灯、霓虹灯闪烁。 程序实例（LAMP.ASM） ORG 0000H AJMP MAIN ORG 0030H MAIN: 9 MOV A,#00H MOV P1,A ;灭所有的灯 MOV A,#11111110B MAIN1: MOV P1,A ;开最左边的灯 ACALL DELAY ;延时 RL A ;将开的灯向右边移 AJMP MAIN ;循环 DELAY: MOV 30H,#0FFH D1: MOV 31H,#0FFH D2: DJNZ 31H,D2 DJNZ 30H,D1 RET END 4.2 方波输出 程序介绍：P1.0 口输出高电平，延时后再输出低电 平，循环输出产生方波。实际应用中例如：波形发生器。 程序实例（FAN.ASM）： ORG 0000H MAIN: ;直接利用P1.0 口产生高低电平地形成方波////////////// ACALL DELAY SETB P1.0 ACALL DELAY 10 CLR P1.0 AJMP MAIN ;////////////////////////////////////////////////// DELAY: MOV R1,#0FFH DJNZ R1,$ RET
五、定时器功能实例 5.1 定时1 秒报警 程序介绍：定时器1 每隔1 秒钟将p1.o 的输出状态改变1 次，以达到定时报警的目的。实际应用例如：定时报警器。程序实例（DIN1.ASM）： ORG 0000H AJMP MAIN ORG 000BH AJMP DIN0 ;定时器0 入口 MAIN: TFLA G EQU 34H ;时间秒标志，判是否到50 个 0.2 秒，即50*0.2=1 秒 MOV TMOD,#00000001B;定时器0 工作于方式 1 MOV TL0,#0AFH MOV TH0,#3CH ;设定时时间为0.05 秒，定时 20 次则一秒 11 SETB EA ;开总中断 SETB ET0 ;开定时器0 中断允许 SETB TR0 ;开定时0 运行 SETB P1.0 LOOP: AJMP LOOP DIN0: ;是否到一秒//////////////////////////////////////// INCC: INC TFLAG MOV A,TFLAG CJNE A,#20,RE MOV TFLAG,#00H CPL P1.0 ;////////////////////////////////////////////////// RE: MOV TL0,#0AFH MOV TH0,#3CH ;设定时时间为0.05 秒，定时 20 次则一秒 RETI END 5.2 频率输出公式 介绍：f=1/t s51 使用12M 晶振，一个周期是1 微秒使用定时器1 工作于方式0，最大值为65535，以产生200HZ 的频率为例： 200=1/t:推出t=0.005 秒，即5000 微秒,即一个高电
外文资料翻译 STC89C52 processi ng chip Prime features: With MCS - 51 SCM product compatibility, 8K bytes in the system programmable Flash memory, 1000 times CaXie cycle, the static operation: 0Hz ~ 33Hz, triple encryption program memory, 32 programmed I/O port, three 16 timer/counter, the eight uninterrupted dual-career UART serial passage, low power consumption, leisure and fall after fall electric power mode can be awakened and continuous watchdog timer and double-number poin ter, power ide ntifier. Efficacy: characteristics STC89C52 is one kind of low power consumption, high CMOS8 bit micro-co ntroller, 8K in system programmable Flash memory. Use high-de nsity nonv olatile storage tech no logy, and in dustrial 80C51 product in structi on and pin fully compatible. The Flash memory chips allows programs in the system, also suitable for programmable conventional programming. In a single chip, have clever 8 bits CPU and on li ne system programmable Flash, in crease STC89C52 for many embedded control system to provide high vigorous application and useful solutions. STC89C52 has following standard efficacy: 8k byte Flash RAM, 256 bytes, 32 I/O port, the watchdog timer, two, three pointer numerical 16 timer/counter, a 6 vector level 2 continuous structure, the serial port, working within crystals and horological circuit. In addition, 0Hz AT89S52 can drop to the static logic operation, support two software can choose power saving mode. Idle mode, the CPU to stop working, and allows the RAM, timer/c oun ters, serial, continu ous to work. Protectio n asa na patter n, RAM content is survival, vibrators frozen, SCM, until all the work under a continuous or hardware reset. 8-bit microcontrollers 8K bytes in the system programmable Flash AT89S52 devices. Mouth: P0 P0 mouth is a two-way ope n drain I/O. As export, each can drive eight TTL logic level. For P0 port to write "1", foot as the high impeda nee in put. When access to exter nal programs and nu merical memory, also known as
1．闪烁灯 1．实验任务 如图4.1.1所示：在P1.0端口上接一个发光二极管L1，使L1在不停地一亮一灭，一亮一灭的时间间隔为0.2秒。 2．电路原理图 图4.1.1 3．系统板上硬件连线 把“单片机系统”区域中的P1.0端口用导线连接到“八路发光二极管指示模块”区域中的L1端口上。 4．程序设计内容 （1）．延时程序的设计方法 作为单片机的指令的执行的时间是很短，数量大微秒级，因此，我们要 求的闪烁时间间隔为0.2秒，相对于微秒来说，相差太大，所以我们在 执行某一指令时，插入延时程序，来达到我们的要求，但这样的延时程 序是如何设计呢？下面具体介绍其原理：
如图4.1.1所示的石英晶体为12MHz，因此，1个机器周期为1微秒机器周期微秒 MOV R6,#20 2个 2 D1: MOV R7,#248 2个 2 2＋2×248＝498 20× DJNZ R7,$ 2个2×248 (498 DJNZ R6,D1 2个2×20＝40 10002 因此，上面的延时程序时间为10.002ms。 由以上可知，当R6＝10、R7＝248时，延时5ms，R6＝20、R7＝248时， 延时10ms,以此为基本的计时单位。如本实验要求0.2秒＝200ms， 10ms×R5＝200ms，则R5＝20，延时子程序如下： DELAY: MOV R5,#20 D1: MOV R6,#20 D2: MOV R7,#248 DJNZ R7,$ DJNZ R6,D2 DJNZ R5,D1 RET （2）．输出控制 如图1所示，当P1.0端口输出高电平，即P1.0＝1时，根据发光二极管 的单向导电性可知，这时发光二极管L1熄灭；当P1.0端口输出低电平， 即P1.0＝0时，发光二极管L1亮；我们可以使用SETB P1.0指令使P1.0 端口输出高电平，使用CLR P1.0指令使P1.0端口输出低电平。 5．程序框图 如图4.1.2所示
51单片机中的汇编语言与 C 语言 C 语言, 更多的是为了掌握单片机的应用, C 语言是高效的应用程序开发工具, 与汇编语言比却不是开发高效应用程序的工具。就目前而言, 更多的是为了应用单片机, 开发应用程序, 更多的是强调开发效率, 而不是程序的运行效率 (相对而言。再就是应用程序对单片机内部资源的使用效率, 这在过去, 单片机内部资源紧缺的年代, 特别的强调, 现在已经不是特别重要了。所以, 大多数人都认为,只用 C 语言,就可以应对大多数单片机的应用开发了。 其实,汇编语言跟 C 语言在本质上一样的,只是语言形式不同而已,一个接近底层逻辑, 一个接近人类语言, 本质上都是对寄存器或存储器的读写操作而已。 汇编语言中,用 MOV 来回传送数据, C 语言里,用等号表示数据传送。汇编语言中,用 call 转去执行子过程程序, C 语言里,用个函数名调用子程序。汇编语言中,用 JMP 完成分支转移, C 语言里用 if 、 switch 、 while 、 for 来判断跳转。汇编语言跟 C 一样可以给寄存器指定命名,然后对定义的名称进行操作。汇编语言提供了对很多标志位的操作, C51根据需要也进行了改进, C 语言可以通过 #include给存储器命名来简化操作。 我觉得, C 语言是最接近汇编语言的一种高级语言, 要说不同, 也许具有大量函数的函数库,是 C 语言与汇编语言的最大区别,也是 C 语言比汇编语言有更大开发效率的原因。 在应用汇编语言进行应用程序开发时, 如果精心规划好程序结构, 设计好各种数据结构、子程序、中断程序,积累大量的算法程序(相当于函数库,也可以高效率的用汇编语言进行单片机开发。倒是兼容性、可移植性是汇编语言的最大限制,因为不同单片机有不同的指令系统,而 C 语言把这个问题,交给了机器也就是编译器去解决了。其实, 计算机的发展, 就是把尽可能多的事情交个机器去解决。
SCM is an integrated circuit chip, is the use of large scale integrated circuit technology to a data processing capability of CPU CPU random access memory RAM, read-only memory ROM, a variety of I / O port and interrupt system, timers / timer functions (which may also include display driver circuitry, pulse width modulation circuit, analog multiplexer, A / D converter circuit) integrated into a silicon constitute a small and complete computer systems. SCM is also known as micro-controller (Microcontroller), because it is the first to be used in industrial control. Only a single chip by the CPU chip developed from a dedicated processor. The first design is by a large number of peripherals and CPU on a chip in the computer system, smaller, more easily integrated into a complex and demanding on the volume control device which. The Z80 INTEL is the first designed in accordance with this idea processor, then on the development of microcontroller and dedicated processors will be parting ways. Are 8-bit microcontroller early or 4 bits. One of the most successful is the INTEL 8031, for a simple, reliable and good performance was a lot of praise. Then developed in 8031 out of MCS51 MCU Systems. SCM systems based on this system until now is still widely used. With the increased requirements of industrial control field, began a 16-bit microcontroller, but not ideal because the cost has not been very widely used. After 90 years with the great development of consumer electronics, microcontroller technology has been a huge increase. With INTEL i960 series, especially the later series of widely used ARM, 32-bit microcontroller quickly replace high-end 16-bit MCU status and enter the mainstream market. The traditional 8-bit microcontroller performance have been the rapid increase capacity increase compared to 80 the number of times. Currently, high-end 32-bit microcontroller clocked over 300MHz, the performance catching the mid-90s dedicated processor, while the average model prices fall to one U.S. dollar, the most high-end [1] model only 10 dollars. Modern SCM systems are no longer only in the development and use of bare metal environment, a large number of proprietary embedded operating system is widely used in the full range of SCM. The handheld computers and cell phones as the core processing of high-end microcontroller can even use a dedicated Windows and Linux operating systems. SCM is more suitable than the specific processor used in embedded systems, so it was up to the application. In fact the number of SCM is the world's largest computer. Modern human life used in almost every piece of electronic and mechanical products will be integrated single chip. Phone, telephone, calculator, home appliances, electronic toys, handheld computers and computer accessories such as a mouse with a 1-2 in both the Department of SCM. Personal computer will have a large number of SCM in the work. General car with more than 40 microcontroller, a complex industrial control systems may even hundreds of single chip at the same time work! SCM is not only far exceeds the number of PC and other computing the sum, or even more than the number of human beings. Single chip, also known as single-chip microcontroller, it is not complete a certain logic chips, but to a computer system integrated into a chip. Equivalent to a
外文翻译---51系列单片机的结构和功能
外文资料翻译 英文原文： Structure and function of the MCS-51 series Structure and function of the MCS-51 series one-chip computer MCS-51 is a name of a piece of one-chip computer series which Intel Company produces. This company introduced 8 top-grade one-chip computers of MCS-51 series in 1980 after introducing 8 one-chip computers of MCS-48 series in 1976. It belong to a lot of kinds this line of one-chip computer the chips have such as 8051, 8031, 8751, 80C51BH, 80C31BH,etc., their basic composition, basic performance and instruction system are all the same. 8051 daily representatives- 51 serial one-chip computers . An one-chip computer system is made up of several following parts: (1) One microprocessor of 8 (CPU). (2) At slice data memory RAM (128B/256B),it use not depositing not can reading /data that write, such as result not middle of operation, final result and data wanted to show, etc. (3) Procedure memory ROM/EPROM (4KB/8KB ), is used to preserve the procedure , some initial data and form in slice. But does not take ROM/EPROM within some one-chip computers, such as 8031 , 8032, 80C ,etc.. (4) Four 8 run side by side I/O interface P0 four P3, each mouth can use as introduction, may use as exporting too. (5) Two timer / counter, each timer / counter may set up and count in the way, used to count to the external incident, can set up into a timing way too, and can according to count or result of timing realize the control of the computer. (6) Five cut off cutting off the control (universal asynchronous receiver/transmitter (UART) ), is it realize one-chip computer or one-chip computer and serial communication of computer to use for. (8) Stretch oscillator and clock produce circuit, quartz crystal finely tune electric capacity need outer. Allow oscillation frequency as 12 megahertz now at most. Every the above-mentioned part was joined through the inside data bus .Among them, CPU is a core of the one-chip computer, it is the control of the computer and command center, made up of such parts as arithmetic unit and controller , etc.. The arithmetic unit can carry on 8 persons of arithmetic operation and unit ALU of logic operation while including one, the 1 storing devices temporarily of 8, storing device 2 temporarily, 8's accumulation device ACC, register B and procedure state register PSW, etc. Person who accumulate ACC count by 2 input ends entered of checking etc. temporarily as one operation often, come from person who store 1 operation is it is it make operation to go on to count temporarily , operation result and loop back ACC with another one. In addition, ACC is often regarded as the transfer station of data transmission on 8051 inside. The same as general microprocessor, it is the busiest register. Help remembering that agreeing with a expresses in the order. The controller includes the procedure counter, the order is deposited, the