Bit timing(can总线BT时间确定-用于确定波特率)

CAN总线能够在一定的范围内容忍总线上CAN节点的通信波特率的偏差，这种机能使得CAN总线有很强的容错性，同时也降低了对每个节点的振荡器精度。

实际上，CAN总线的波特率是一个范围。

假设定义的波特率是250KB/S，但是实际上根据对寄存器的设置，实际的波特率可能为200~300KB/S（具体值取决于寄存器的设置）。

在CAN的底层协议里将CAN数据的每一位时间(TBit）分为许多的时间段(Tscl)，这些时间段包括：A．位同步时间(Tsync)B．时间段1(Tseg1)C．时间段2(Tseg2)其中位同步时间占用1个Tscl；时间段2占用(Tseg1+1)个Tscl；时间段2占用(Tseg2+1)个Tscl,所以CAN控制器的位时间(TBit)就是：TBit=Tseg1+Tseg2+Tsync=(TSEG1+TSEG2+3）*TsclCAN的波特率(CANbps)就是1/TBit。

Tsync=1Tscl但是这样计算出的值是一个理论值。

在实际的网络通信中由于存在传输的延时、不同节点的晶体的误差等因素，使得网络CAN的波特率的计算变得复杂起来。

CAN在技术上便引入了重同步的概念，以更好的解决这些问题。

这样重同步带来的结果就是要么时间段1(Tseg1)增加TSJW（同步跳转宽度SJW+1），要么时间段减少TSJW，因此CAN的波特率实际上有一个范围：1/(Tbit+Tsjw) ≤CANbps≤1/(Tbit-Tsjw)CAN有波特率的值四以下几个元素决定：A．最小时间段Tscl；B．时间段1 TSEG1；C．时间段2 TSEG2；D．同步跳转宽度SJWSJW（重同步跳转宽度）决定了一次重同步期间一个位时间被延长或缩短的时间量子Tscl是通过总线时序寄存器设置计算的。

Tscl＝（BRP+1）/FVBP。

FVBP为微处理器的外设时钟。

而TSEG1与TSEG2又是怎么划分的呢？TSEG1与TSEG2的长度决定了CAN数据的采样点，这种方式允许宽范围的数据传输延迟和晶体的误差。

CAN波特率计算CAN（Controller Area Network）是一种常用于实时通信的串行总线系统。

CAN总线的波特率（即数据传输速率）是非常重要的参数，它决定了CAN总线传输数据的速度和可靠性。

计算CAN总线的波特率需要考虑以下几个因素：1. 位时间（Bit Time）：CAN总线被划分为若干个位时间，每个位时间由若干个时间段组成。

其中最重要的三个时间段是同步时间段（Synchronization Segment, Sync_Seg）、传播时间段（Propagation Segment, Prop_Seg）和相位段（Phase Segment, Phase_Seg）。

2. 位时间的总数：位时间的总数由同步时间段、传播时间段和相位段的时长之和决定。

位时间的总数记为N，通常有一个最小值（N_min）和一个最大值（N_max）。

3.位时间的时间分配：每个时间段的时长可以根据实际需求进行分配。

一般来说，同步时间段的时长很短，传播时间段的时长取决于总线长度和传播速度，相位段的时长取决于网络拓扑结构和所需的抗干扰能力。

4. 采样点（Sampling Point）：CAN总线数据帧中每个位的采样点位置是固定的，并且通常位于相位段的中心。

5. 采样点的位置：采样点的位置可以通过同步时间段的时长（t_sync）、传播时间段的时长（t_prop）和位时间的总数（N）来计算。

采样点的位置可以用相位段的时长（t_phase）相对于整个位时间的长度（t_bit）来表示。

现在，我们来具体计算CAN总线的波特率的步骤：1.确定CAN总线的特性：首先需要确定CAN总线的物理特性，包括总线长度、传播速度等参数。

2. 确定位时间的总数（N）：根据CAN总线的要求或规范，可以确定位时间的总数的最小值（N_min）和最大值（N_max）。

一般来说，N的取值范围在8到25之间。

3. 计算同步时间段的时长（t_sync）：同步时间段的时长一般为1至3个时间单元（CAN位时间的最小单位）。

例：CAN控制器的晶振f can_clk=10MHZ,节点间最长的距离为40m，tq不分频，直接采用控制器的时钟，总线输出延迟为50ns，接收延迟为30ns，波特率为1Mbps.tq=1/f can_clk=1/10 MHZ=100ns总线的最大传输延迟=总线的最长距离/光电速度=40/3*108≈133nsProp_Seg=2*(总线输入延迟+总线输出延迟+总线最大传输延迟)=2*（30ns+50ns+133ns）=426 ns考虑冗余预留，则Prop_Seg=600 ns=6 tq; Sync_Seg=1 tq;Phase_Seg1=1 tq;Phase_Seg2=2tq(因为采样是在Phase_Seg1和Phase_Seg2之间，所以在Phase_Seg2中应包含至少1 tq处理时间)真实SJW=min(Phase_Seg1,Phase_Seg2)=1tqBit_time=Sync_Seg+Prop_Seg+Phase_Seg1+Phase_Seg2=10 tq=1 Mbps晶振漂移容许=min（Phase_Seg1,Phase_Seg2）/ 2*(13*Bit_time-Phase_Seg2) =1 tq / 2*(13*10 tq-2 tq) =0.39%寄存器配置：[0]1[TSeg2]3[TSeg1]4[SJW]2[BRP]6= [0]1 [Phase_Seg2-1]3 [Prop_Seg+Phase_Seg1-1]4 [真实SJW-1]2 [分频数-1]6 =[0]1[2-1]3 [1+6-1]4 [1-1]2[1-1]6=[0]1 [1]3 [6]4 [0]2 [0]6=0x1600下面是从Cygnal网站论坛上看到的：#define BTR(tseg1, tseg2, sjw, brp)(((tseg2 - 1)<<12)|((tseg1 -1)<<8)|((sjw-1)<<6)|(brp-1))#define kBTR_1MbpsBTR(2,8,1,2)// 1 Mbps#define kBTR_500kbpsBTR(2,8,1,4)// 500 kbpsvoid set_bitrate( unsigned int btr ){unsigned char SFR_SAVE_PAGE;SFR_SAVE_PAGE=SFRPAGE;SFRPAGE = CAN0_PAGE;CAN0CN |= 0x41;CAN0ADR = BITREG;CAN0DAT = btr;CAN0CN &= 0xbe;SFRPAGE=SFR_SAVE_PAGE;}set_bitrate( kBTR_1Mbps );//1 Mbpsset_bitrate( kBTR_500kbps );//500 kbpsTProp_seg = 2 x (transceiver loop delay(150nsec) + bus line delay(5nsec/m)) // condition from the CAN parameter definition1 <= BRP <= 32Tq = BRP / FsysTSync_Seg = TqTq <= TProp_Seg <= 8*TqTq <= TPhase_Seg1 <= 8*TqTq <= TPhase_Seg2 <= 8*TqTq <= TSJW <= 4*TqTbit = TSync_Seg + TProp_Seg + TPhase_Seg1 + TPhase_Seg2Tbit = 1 / baud (nearly equal)// condition from F040 exampleTPhase_Seg1 == TPhase_Seg2TSJW = min( TPhase_Seg1, 4*Tq )// quantamizetseg1 = (TProp_Seg + TPhase_Seg1) / Tqtseg2 = TPhase_Seg2 / Tqsjw = TSJW / TqBTR = (((tseg2 - 1)<<12)|((tseg1 - 1)<<8)|((sjw-1)<<6)|(BRP - 1))//----------------------------------------------------------------// procedure// 1) calculate BRP: select BRP as the smallest integer within these range, a)b)c)// a) BRP range 1(1 + 1 + 1 + 1) * Tq <= Tbit <= (1 + 8 + 8 + 8) * Tq(Fsys/baud) / 25 <= BRP <= (Fsys/baud) / 4// b) BRP range 2Tq <= TProp_Seg <= 8 * Tq(Fsys*TProp_Seg) / 8 <= BRP <= (Fsys*TProp_Seg)// c) BRP range 3(Tbit - TProp_seg) <= (1 + 8 + 8) * Tq{(Fsys/baud) - (Fsys*TProp_seg)} / 17 <= BRP// 2) Calculate quantimized value of Tbit, TProp_Seg and TPhase_Seg1 QTbit = baud / Tq = (Fsys/baud) / BRPQTProp_Seg = TProp_Seg / Tq = ceil((Fsys*TProp_Seg) / BRP)QTPhase_Seg1 = int((QTbit - 1 - QTProp_Seg) / 2)// 3) determine tseg1,tseg2,sjwtseg1 = QTProp_Seg + QTPhase_Seg1tseg2 = QTbit - 1 - tseg1sjw = min( QTPhase_Seg1, 4 )//C8051F040 CAN 波特率对照表(系统频率22118400HZ)#define BAUDRATE_40K0x7adb//40K,250m#define BAUDRATE_50K0x7ad5//50K,250m#define BAUDRATE_80K0x7bcc//80K,250m#define BAUDRATE_100K0x6dc9//100K,250m#define BAUDRATE_125K0x6dc7//125K,250m#define BAUDRATE_200K0x2947//200K,250m#define BAUDRATE_250K0x0807//250K,250m#define BAUDRATE_500K0x0803//500K,100m#define BAUDRATE_800K0x2941//800K,40m#define BAUDRATE_1000K 0x1701//1000K,30m//C8051F040 CAN 波特率对照表(系统频率22118400HZ)#define BAUDRATE_40K0x7adb//40K,250m#define BAUDRATE_50K0x7ad5//50K,250m#define BAUDRATE_80K0x7bcc//80K,250m#define BAUDRATE_100K0x6dc9//100K,250m #define BAUDRATE_125K0x6dc7//125K,250m #define BAUDRATE_200K0x2947//200K,250m #define BAUDRATE_250K0x0807//250K,250m #define BAUDRATE_500K0x0803//500K,100m #define BAUDRATE_800K0x2941//800K,40m#define BAUDRATE_1000K 0x1701//1000K,30m。

第一章1、简要说明现场总线、控制网络的定义答：现场总线是指将现场设备（如数字传感器、变送器、仪表与执行机构等）与工业操作单元、现场操作站等互联而成的通信网络，它的关键标志是能支持双向、分散、多节点、总线式的全数字通信，是工业控制网络向现场及发展的产物。

2、简要说明现场总线技术的特点答：现场总线是3C（计算机、通信、控制）技术的融合。

其技术特点是:信号输出全数字、控制能力全分散、标准统一全开放。

具体是（1）系统的开放性（2）互操作性与互用性（3）现场设备的智能化与功能自治性（4）系统结构的高度分散性（5）对现场环境的适应性。

3、简要说明网络化控制系统的结构组成答：由被控对象、执行器、传感器、网络时延、控制器组成4、网络化控制系统的主要技术特点有哪些答：主要有：1、结构网络化2、节点智能化3、控制现场化和功能分散化4、系统开放化和产品集成化5、对现场环境的适应性5、HART通信模型有那几层组成答：HART通信模型由3层组成：物理层、数据链路层和应用层6、与传统布线相比，P-NET现场总线技术在工业控制应用中具有哪些优势答：与传统布线相比，P-NET现长总线技术在工业控制应用中有很大的优势，它可以简化设计和安装，减少布线的数量和费用，避免各种设备故障的发生，实现更直接也更广泛的使用功能。

7.WorldFIP可用的运输速率有哪些，标准传输速率是多少？答：传输速率用于铜线的有31.25Kbit/s、1Mbit/s和2.5Mbit/s，其中1Mbit/s是标准速率。

第二章1、什么是差错控制答：在计算机通信中，为了提高通信系统的传输质量而提出的有效的检测错误并进行纠正的方法叫做差错检测和校正，简称为差错控制2、数据通信系统由哪几部分组成答：数据通信系统由数据信息的发送设备、接收设备、传输介质、传输报文、通信协议等几部分组成3、简要介绍通信系统的通信指标答：通信指标有1、有效性指标2、可靠性指标3、通信信道的频率特性4、介质宽带，信息传输的有效性指标和可靠性是通信系统最主要的指标4、数据传输方式有哪些？选取其中两种进行简要介绍答：数据传输方式是指数据代码的传输顺序和数据信号传输的同步方式，有串行传输与并行传输，同步传输与异步传输，位同步、字符同步与帧同步等几种在串行传输中，数据流以串行方式逐位地在一条信道上传输，每次只能发送一个数据位，发送方必须确定是先发送数据字节的高位还是低位。

（stm32f103学习总结）—can总线参考： 1 CAN总线介绍 CAN 是Controller Area Network 的缩写，中⽂意思是控制器局域⽹ 络，是ISO国际标准化的串⾏通信协议。

它是德国电⽓商博世公司于1986 年⾯向汽车⽽开发的CAN 通信协议。

此后，CAN 通过ISO11898 及 ISO11519 进⾏了标准化。

CAN是国际上应⽤最⼴泛的现场总线之⼀，在 欧洲已是汽车⽹络的标准协议。

CAN 的⾼性能和可靠性已被认同，并被 ⼴泛地应⽤于⼯业⾃动化、船舶、医疗设备、⼯业设备等⽅⾯。

CAN通信只具有两根信号线，分别是CAN_H和CAN_L，CAN 控制器根据 这两根线上的电位差来判断总线电平。

总线电平分为显性电平和隐性电 平，⼆者必居其⼀。

发送⽅通过使总线电平发⽣变化，将消息发送给接 收⽅。

2 CAN物理层 与I2C、SPI等具有时钟信号的同步通讯⽅式不同，CAN通讯并不是以时钟信号来进⾏同步的，它是⼀种异步通讯，只具有CAN_High和CAN_Low两条信号线，共同构成⼀组差分信号线，以差分信号的形式进⾏通讯。

CAN物理层的形式主要分为闭环总线及开环总线⽹络两种，⼀个适合于⾼速通讯，⼀个适合于远距离通讯。

2.1 闭环can总线⽹络CAN闭环通讯⽹络是⼀种遵循ISO11898标准的⾼速、短距离⽹络，它的总线最⼤长度为40m，通信速度最⾼为1Mbps，总线的两端各要求有⼀个“120欧”的电阻2.2 开环can总线⽹络CAN开环总线⽹络是遵循ISO11519-2标准的低速、远距离⽹络，它的最⼤传输距离为1km，最⾼通讯速率为125kbps，两根总线是独⽴的、不形成闭环，要求每根总线上各串联有⼀个“2.2千欧”的电阻2.3通讯节点 CAN总线上可以挂载多个通讯节点，节点之间的信号经过总线传输，实现节点间通讯。

由于CAN通讯协议不对节点进⾏地址编码，⽽是对数据内容进⾏编码，所以⽹络中的节点个数理论上不受限制，只要总线的负载⾜够即可，可以通过中继器增强负载。

1总线定时寄存器0（BTR0）总线定时寄存器0的内容确定波特率预引比例因子（BRP）和同步跳转宽度（SJW）的值。

若复位模式有效，此寄存器是可以被访问（读/写）的。

只有选择PeliCAN模式，此寄存器在运行模式中才是可读的。

在BasicCAN模式中呈现的是‘FFH’。

总线定时寄存器0各位的说明见表3-49。

表3-49 总线定时寄存器0（BTR0）各位的说明；CAN地址6（1）波特率预引比例因子（BRP）CAN系统时钟的周期是可编程的，并决定各个位定时。

CAN系统时钟使用下式进行计算：其中，=XTAL的频率周期= 1/（2）同步跳转宽度（SJW）为补偿在不同总线控制器的时钟振荡器之间的相移，任何总线控制器必须重同步于当前发送的任何相关信号沿。

同步跳转宽度确定一个位时间可以被一次重同步所缩短或延长的时钟周期的最大数目：2总线定时寄存器1（BTR1）总线定时寄存器1的内容确定位时间的长度、采样点的位置和在每个采样点欲获取的采样数目。

如果复位模式有效，这个寄存器可以被访问（读/写）。

只有选择PeliCAN模式，这个寄存器在运行模式中才是可读的。

在BasicCAN模式中呈现的是‘FFH’。

总线定时寄存器1各位的说明见表3-50。

表3-50 总线定时寄存器1（BTR1）各位的说明；CAN地址7（1）采样（SAM）SAM位的取值说明如表3-51所示。

表3-51 采样（SAM）位的取值说明（2）时间段1（TSEG1）时间段2（TSEG2）位周期的一般结构如图3-38所示。

(TSEG1)和(TSEG2)决定每一位时间的时钟数目和采样点的位置，这里：采样点（S）可能值是BRP=000001, TSEG1=0101, TSEG2=010。

必须注意！BTR0、BTR1的设置必须满足：1.在位时间中，时间份额的总数必须被编程为至少8至25；2.重同步跳转宽度< Tseg2;3.Tseg2< Tseg1。

波特率的计算：BitRate = Fpclk/( (BRP+1) * ((Tseg1+1)+(Tseg2+1)+1)。

can位时序参数解释CAN（Controller Area Network）是一种广泛应用于汽车和工业领域的通信协议。

在CAN总线通信中，位时序参数是指在通信过程中各个位（bit）的时间间隔和序列。

位时序参数主要包括以下几个方面的内容：1. 传输速率：也称为波特率（Baud Rate），指的是每秒钟传输的位数。

传输速率决定了通信的速度和稳定性。

通常用单位为bit/s来表示，比如常见的波特率有250kbit/s、500kbit/s等。

2. 同步段：在CAN通信的每一帧（Frame）的开始部分，都有一个同步段（Sync Segment）。

同步段的作用是提供足够的时间给接收器进行同步，确保接收器能够正确地识别位的开始位置。

通常同步段的长度为一个时间单元（Time Unit）。

3. 传播延迟（Propagation Delay）：指的是信号从发送端传播到接收端的时间延迟。

由于CAN总线的物理长度和通信速率的限制，信号传播会存在一定的时间延迟。

传播延迟对于数据的传输速率和可靠性有影响。

4. 位时间：位时间是指一个位（bit）所占用的时间。

在CAN通信中，每个位时间由许多小的时间单元组成。

位时间的长度由同步段、传播延迟、采样点（Sample Point）等因素共同决定。

5. 采样点：采样点是指一个位时间内取样的时刻。

在CAN通信中，接收器需要在每个位时间的合适时刻对信号进行采样，以确定位的值。

采样点的选择对于正确解析传输的数据至关重要。

通过设置合适的位时序参数，可以保证CAN通信的稳定性和可靠性。

不同的应用场景可能需要不同的位时序参数，因此在CAN通信系统的设计和调试过程中，需要合理地选择和调整这些参数。

通过对CAN位时序参数的解释，希望能够帮助你更好地理解CAN通信协议，以及在实际应用中对位时序参数的设置和优化的重要性。

TN1346Technical note SPC58x configuring CAN and CAN-FD bit timing parametersIntroductionThis technical note details how to configure the bit timing and baud-rate for the CAN peripheral available on all ST automotive SPC58x microcontrollers.The document provides a practical description of the configuration registers and some examples that aim to speed up the peripheral setup. The configuration steps are shared among the SPC58 microcontroller family excepting for minor changes especially related to the CAN protocol clock initialization. The differences found for the protocol clock configuration are mainly due to different clock tree; these are detailed inside each microcontroller’s reference manual (see Section 5 Reference documents).This document and related examples will focus on the CAN bit timing and baud-rate configuration of SPC584Cx/SPC58ECx32-bit MCU.CAN overview 1CAN overviewSPC584Cx/SPC58ECx has eight CAN instances embedded in two different subsystems as documented in thedevice reference manual. All the CAN controllers into the same subsystem will share resources like RAM memory,clock, etc.Each CAN subsystem consists of the following major blocks:•Modular CAN cores: The registers of the CAN module can be accessed using the generic slave interface (GSI). The peripheral GSI module enables acts as a request from each master.•CAN-RAM arbiter: it is an additional logic for arbitration between the requests for the RAM access by the various CAN controllers.•SRAM: the CAN subsystem interfaces with an external RAM using this interface, it is the SRAM.•ECC controller: it contains the logic to compute and validate the correction code on the SRAM memory.1.1Peripheral clocksAs described in the device’s reference manual, each CAN instance inside a CAN subsystem needs two differentclocks:•Host clock•Protocol clockNote:refer to the device’s reference manual for this clock routing and details (see Section 5 Reference documents) Note:to achieve a stable function of the peripheral, the host clock must always be faster or equal to the CAN protocol clock.1.2Protocol clock selectionThis paragraph details the protocol clock. It`s the clock used by the CAN controller to define the time quantaperiod and define the bit timing (Baudrate).In this microcontroller family it is possible to choose the protocol clock source between:•XOSC•PLL0The desired configuration is made through the clock generation module (CGM) registers.In this example, the registers for CAN subsystem 1 and 2 are respectively CGM_AC8 and CGM_AC11.See the following figure.Protocol clock selectionCAN clock schemaFigure 1.register and setup the XOSC as CAN protocol clock in CGM_AC8_SC register as below:Supposing to choose the 40 MHz oscillator XOSC this register must be programmed:// Select XOSC as Source clockMC_CGM.AC8_SC.B.SELCTL = 0x01; // 1 it is the default value// enable the dividerMC_CGM.AC8_DC0.B.DE = 0x01// divide input clock by 2MC_CGM.AC8_DC0.B.DIV = 0x01; // the divider is intended one plus the value wrote in register Using the above setup, the protocol clock provided to CAN will have a frequency of 20 MHz that is the XOSC frequency (40 MHz) divided by 2.2Baud rate configurationThis chapter describes how to configure bit timing parameters according to the baud rate value. It aims to provideconfiguration examples for both CAN Standard and CAN-FD.On the base of the protocol clock configuration, in this example the clock is considered running at 20 MHz.It is mandatory to know that the CAN controller divides each bit in an integer number of time-quanta (Tq). Thetime-quanta time is the period of protocol clock:Tq = 1/protocol clockActing on baud-bate pre-scaler (NBRP field of NBTP register) it is possible to define the number of Tq per bit.For example, if it is needed a 1M baud-rate, the bit-time will be 1 µs. If the CAN controller has a Protocol clockof 20 MHz, defining a baud rate pre-scaler equals to “1”, then the Tq will be 50 ns. Dividing the bit time by the Tqtime (protocol clock period) the result is 20 time-quanta per bit.Using a baud-rate pre-scaler equals to “2”, the frequency of protocol clock will be divided by 2 and 10 MHz asprotocol clock will be obtained. So, following the same previous formula, the number of Tq per bit will be 10instead of 20.Note:all the pre-scalers are acceptable for a selected baud-rate. In the previous example, using a pre-scaler value of 3, the protocol clock will be 6.666 MHz (20 MHz / 3 ) and the Tq period will be about 152 ns. Dividing the bittime (1 µs at 1 Mbit/s) for the Tq period the result isn`t an integer number. Since CAN protocol the number ofTq inside a bit must be integer, then the pre-scaler 3 cannot be used for 1 M baud-rate having a protocol clock(coming from CGM clock generation module) of 20 MHz.3Bit timing configurationConfiguring the bit timing registers, it is possible to define the position of the sample point for all the bits that thecontroller gets on the bus and the baud-rate as well.For each bit, three sections are available, as shown in the following figure.Figure 2. Bit timingEach section is composed by a configurable number of time-quanta, except for SYNC_SEG that is alwayscomposed by 1 time-quanta.The sum of SYNC_SEG, TSEG1 AND TSEG2 is equal to the total number of time-quanta that compose the bit.The sample point is where the controller samples the bit and is placed at the end of TSEG1 (or beginning ofTSEG2).Configuring the length of segments TSEG1 and TSEG2 (both expressed in number of time-quanta (Tq)) it isdefined the positioning of the sample point. It must be programmed in the registers NBTP (for arbitration part ofthe message) and DBTP for the data. In CAN-FD mode both registers must be programmed, while in standardCAN mode it is needed to only configure the NBTP register.3.1Standard CAN exampleSupposing it is needed to configure the CAN controller with a 1Mbit/ baud-rate and a sample point of 75% theNBTP register will be programmed as shown below.Figure 3. NBTP registerThe NSJW field is used for the Resynchronization and generally it should <= NTSEG2 value.Supposing to have 20 MHz as protocol clock, and no other pre-scaler must be applied on this frequency, so theNBRP field will be set to 0. In this case the time-quanta will be 1/20000000 = 50 ns. The bit time (the length of abit) at 1 Mbit/s is 1 µs.Dividing the bit time period by the time-quanta period it is seen that one bit contain exactly 20 time-quanta. Note:if the division result is not an integer value user has to try another pre-scaler and so, the sum of segments length NTSEG1 + NTSEG2 = 19 (this because SYNC_SEG is always 1 Tq).Supposing to sample each bit at 75%, then the sum SYNC_SEG + NTSEG1 should be the 75% of total TQnumber per bit that in our case (20 total Tq per bit) is 15 time-quanta.Considering one time-quanta of SYNC_SEG, then the NTSEG1 must be 14 Tq and the remaining 5 Tq are thelength of NTSEG2.At the end, NBTP field values are:•NSJW = 4 (NTSEG2 value)•NBRP to 0•NTSEG1 to 13•NTSEG2 to 4Note:from device’s reference manual: the actual interpretation by the hardware of this value is such that one more than the value programmed here is used (see Section 5 Reference documents)Considering one time-quanta of SYNC_SEG, then the DTSEG1 must be 5 Tq and the remaining 4 Tq are thelength of DTSEG2.The DBTP register fields are:•TDC to 1 (because baud-rate > 1M)•DSJW to 3 (DTSEG2 value)•DBRP to 0•DTSEG1 to 4•DTSEG2 to 3Note:From device’s reference manual: the actual interpretation by the hardware of this value is such that one more than the value programmed here is used. (see Section 5 Reference documents)3.2CAN-FD exampleThis paragraph shows how to configure the bit timing and the baud-rate in case of CAN-FD. The software mustconfigure two registers: NBTP and DBTP, former is for the arbitration part of a message and the latter one forthe data part of the message. The NBTP register programming does not change from the previous example.So below it is showed how to configure the baud-rate for the data part of a message. It is also detailed theconfiguration of transceiver delay compensation for CAN-FD mode (not available on standard CAN).Figure 4. DBTP registerThis register has an extra bit: Transceiver delay compensation (TDC). It enables the use of transceiver delaycompensation and must be set for baud-rate greater than 1 M. Using the TDC, the Software application can alsoconfigure a secondary sample point.The first sample point is to define the segments length in the bit timing configuration (DTSEG1 and DTSEG2),while the second sample point depends on transceiver delay compensation value.Supposing to configure the baud-rate of the message data part at 2 M and the two sample points at 60% and80% of the bit length. Below it will be showed how to program the registers:•TDC to 1 (because baud-rate > 1 M)•DSJW to this is used for the resynchronization and generally it could be equal to DTSEG2 value (maximum synch width).Supposing to have 20 MHz as protocol clock, and no other pre-scaler must be applied on this frequency, so theDBRP field will be set to 0. The time-quanta period will be 1/20000000 = 50 ns. The bit time (the length of a bit) at2 Mbit/s is 500 ns.Dividing the bit time period by the time-quanta period, it can be noticed that one bit contains exactly 10 time-quanta.Note:if the division result is not an integer value user has to try another pre-scaler and so DTSEG1 + DTSEG2 = 9 (this because SYNC_SEG is always 1 Tq).Supposing that it is needed a primary sample point at 60% of bit length then User can easily calculate that is 6 Tqon a bit length of 10 Tq.Considering one time-quanta of SYNC_SEG, then the DTSEG1 must be 5 Tq and the remaining 4 Tq are thelength of DTSEG2.The DBTP register fields are:•TDC to 1 (because baud-rate > 1 M)•DSJW to3 (DTSEG2 value)•DBRP to 0•DTSEG1 to 4•DTSEG2 to 3Note:from device’s reference manual: the actual interpretation by the hardware of this value is such that one more than the value programmed here is used (see Section 5 Reference documents)4Transceiver delay compensationAfter configuring the baud-rate and the primary sample points, the transceiver delay compensation needs to be calculated. The transceiver delay compensation has been added to CAN-FD protocol to compensate CAN transceiver’s loop delay at baud-rate greater than 1M, thereby enabling transmission with higher bit rates during the CAN FD data phase independent of the delay of a specific CAN transceiver. There is a relationship between TDCO (transceiver delay compensation offset) and secondary sample point:Note:this value is declared inside the transceiver specification and often called: loop delay.Secondary sample point position% = TDCO * (protocol_clock_period (ns) * (bitrate(Mbits) / 1000))So: TDCO = secondary sample point position% / (protocol_clock_period (ns) * (bitrate(Mbits) /1000))In this example:TDCO = 0.80 / (50 * 0.002) = 8Figure 5. Transceiver delay timing shows how the transceiver delay compensation works. In a glance, thecontroller calculates the delay between transmit and receive signals and tries to compensate that by using TDCO value. This is to sample, at the correct secondary sample point, where the controller checks the transmission errorsFigure 5.Transceiver delay timingTransceiver delay compensationReference documents 5Reference documents•RM0407, SPC584Cx/SPC58ECx 32-bit MCU family built on the Power Architecture for automotive body electronics applications reference manual•SPC58EHx, SPC58NHx datasheetAcronyms and abbreviations 6Acronyms and abbreviationsTable 1. AcronymsRevision historyTable 2. Document revision historyContentsContents1CAN overview (2)1.1Peripheral clocks (2)1.2Protocol clock selection (2)2Baud rate configuration (4)3Bit timing configuration (5)3.1Standard CAN example (5)3.2CAN-FD example (6)4Transceiver delay compensation (8)5Reference documents (9)6Acronyms and abbreviations (10)Revision history (11)Contents (12)IMPORTANT NOTICE – PLEASE READ CAREFULLYSTMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. 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