a r X i v :p h y s i c s /0611299v 1 [p h y s i c s .i n s -d e t ] 30 N o v 2006LC-DET-2006-008
November 2006
A proposed DAQ system for a calorimeter at the International Linear Collider M.Wing 1,?,M.Warren 1,P.D.Dauncey 2and J.M.Butterworth 1for CALICE-UK groups 1University College London ,2Imperial College London ?Contact:mw@https://www.doczj.com/doc/0c502674.html, Abstract This note describes R&D to be carried out on the data acquisition system for a calorimeter at the future International Linear Collider.A generic calorimeter and data acquisition system is described.Within this framework modi?ed designs and potential bottlenecks within the current system are described.Solutions leading up to a technical design report will to be carried out within CALICE-UK groups.
1Introduction
With the decision on the accelerator technology to be used for a future International Linear Collider(ILC),detector R&D can become more focused.The time-line for an R&D programme is also clearer with,assuming a technical design report to be written by2009,three years to de?ne the make-up of a given sub-detector.Within the CALICE collaboration,which is designing a calorimeter for the ILC,a collection of UK groups (CALICE-UK)are part of the initial e?ort to prototype a calorimeter composed of silicon and tungsten[1].The electromagnetic section of the calorimeter(ECAL)has been taking test-beam data at DESY and CERN in2006.The UK has designed and built electronics to readout the ECAL[4]-these are also now being used by the analogue hadronic calorimeter-and is taking part in the current data-taking period.Building on this expertise,CALICE-UK has de?ned an R&D programme.A signi?cant part of this programme is the design of the data acquisition(DAQ)system for a future calorimeter. In the work,DAQ equipment will be developed which attacks likely bottlenecks in the future system and is also su?ciently generic to provide the readout for new prototype calorimeters,such as the prototype to be built in the EUDET project[5].The main aim is to start an R&D programme which will work towards designing the actual DAQ system of the future calorimeter.Alternative designs of a DAQ system which could a?ect the layout of the?nal detector or functionality of components are also considered. The concept of moving towards a“backplaneless”readout is pursued.A strong under-pinning thread here is to attempt to make use of commercial components and identify any problems with this approach.Therefore the system should be easily upgradable, both in terms of ease of acquiring new components and competitive prices.
This note is organised as follows.The parameters of the superconducting accelerator design and calorimeter structure and properties which impinge upon considerations of the DAQ system for a calorimeter are discussed in Section2.The main body of the note in Section3discusses the DAQ design and proposes areas of R&D within it.The work is will investigate the three principal stages of the DAQ system:the connection along the calorimeter module;the connection from the on-to o?-detector;and the o?-detector receiver.In Section4a model DAQ system for the?nal ECAL is proposed. This necessarily makes many assumptions but gives an idea of the scale of the system involved:it can also be the start of an initial costing.The note ends with a brief summary in Section5.
The programme detailed below will allow CALICE-UK groups to continue to assist in development of new technologies for the DAQ system.We would expect to write a chapter in the future technical design report on the DAQ system for the calorimeter. For the?nal calorimeter,the DAQ should ideally be the same for the ECAL and HCAL. Although CALICE-UK has so far concentrated on the ECAL,our proposals for R&D contained in this document are su?ciently generic that both calorimeter sections should be able to converge to use the DAQ system we design.This will place us in a position to build the DAQ system for future large-scale prototype calorimeters(e.g.EUDET)and the?nal system.Indeed the principle of a generic design using commercial components should be applicable to many detector sub-systems.Therefore,the R&D to be performed
here may have consequences or applications to the global DAQ system for a future detector.
2General detector and accelerator parameters
The design[1]for a calorimeter for the ILC poses challenges to the DAQ system mainly due to the large number of channels to be read out.The TESLA design[1]for a sampling electromagnetic calorimeter is composed of40layers of silicon interleaved with tungsten. The calorimeter,shown in Fig.1,has eight-fold symmetry and dimensions:a radius of about2m,a length of about5m and a thickness of about20cm.Mechanically,the calorimeter will consist of6000slabs,of length1.5m,each containing about4000silicon p-n diode pads of1×1cm2,giving a total of24million pads.More recent designs for the detector collaborations consider fewer layers,29for LDC[2]and30for SiD[3],and also smaller pad sizes of5×5mm2,or even3×3mm2.
Figure1:View of the barrel calorimeter modules and detail of the overlap region between two modules,with space for the front-end electronics.
A generic scenario for the DAQ system is as follows.At the very front end(VFE), ASIC chips will be mounted on the PCBs and will process a given number of pads.The ASICs will perform pre-ampli?cation and shaping and should also digitise the data and may even apply a threshold suppression.The current design[6]of such chips has each containing64channels,although this may be higher in the?nal calorimeter.The ASIC power consumption has to be minimised as they are di?cult to cool due to the small gaps between layers which are required to take advantage of tungsten’s Moli`e re radius. The data will be digitised in the ASIC and transferred to the front-end(FE)electronics which are placed in the detector at the end of the slab as shown in Fig.1.It is expected that zero suppression will be done in the FE(using FPGAs)to signi?cantly reduce the
rate.The data will then be transferred o?the detector,probably via a network switch,
to a receiver of many PCI cards in a PC farm.
If we assume the TESLA design for data taking at800GeV,the following parameters
have to be considered.There will be a4886bunch crossings every176ns in a bunch train,giving a bunch train length of about860μs.The bunch train period is250ms,
giving a duty factor between trains of about0.35%.The ECAL is expected to digitise
the signal every bunch crossing and readout completely before the next bunch train.In a shower,up to100particles/mm2can be expected,which in a1×1cm2pad equates to
10000minimum ionising particle deposits.The ADC therefore needs a dynamic range
of14bits.Assuming no threshold suppression and that2bytes are used per pad per sample,then the raw data per bunch train is24·106×4886×2=250GBytes which equates to0.3-2.5MBytes for each ASIC depending on whether they process between 32and256channels.The data appears within a bunch train length of860μs giving a
rate out of the ASIC of0.4-3GBytes/s,which we take to be1GBytes/s from now on.
Threshold suppression and/or bu?ering(to allow readout between bunch trains)within the ASIC could reduce this rate.However,suppression in the ASIC may not be?exible enough compared with doing this in the FE and bu?ering requires some ASIC power to remain on between bunch trains,potentially generating too much heat.Hence the rates after the VFE depend on the assumptions made and system layout and will be discussed for each individual case where necessary.
3Design of a DAQ system
3.1Transmitting digitised data from the VFE chip
The transmission of digitised data from the ASIC is very heavily in?uenced by what can be done within the slab given the low heat-load requirements due to the di?culties of cooling.It is not yet known what the capabilities of the VFE ASIC will be,so various possibilities were considered.
In general,somewhere in the readout system,there will have to be an ADC and a threshold discriminator.These tasks could in principle be performed in either order and could be done in the VFE or in the FE.There is also the possibility of bu?ering events in either the VFE or FE.This would allow the data to be read out between bunch trains rather than bunch crossings.This entails a dramatic decrease in the rate of read out due to the large spacing between bunch trains.There is then a matrix of possibilities,with some number of the functionalities,ADC,thresholding and bu?ering,being done in the VFE or FE.Below the four possibilities are considered for the ADC and thresholding, and also the bu?ering in the VFE.
1.Neither ADC nor thresholding is done in the VFE
2.Only the ADC is done in the VFE
3.Only the thresholding is done in the VFE
4.Both are done in the VFE
5.Bu?ering done in the VFE
We consider that threshold discrimination is best done after the ADC step rather than before.This allows much easier monitoring the pedestals and noise,etc.,by allowing some readout at a low rate even when below the threshold.In addition,setting a stable analogue threshold is not easy;any drifts will change the level.The uniformity over all channels might not be good enough which would then require a large number of trim DACs.
1)If neither an ADC or threshold discriminator is built into the VFE ASIC(due to them taking too much power),then the raw analogue signals will be sent out to the FE. This is2k analogue channels which require around14bits precision,which is not trivial to achieve.Even if this can be done,digitising the data at the FE would be hard.The space is limited and so it is likely only a restricted number of ADCs could be mounted in this area.Assuming20channels of ADCs would be possible,then each would have to handle100pads,with these being multiplexed in turn into the ADC.To keep up with the sampling rate needed,i.e.176ns for each channel would therefore require the ADCs to sample at1.76ns.Finding a14-bit FADC which can do this would not be easy.The alternative would be to use an analogue pipeline;assuming one for each of the20ADC channels would result in each pipeline storing about500k analogue samples which is di?cult.Putting an analogue threshold in front of the ADCs would clearly cut the rate down but would need a major ASIC development to handle this;a variable length analogue pipeline with time-stamps would be needed.This is in addition to the pedestal monitoring problems mentioned above.
2)Only doing the ADC on the VFE seems a much more reasonable option.The14-bit requirement is much easier to achieve with a short signal path before the ADC.The digitised data can be transmitted from the VFE to the FE more easily than analogue data.The rates are not trivial however;these would be around50GByte/s per slab,or 1GByte/s from each wafer/ASIC.This is at the level where a?bre would be needed; commercial?bres now carry5GBytes/s.Fibres are also less noisy than copper.This use of?bres within the slab would raise many other issues such as the power needed to transmit the light out(or could it be supplied by an external laser and then only modulated on the ASIC),how to reliably attach the?bres at each end(a total of 300000?bres would be needed for6000slabs each with50ASICs),how large the?bre connectors would be(the total thickness within the slabs is limited to some mm only), etc..Although this is an active area of commercial development,it is not clear if opto-electronic intra-PCB communications will become standard enough on the time-scale needed[7].
It is clear some development would be needed for this to be an option;the equivalent system in ATLAS has three?bres transmitting a total of10MBytes/s with a2mm high connector needed.Self-aligning silicon-?bre interfaces are possibilities;while we could not do signi?cant R&D compared with the commercial sector,we could test industrial prototypes and do R&D in conjunction with industry.
Once the data are on a?bre direct from the ASIC,the idea of whether any FE electronics
would be needed at all was raised,as the?bre would go10s of metres,bypassing the FE completely.However,shipping out all the raw data to the o?ine seems an expensive overkill,but is considered as this may change with commercial development.
3)Only doing the threshold in the VFE su?ers from the same problems as mentioned above;there is a di?culty of monitoring the pedestals as well as the complexity of the ASIC needed to handle the channels.
4)Doing both ADC and threshold in the VFE places the easiest requirements on the FE,with a corresponding increase in di?culty for the VFE.Assuming the threshold is applied after the ADC,some communication of the threshold and other con?guration data from the FE to the VFE will still be needed.The data rate out is clearly reduced; it would be around400MBytes/s for the slab,or20MBytes/s for each wafer/ASIC. Although easiest for transferring data from the VFE to FE,due to the low rates,it is not clear if the threshold can be reliably applied in the VFE.This scenario also looks like the situation if the Monolithic Active Pixel Sensors(MAPS)technology-essentially a digital calorimeter-were used rather than silicon diodes.For the diode option in this scenario,it is also questionable as to whether signi?cant FE electronics logic is needed.As the ASIC performs both ADC and threshold suppression,the data could be transferred directly o?the detector.
5)It is generally assumed that bu?ering in the FE is possible,with large amounts of memory available in modern FPGAs.However,the issue of bu?ering in the ASICs is more technically challenging.The challenges for such a procedure are having a large enough memory integrated into the ASICs and the keeping the power low whilst the data is being read out between bunch trains.The advantages are clear:the rate of transmission from the ASIC to the FPGA is reduced by about two orders of magnitude. For the proposed electrical connections along the board this will ease the transmission signi?cantly.
We,therefore,propose R&D for two scenarios where only the ADC is done in the VFE and where the ADC and thresholding are done in the VFE,both coupled with bu?ering in the VFE because they provide realistic solutions and have complementary applications.In favour of only performing the ADC,any threshold suppression can be performed more accurately in the FPGA at the FE rather than in the VFE.When thresholding is also done in the VFE along with the ADC,the data transfer rate from the VFE and FE is signi?cantly smaller.A schematic of scenario2)is shown in Fig.2. In both scenarios,we intend to set-up a mock data transfer system which requires having a test board with FPGAs linked by?bres.This will simulate a link between the VFE ASICs and the FE FPGAs.Any developed system e.g.a new VFE chip design or the MAPS set-up could also be tested in our prototype system.We will also demonstrate that the system would work for the hadronic calorimeter as well as the ECAL.This would require modifying the system to have a more links but a lower rate. The prototype will incorporate,wherever possible,commercially available components such as Virtex-4FPGAs[8]which has multi-gigabit serial transceivers and is compatible with10/100/1000Mbit/s ethernet and PCI express x16and higher.
The?nal chip should have around64channels and would be embedded inside the de-
Slab
FE FPGA PHY
ASIC Data ASIC ASIC ASIC Conf
Clock + Control
Figure 2:Design of VFE to FE link.
tector.The ADC(s)should be included in the chip in order to output digital data serially at high rate (typically 1-2Gbit/s).The DAQ would thus look more like “an event builder”than a traditional DAQ.It would perform the data reformatting (from “?oating”gain +10bit to 16bit),calibration,possibly linearisation and some digital ?ltering.It is possible that at this level,some event processing will be performed.The other task of the DAQ is to load all the parameters needed by the front-end,control the power cycling and run the calibration.These speci?cations ?t in well with our current generic system.
The current version of the VFE ASIC chip [11]is being used to read out the existing CALICE ECAL.This chip does not meet the requirements for the ILC ECAL and the development of the design is an ongoing project in LAL/Orsay [6].In the next 1–2years,it is expected to have a version of such a chip with low enough power and noise that would serve as a realistic prototype.This ASIC is expected to have (at least)32channels,an internal ADC per channel,multiple gain ranges,and optional threshold suppression and digital bu?ering to reduce the required output rate.
Instead of using silicon diodes,the feasibility of using the MAPS technology is to be investigated [10].The use of this technology would also have an impact on the design of the DAQ system.Here,there would be no ADC and a threshold has to be applied on the wafer,by de?nition.The data rate for a ?nal detector would be 3GBytes/s per slab,or 150MBytes/s per wafer,which is low enough for non-?bre communication.
If threshold suppression or bu?ering could be done in the VFE ASIC,the rate to the FE would be reduced by two orders of magnitude.Current designs cannot do this and it may not even be desirable or practical,so we have to allow for data rates of order GByte/s needing to be transferred out of each VFE ASIC during the bunch train.Whether an electrical or optical connection would be needed has to be investigated.Although chip-to-chip ?bres are not yet standard technology,this is an active area of industrial research [7].
Issues of how the data would be transported from the VFE to FE have to be considered and can be done already without a real prototype.Transporting of order GByte/s of data over 1.5m in a very limited space is a challenge.The conventional approach would be to use copper but here the e?ects of noise and interference will have to be considered.
There is also the possibility of using optical ?bres although here there are also design considerations:the size of connectors would have to be investigated as the vertical clearance at the VFE is of the order of mm and the power needed to transmit light out would also need to be investigated.This work ties in closely with the mechanical and thermal aspects of the design.
In preparation for a real prototype,a test system will be built with a 1.5metre PCB containing FPGAs linked optically or electronically.The data transfer would then be considered as a function of the number of VFEs,whether zero suppression is done in the VFEs and whether data is bu?ered during the bunch train.The bandwidth and cross-talk of the data transfer can be simulated using CAD tools.The clock and control distribution from the front-end to the VFE chips can be investigated as to whether one transmission line per chip is needed or multi-drop is possible.
3.2Connection from on-to o?-detector
In this section,we consider two widely di?ering scenarios,(shown in Figure 3):
PC
1000x
Macro Event Builder PC Busy Network Switch
100Gb S l a b
Layer-1 Switch Macro Event Builder PC PC PC PC S l a b
Event
Builder
PCs Macro Event Builder PC Macro Event Builder PC
Macro Event Builder PC Event Builder PCs Event Builder PCs Large Network Switch Farm 5Tb S l a b S l a b S l a b S l a b S l a b
S l a b S l a b S l a b
S l a b S l a b S l a b S l a b S l a b S l a b
S l a b S l a b S l a b
S l a b S l a b S l a b
S l a b S l a b Large Network Switch Farm 5Tb Large Network Switch Farm 5Tb Figure 3:A comparison of the two scenarios,“Alternative con?guration”(left)and “Standard con?guration”(right)for the on-to o?-detector DAQ system.
Standard Con?guration
In our assumed standard detector con?guration,communication from the VFE will pass via the electronics at the FE to an o?-detector receiver.We assume that threshold suppression will be done at the FE,and hence the rate would be signi?cantly reduced from that at the VFE.Assuming that the rate is reduced to1%of the original data volume of250GBytes per bunch train and each sample above threshold needs a channel and timing label,the total data volume to be read out from the calorimeter is about 5GBytes or about1MByte per slab.These data have to be read out within a bunch train period of250ms,giving a rate of5MBytes/s.
Alternative con?guration
Here we imagine that the FE is removed and the communication is directly from the VFE to the o?-detector.We assume that the ASIC only digitises the data and250GBytes has to be transported o?the detector per bunch train.This will require a high-speed optical network.It should be noted,however,that the need for FE electronics also becomes questionable if more processing is done on the ASIC chip,such as threshold suppression. In such a scenario,transporting the data directly from the ASIC o?the detector could be done and so the FE would become redundant.The number of?bres required to read-out the24million channels would vary between750000to about90000depending on whether the ASIC handles32or256channels.If we assume that the diameter of a?bre is150μm,or with cladding250μm then if half of the circumference of12m had?bres running along it,the bundle would be up to1cm in depth,but could be as little as1mm,depending on the number of ASICs and hence?bres.This would leave ample room for other cables and power supplies.This concept would revolutionise the whole calorimeter design and so needs to be considered now when changes in its general structure could be considered.Our research in this area will provide important feedback to groups designing the ASIC chips.
The o?-detector receiver,as described later,is assumed to consist of PCI cards housed in PCs.The reliability of large PC farms is an issue for reading out the data;if one PC goes down,all of the data in that region of the calorimeter is lost.Current PC farms show a rate of1PC failure per day in a farm of200.This is not large but is also not small and would require some surplus of PCs(say10%)above the number required based just on the number of detector channels.For a?nal working calorimeter readout system these PCs would need to be repaired and put back into the system on a regular basis.The standard scenario would require less high-speed equipment o?the detector,whereas the alternative would require many optical?bres with dedicated optical switching.The alternative scenario would,however,remove material from inside the detector which would ease construction and have a potentially advantageous impact on event reconstruction and,hence,physics measurements.It would also reduce the number of processing components within the detector which could be attractive since they would be inaccessible for long periods of time.
Using the experience gained from the two scenarios above,a hybrid path can be ex-plored.By optimising the functionality in the VFE and matching it to an FE,overall instantaneous data rates can be reduced as well as lowering?bre count.For example, if data is bu?ered in the VFE,some form of passive multiplexer can be envisaged that
will combine data from all the VFEs.This could take the form of spliced optic-?bres, or an OR gate.This would not necessarily remove the need for an FE,but the reduced size and complexity will have many bene?ts(thermal,con?guration time,SEUs,cost, etc.).
To transmit data onto the detector,we will attempt to use the same commercial hard-ware used for o?-detector communication.The requirements are di?erent,though,as the detector front-end requires clock and synchronisation signals as well as low-level con?guration and data https://www.doczj.com/doc/0c502674.html,mercial network hardware is not ideally suited to synchronous tasks but the signi?cant cost and reliability bene?ts make it worthy of in-vestigation.This is split into two areas:failsafe con?guration prior to normal running, and clock and control signal distribution.
Failsafe Con?guration In a scenario requiring an FPGA on-detector,it is imperative that the device can be re-con?gured remotely.This is necessary not only because of the number of FPGAs but also because of the uncertainty in the detector performance in terms of data suppression,pedestal drifts,bad channel identi?cation etc.,all of which have to be implemented in the FE FPGA.The optimal algorithms for these tasks will only be determined after some experience of operating the calorimeter.As the FPGAs are relatively inaccessible,it is important that a failsafe method of reseting and re-con?guring the devices exists.
Avoiding the use of additional control lines necessitates a means to extract signals from the communications interface.Most probably this will involve“spying”on the serial data line.
Of primary importance is to force the FPGA into a known state under any conditions (i.e.a hard-reset).It may simply be possible to send an exceptionally long series of“1”s to the slab(say40M=1second)where an RC type-circuit with a long time-constant will trigger the reset.A more complex method would require some discrete logic(like a shift-register with parallel output into a comparator)searching the incoming data-stream for a“magic”number.Power cycling the board is also a(less elegant)solution, but still requires attention in circuit design to ensure the FPGA will boot.
Once hard-reset,the FPGA will follow its start-up logic to initiate the boot-making use of2distinct methods:
?Use a non-volatile base con?guration that is either hardwired into the FPGA or provided by a EEPROM external to the FPGA.In this case the FPGA would assist in writing the con?guration to its internal RAM and then issue a re-boot-using-internal-con?guration command to itself.
?By waiting for external stimulus(usually a clock)to control data the data being fed into the device.This requires additional hardware to format the the serial-data into data/clock/control for FPGA consumption.
In both cases some external hardware is required,the amount of which will only fully understood after a more detailed evaluation.A possible outcome could be that a small non-volatile programmable device could provide the most?exible solution,but the e?ects of radiation need further examination.
Larger devices with non-volatile con?guration memories could be used for the entire front-end logic,but apart from the increased cost and limited re-programming cycles making these less desirable,these devices are not able to re-program themselves. Reliability in the detector environment of these memories over the lifetime of an ex-periment,as well as SEUs,also need to be addressed.Non-volatile memories have limited programming cycles,whereas modern SRAM-based FPGAs boast that they can re-con?gured an in?nite number of times.By refreshing the con?guration periodically, the e?ect of SEU corruption can be minimised.Considering an FPGA with one million logic gates(which speci?es a4Mbit PROM),con?guring this device at40MHz would take100ms-a re-con?g every250ms bunch-train!
Being able to re-con?gure the FE when needed also allows the selection of a smaller component that can be con?gured for speci?c function,rather than a large one-size?ts all device.
Reducing the number of components on the front-end-module is advantageous from a cost,reliability and dead material point of view,so we will focus on methods of generating a data-stream onto the detector that requires the minimum of components to extract signals from the physical network interface module.
Clock and Control To ensure the on-detector electronics captures data from actual collisions,all components in the detector are synchronised to the bunch-crossing clock. Bunch-train start,stop and ID signals are also be required.Traditionally this is done with a bespoke,low-latency,highly synchronous system,but here we will look at using a commercial network switch.
Switches are not designed for synchronous signal fanout.In fact the now obsolete forerunner to the switch,the hub,is much better suited to the task.Modes for signal broadcasting do exist,but these need to be closely examined.Studies on latency and port-to-port skew will be undertaken.
To obtain maximal control over timing,the lowest level protocols will need to be used. Directly accessing the network at the physical layer(i.e.as a simple serial link)would facilitate complete control over data-packet composition and timing.For this a specialist and customisable network interface card is required.
To regenerate the clock at the detector end,the time structure of the data transmitted needs to be structured accordingly.This would probably take the form of a local os-cillator being periodically resynced to the data clock.As the bunch-crossing interval is 7ns,a1Gbit(1ns)link would be the minimum rate needed.Board-level signals,such as train-start may also need to be decoded directly from the data stream(as with the failsafe system above).
In summary,this is as an investigation to verify that a clock,control and con?guration system can be constructed using commercial network hardware for distribution.
3.3O?-detector receiver
An ideal system would have all data from the detector for each bunch train sent directly to a single PC where full event reconstruction would be performed.However,considering that the electromagnetic calorimeter alone will contain24million channels,even after data suppression this seems unfeasible.
It would,however,be desirable to geographically group as many channels as possible at a processor.This would permit broader local clustering which could be used as an input to full event reconstruction later.The fundamental questions to be answered are how much of the calorimeter can be received into one PC and how much needs to be received to make local clustering e?ective.The impact this has on full event reconstruction and on simulated physics needs to be evaluated.This task therefore involves a combination of hardware and simulation work.
We propose a system comprising PCI cards(see Fig.4)mounted in PCs.These cards will provide timing,clock,control and con?guration data,be capable of performing local clustering,as well as being able to be re-con?gured to act as data transmitters to exercise the receivers.We will use the“new”PCI Express bus standard[9]as this o?ers increased bandwidth and?exibility by using many high bandwidth serial links (called lanes)instead of a single parallel bus.It is expected to be scalable due to future increases in the number of lanes.Aside from providing an interface to the processor, lanes can be setup between cards,allowing advanced clustering prior to processing. Although it is hard to predict what technology will be available for the?nal system, gaining experience with serial bus technologies now,will prove valuable for estimates of how much data can be realistically processed by a computer and help us understand the bene?ts and bottlenecks,as well as the scalability.
Much of this DAQ workpackage relies on novel methods in using network infrastructure, so a card providing both direct access to the network hardware and room to build any other functionality is useful.This applies to the PCI Express interface too,where the card will be able to test-drive the bus and provide debug feedback and monitoring.
4A model DAQ system for the ECAL
As has been discussed in this note many options exist for the functionality of the com-ponents at various stages.It is therefore di?cult to make a de?nitive statement on what a DAQ system would like and how many components it would have.However, work is ongoing to try and do as much of the work(data reduction)as possible on the detector,thereby reading out as little as possible.Therefore we consider that the ADC and thresholding are done in a32-channel VFE and bu?ering in the FE.Under this model and making reasonable assumptions on the data rate a model system is detailed below.
The raw data size is assumed to be2Bytes per channel with an additional4Bytes per channel needed for a timing label.Imposing the threshold suppression reduces the data rate by a factor of100,leading to a data size for the whole detector of(24×106×4886×
P C M o t h e r b o a r d PCI-Receiver
Large FPGA Memory Micro-Processor/s
TX Module RX Module RX Module RX Module RX Module PCIe Interface CPU Inter-Slot
Fast Control
Interface would clearly be advantageous to bundle the data from several slabs together.Bundling half a tower of 20slabs would give a rate of 0.75Gbit/s which could be adequately read out using current ?bres.Such a grouping would lead to 300?bres coming o?the detector.Assuming a PCI card which can receive 8?bres,this would require 38PCI cards.With a PC hosting 2such cards than a system of 19PCs would be required.We then assume a 20%contingency for more ?bres reading out neighbouring areas to allow for redundancy and for faulty PCs or PCI cards.This gives a total of about 50PCI cards housed in 25PCs a clearly manageable number for such a granular calorimeter.5Summary
A conceptual design of a data acquisition system for the ILC calorimeter has been discussed.The concept relies heavily on commercial equipment and is generic such that it could be applied to other detector systems.Potential bottlenecks have been identi?ed and form a programme of research and development of the next three to four years for the CALICE-UK groups.Bench tests and real-time tests with prototype calorimeters,within the EUDET project,will be undertaken.After this period,a technical design of the data acquisition system will be possible.
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三分类血液细胞分析仪与 五分类区别 This manuscript was revised by the office on December 22, 2012
三分类血液细胞分析仪与五分类区别 血液细胞分析仪又名血细胞分析仪，目前市场上的血细胞分析仪主要分为全自动的和半自动的仪器。随着该仪器成为医院临床检验的必备仪器以及近几年来计算机技术的不断发展，产品也从三分群转向五分群，从二维空间转向三维空间，对于三分类血液细胞分析仪与五分类仪器有何区别呢？ 1、仪器检测原理的区别 三分类的仪器大都采用电阻抗检测技术，由信号发生器、放大器、甄别器、阀值调节器、检测计数系统和自动补偿装置组成；五分类的产品大都采用光散射检测技术，主要由激光源（多采用氩离子激光器，以提供单色光）、检测区（主要由鞘流形式的装置构成，以保证细胞混悬液在检测液流中形成单个排列的细胞流）、检测器（散射光检测器系光电二极管，用以收集激光照射细胞后产生的散射光信号；荧光检测器系光电倍增管，用以接受激光照射荧光染色后细胞产生的荧光信号）。 2、白细胞分类方法的区别 三分类产品是将白细胞分为淋巴细胞，单核细胞，粒细胞；五分类的仪器则是将白细胞分为淋巴细胞、单核细胞、粒细胞（中性细胞、嗜酸性细胞、嗜碱性细胞）。 3、适用客户的区别 三分类血液细胞分析仪主要适用于三甲以下的医院、妇幼保健院、诊所以及社区服务中心等，价格相对要便宜很多；而五分类的产品主要用于三甲以上的医院，价格以及试剂方面要贵很多。 随着当前临床检测的需要，各种血液细胞分析仪不断涌现，小编个人认为产品没有好坏之分，主要是选择合适自己的，客户可根据临床检测样本量的多少以及检测标准来选择
第一章系统的组成和分类 干粉灭火系统根据其灭火方式、保护情况、驱动气体储存方式等不同可分为10余种类型，本节主要介绍系统的组成及其分类。 一、干粉灭火系统的组成 干粉灭火系统在组成上与气体灭火系统相类似。干粉灭火系统由干粉灭火设备和自动控制两大部分组成。前者由干粉储存容器、驱动气体瓶组、启动气体瓶组、减压阀、管道及喷嘴组成；后者由火灾探测器、信号反馈装置、报警控制器等组成，见图3-8-1所示。 二、干粉灭火系统的分类 （一）按灭火方式分类
1．全淹没干粉灭火系统 全淹没干粉灭火系统是指将干粉灭火剂释放到整个防护区，通过在防护区空间建立起灭火浓度来实施灭火的系统形式。该系统的特点是对防护区提供整体保护，适用于较小的封闭空间、火灾燃烧表面不宜确定且不会复燃的场合，如油泵房等类场合。 2．局部应用干粉灭火系统 局部应用干粉灭火系统是指通过喷嘴直接向火焰或燃烧表面喷射灭火剂实施灭火的系统。当不宜在整个房间建立灭火浓度或仅保护某一局部范围、某一设备、室外火灾危险场所等，可选择局部应用干粉灭火系统，例如用于保护甲、乙、丙类液体的敞顶罐或槽，不怕粉末污染的电气设备以及其他场所等。 （二）按设计情况分类 1．设计型干粉灭火系统 设计型干粉灭火系统是指根据保护对象的具体情况，通过设计计算确定的系统形式。该系统中的所有参数都需经设计确定，并按要求选择各部件设备型号。一般较大的保护场所或有特殊要求的场所宜采用设计型系统。 2．预制型干粉灭火系统 预制型干粉灭火系统是指由工厂生产的系列成套干粉灭火设备，系统的规格是通过地保护对象做灭火试验后预先设计好的，即所有设计参数都已确定，使用时只需选型，不必进行复杂的设计计算。保护对象不很大且无特殊要求的场合，一般选择预制系统。 （三）按系统保护情况分类 1．组合分配系统 当一个区域有几个保护对象且每个保护对象发生火灾后又不会蔓延时，可选用组合
PLC编程语言/操作指令/使用步骤详解 [导读]控制系统流程图是一种较新的编程方法。它是用像控制系统流程图一样的功能图表达一个控制过程，目前国际电工协会（IEC）正在实施发展这种新式的编程标准。 一、PLC编程语言 1．梯形图编程语言 梯形图沿袭了继电器控制电路的形式，它是在电器控制系统中常用的继电器、接触器逻辑控制基础上简化了符号演变来的，形象、直观、实用。 梯形图的设计应注意以下三点： （一）梯形图按从左到右、从上到下的顺序排列。每一逻辑行起始于左母线，然后是触点的串、并联接，最后是线圈与右母线相联。 （二）梯形图中每个梯级流过的不是物理电流，而是“概念电流”，从左流向右，其两端没有电源。这个“概念电流”只是形象地描述用户程序执行中应满足线圈接通的条件。 （三）输入继电器用于接收外部输入信号，而不能由PLC内部其它继电器的触点来驱动。因此，梯形图中只出现输入继电器的触点，而不出现其线圈。输出继电器输出程序执行结果给外部输出设备，当梯形图中的输出继电器线圈得电时，就有信号输出，但不是直接驱动输出设备，而要通过输出接口的继电器、晶体管或晶闸管才能实现。输出继电器的触点可供内部编程使用。 2．语句表编程语言
指令语句表示一种与计算机汇编语言相类似的助记符编程方式，但比汇编语言易懂易学。一条指令语句是由步序、指令语和作用器件编号三部分组成。 3．控制系统流程图编程图 控制系统流程图是一种较新的编程方法。它是用像控制系统流程图一样的功能图表达一个控制过程，目前国际电工协会（IEC）正在实施发展这种新式的编程标准。 二、基本指令简介 基本指令如表所示 取指令 LD I、Q、M、SM、T、C、V、S、L 常开接点逻辑运算起始 取反指令 LDN I、Q、M、SM、T、C、V、S、L 常闭接点逻辑运算起始 线圈驱动指令
内控案例专栏系列一：促销活动中的舞弊防范与内部控制 一、案例简介：促销存漏洞，一人独得200个特等奖 据媒体报道，重庆某知名电器连锁公司广告宣传部主管王某，在一年多时间里创下了一个“中大奖”的纪录：从2007年9月到2008年12月，他一人先后狂中200个特等奖，独得奖金79万多元。 然而，王某之所以能疯狂中奖，靠的不是运气，而是在自家公司开展的有奖促销活动中欺上瞒下，假冒顾客名义领奖。该公司2007年9月至2008年12月期间，开展了一场声势浩大的“刮刮卡刮奖促销”活动，其中最吸引人的是直返现金4999元的特等奖。奇怪的是，在这一年多时间里，公司30多家门店接待了成千上万名顾客，也有人中过奖金额度比较低的奖，却没有一名顾客刮中过特等奖，200个特等奖就此“不翼而飞”。一方面，顾客对特等奖迟迟难现充满疑惑，另一方面，该公司却一直在为并不存在的特等奖“埋单”──每隔一段时间，都有几名顾客中了特等奖的资料传来，相关材料也很完备，公司便一直按规定给予了报销。 直到2008年12月，公司在一次审核过程中，发现一些特等奖领奖人购物发票上的姓名和领奖人的身份证复印件不一致，奖金有被侵占的嫌疑。公司广告宣传部主管王某因有重大嫌疑，经公司监察部询问，他向公司总经理承认了自己冒领奖金的事实。 按照常理，要独揽这些特等奖，王某起码要通过三道关卡：一是要在众多奖券中，准确摸清楚哪些能中奖；二是要设法防止这些“特殊奖券”被投放到各个分店，以免流入顾客手中；三是向财务部门冒领奖金时，必须提供中奖人的购物凭证和身份证明，并成功通过上级的审核。 巧合的是，这些关卡看似难以逾越，实际上的“把关权”却都掌握在王某手中。这才导致他私吞大奖如探囊取物。记者采访获悉，这批“刮刮卡”的奖券是由河北省一家印刷厂统一印制的，王某恰恰负责联系印刷厂。他以“方便分配奖券”的名义，要求印刷厂把特等奖券和其他奖券分开，就此成功地把特殊奖券“挑”了出来。他再利用自己投放奖券的权力，把特等奖券全部扣留，一个也没有投放到分店。 按照规定，分店的中奖顾客信息和报销费用也必须经过王某审核。政法机关办案人员介绍，王某收集了一大批顾客的购物发票复印件，又从亲戚朋友那里弄来了一些身份证复印件，以“他人代领”的名义，炮制了一批“中奖材料”，分批向公司财务部冒领奖金，连连得手。 记者在采访中发现，王某作为企业的一名中层管理人员，之所以能轻易地侵吞奖金，关键在于他一手握着奖券的发放权，另一手握着领奖的审核权，在一定程度上是“自己监督自己”。重庆国美电器公司下属30多家分店尽管有众多员工，对于特等奖“难产”也未必没有疑问，但由于难以监督上级，只能任由王某“疯狂领奖”，直至东窗事发。
第三篇应用系统 应用系统是把概念、技术和企业的实际相联系的桥梁。它是建筑在硬件、系统软件、甚至通用软件上的系统，它直接面对用户，面对企业的高层领导、中层管理和基层业务人员。 本篇在介绍了应用系统的分类以后，着重介绍四种应用系统，即层次信息系统，只能信息系统，组织信息系统和决策信息系统，见图III.1 应用系统 层次信息系统职能信息系统组织信息系统决策支持系统 图III.1 几种应用系统 通过本篇的讲述，使读者对应用系统有个全面的了解，了解应用系统是什么? 能作什么? 从而具体了解计算机的潜力，善于把IT技术应用于管理，为学习系统开发和管理打下基础。
第11章应用系统分类 11．1 信息系统角色的演变 企业或组织中信息系统所担当的角色在不断的改变扩张。不计较分类的严格性，其演变有以下过程： 1950——1960年数据处理系统 电子数据处理(electronic data processing, EDP) 业务处理(transaction Processing, TP) 记录保存(record keeping) 传统的簿记应用。 1960—1970年管理报告系统 管理信息系统(狭义) 管理报告系统(management reporting systems) 信息管理系统(information management systems，IMS) 1970—1980年决策支持系统 决策支持系统(decision support systems，DSS) 管理支持系统(management support systems, MSS)等 1980—1990年战略和终端用户支持系统 终端用户运算系统(end-user computing systems，EUCs) 主管信息系统(executive information systems，EIS) 主管支持系统(executive support systems, ESS 专家系统(expert systems，ES) 战略信息系统(strategic information systems，SIS)等 以上这么多名词是根据其出现的前后顺序列出的，它也可以算分类的一维，就是时间维，但是按照其他概念的分类来说，它的概念是混乱的。分类应当根据一定的原则，一种原则形成分类空间中的一维，沿着这些维构成分类空间中的一个坐标系，其概念是由浅人深，而且是不相交的。分类空间中的坐标应当是正交的，即每一维是独立的。根据这个原则我们在下节讨论一下应用系统的分类。
第一章 可编程控制器简介 可编程序控制器，英文称Programmable Controller ，简称PC 。但由于PC 容易和个人计算机（Personal Computer ）混淆，故人们仍习惯地用PLC 作为可编程序控制器的缩写。它是一个以微处理器为核心的数字运算操作的电子系统装置，专为在工业现场应用而设计，它采用可编程序的存储器，用以在其内部存储执行逻辑运算、顺序控制、定时/计数和算术运算等操作指令，并通过数字式或模拟式的输入、输出接口，控制各种类型的机械或生产过程。PLC 是微机技术与传统的继电接触控制技术相结合的产物，它克服了继电接触控制系统中的机械触点的接线复杂、可靠性低、功耗高、通用性和灵活性差的缺点，充分利用了微处理器的优点，又照顾到现场电气操作维修人员的技能与习惯，特别是PLC 的程序编制，不需要专门的计算机编程语言知识，而是采用了一套以继电器梯形图为基础的简单指令形式，使用户程序编制形象、直观、方便易学；调试与查错也都很方便。用户在购到所需的PLC 后，只需按说明书的提示，做少量的接线和简易的用户程序编制工作，就可灵活方便地将PLC 应用于生产实践。 一、PLC 的结构及各部分的作用 PLC 的类型繁多，功能和指令系统也不尽相同，但结构与工作原理则大同小异，通常由主机、输入/输出接口、电源扩展器接口和外部设备接口等几个主要部分组成。PLC 的硬件系统结构如下图所示： 图1-1-1 1、主机 主机部分包括中央处理器（CPU ）、系统程序存储器和用户程序及数据存储器。CPU 是PLC 的核心，它用以运行用户程序、监控输入/输出接口状态、作出逻辑判断和进行数据处理，即读取输入变量、完成用户指令规定的各种操作，将结果送到输出端，并响应外部设备（如电脑、打印机等）的请求以及进行各种内部判断等。PLC 的内部存储器有两类，一类是 接触器 电磁阀指示灯电源 电源 限位开关选择开关按钮
三分类血液细胞分析仪与五分类区别 血液细胞分析仪又名血细胞分析仪，目前市场上的血细胞分析仪主要分为全自动的和半自动的仪器。随着该仪器成为医院临床检验的必备仪器以及近几年来计算机技术的不断发展，产品也从三分群转向五分群，从二维空间转向三维空间，对于三分类血液细胞分析仪与五分类仪器有何区别呢？ 1、仪器检测原理的区别 三分类的仪器大都采用电阻抗检测技术，由信号发生器、放大器、甄别器、阀值调节器、检测计数系统和自动补偿装置组成；五分类的产品大都采用光散射检测技术，主要由激光源（多采用氩离子激光器，以提供单色光）、检测区（主要由鞘流形式的装置构成，以保证细胞混悬液在检测液流中形成单个排列的细胞流）、检测器（散射光检测器系光电二极管，用以收集激光照射细胞后产生的散射光信号；荧光检测器系光电倍增管，用以接受激光照射荧光染色后细胞产生的荧光信号）。 2、白细胞分类方法的区别 三分类产品是将白细胞分为淋巴细胞，单核细胞，粒细胞；五分类的仪器则是将白细胞分为淋巴细胞、单核细胞、粒细胞（中性细胞、嗜酸性细胞、嗜碱性细胞）。 3、适用客户的区别 三分类血液细胞分析仪主要适用于三甲以下的医院、妇幼保健院、诊所以及社区服务中心等，价格相对要便宜很多；而五分类的产品主要用于三甲以上的医院，价格以及试剂方面要贵很多。 随着当前临床检测的需要，各种血液细胞分析仪不断涌现，小编个人认为产品没有好坏之分，主要是选择合适自己的，客户可根据临床检测样本量的多少以及检测标准来选择购买三分类的还是五分类的产品。现在临床应用而言，三分类的仪器应用更为广泛，目前汉方的血液细胞分析仪均采用三分类的仪器，无论是在价格上、操作方法上，还是在检测结果上都不亚于五分类仪器。
一、分析仪器的分类 （一）、理化分析仪器 （二）、生化分析仪器 （三）、物化分析仪器 （四）、常规实验仪器 （五）、专用分析仪器 （六）、样品处理设备 （七）、电子仪器设备 （一）、理化分析仪器 1、色谱类分析仪器 2、光谱类分析仪器 3、电化学分析仪器 4、元素分析仪器 5、光学分析仪器 6、玻璃仪器 1、色谱分析 1）气相色谱仪2）液相色谱仪3）凝胶色谱仪4）离子色谱仪5）质谱仪6）薄层色谱仪7）毛细管电泳8）其他 2、光谱分析 1、可见分光光度计 2、紫外可见分光光度计 3、近红外分光光度计 4、红外分光光度计 5、原子吸收分光光度计 6、原子荧光分光光度计 7、荧光分光光度计 8、光声分光光度计 9、光电直读光谱仪10、ICP 光谱仪11、MPT光谱仪12、激光光谱仪13、拉曼分光光度计14、光谱成像仪15、旋光仪16、色度仪17、其他 3、电化学分析产品 1）电导分析/PH分析2）电位分析3）电解库仑分析4）极谱伏安分析5）流动注射分析仪 6）滴定仪7）电泳仪8）COD9）BOD10）其他 （二）生化仪器分类 1、分子生物学类仪器 2、细胞生物学类仪器 3、微生物学类仪器 4、通用生物实验食品 1、分子生物学类仪器 1）PCR仪2）电泳仪3）凝胶成像系统4）酶标仪/洗板机 2、细胞生物学类仪器 1）显微镜2）高压破碎仪3）超声波破碎仪4）多参数生化分析仪 3、微生物学类仪器 1）菌落计数器2）全自动微生物鉴定仪 4、通用生物实验仪器 1）高压灭菌器2）离心机3）移液器4）培养箱 （三）、物化分析仪器 1、粘度计 2、熔点仪 3、密度计 （四）、常规实验仪器 1、干燥箱 2、电炉 3、低温冰箱/保存箱 4、摇床（振荡器） 5、灭菌器 6、恒温水浴/油浴： 7、超净工作
当前，系列凶杀、系列盗窃、系列强奸等多种类型的案件正在以较快的速度增长，成为社会和谐的干扰因素。对于系列性案件的侦破而言，认真分析系列性案件的发生、发展过程及其各阶段的特点，从而厘清明晰的侦查思路具有非常重要的意义。 一、分析系列性案件各阶段特点的意义任何事物和现象都有其发生、发展和形成的过程，其过程往往表现出某些规律和特点，研究这些规律和特点有利于对该事物或现象的认识。系列性案件是作案人连续多次所作的案件。在多起作案过程中，必然会存在着某些规律性的表现。分析系列性案件的发生、发展过程，既有利于总结作案人作案规律和作案手段、实施方法以及心理状态，同时还有利于发现作案分子的作案人数、活动地域、侵害目标等方面的特点，从而为侦查措施的制定，侦查工作的切入提供依据。 显然，每一宗系列性案件的性质不尽相同，作案动机不尽一致，参与作案的人数多少不等，实施作案过程中使用的具体手段、方法多种多样，但所有的系列案件总是在第一起案件发生时，因公安机关未能迅速破案，作案人未受到及时打击，又连续多次作案，以致形成系列性案件，都有着从少到多，从小到大，从轻到重的发展过程。笔者通过对近百起各类系列案件的研究，按照作案人员活动区域、 参与人数、案件大小、案件性质以及反侦查意识等几方面考量，认为其形成过程一般可分为初始期、发展期和疯狂期三个阶段。 二、系列性案件的初始期分析（一）初始期特点 初始期泛指作案人开始作了一两起案件之后，犯罪活动未予停止，又连续作案若干起的一定阶段。这一时期的主要特点是：作案人经验少，胆量小，遇有某些障碍或反抗可能会放弃；侵害对象单一；犯意表现不十分坚定；活动范围相对较小；现场反映紊乱。具体来说：1.就作案参与人员而言，多为单独一人实施，若是多人，作案时一般也无核心人物，人员的聚合处于松散状态。2.就作案活动区域而言，一般多在作案人居住地或落脚地不远的范围内。在作案活动范围的大小确定上，既要考虑作案分子徒步、骑车，也要考虑作案分子乘坐汽车、摩托车、农用机动车辆等，因而对作案人活动区域的判断视野要求开阔。如果现场上发现遗留有交通工具印迹，则据此判断准确性更高。3.就作案指向的目标而言，侵害的对象多为同类，所作案件类型单一，一起案件往往只涉及一种犯罪性质。如系列性强奸案件，多是涉及性侵害方面的犯罪，很少获取受害人随身携带的钱财物品等。4.就发案时间而言，前案与后案间隔时间较长。这一时期作案人犯罪心理不稳 系列性案件的阶段性特点分析 韩 铮 （河南公安高等专科学校侦查系，河南郑州450002） 摘 要：系列性案件的发生发展过程可分为初始期、发展期和疯狂期三个阶段。各阶段在案件中表现为不同的 特点。对各时期侦破案件的切入点进行准确的把握， 可为侦破系列性案件提供切实的思路和侦查方法。关键词：系列性案件；初始期；发展期；疯狂期；中图分类号：D631 文献标识码：A 文章编号：1008-2433（2009）03-0122-03 收稿日期：2009-03-02作者简介：韩 铮（1973—），男，河南沈丘人，河南公安高等专科学校教师。 2009年6月 河南公安高等专科学校学报Jun.2009 第3期（总第106期） Journal of Henan Public Security Academy No.3 122
2013年效果图收费标准 一：家居收费标准： 1、单层楼层客厅：400元/张 2、复式楼层客厅：450-550元/张（看复杂程度） 3、别墅客厅：450-550元/张（看复杂程度） 4、卧室：300元/张 餐厅：300元/张 5、别墅起居室：300-500元/张 7、别墅外观：600-1200元/张 以上纯中式、欧式设计另加100元/张（简中简欧除外） 二：商业空间收费标准：- 办公类：- 1、大型办公室：400-800元/张（看大小） 2、前厅：：250-400元/张 3、过道：200-400元/张 4、单独办公室：300-500元/张（看大小） 5、小型会议室：300-600元/张（看大小） 6、大型会议室：400-800元/张（看大小） 娱乐类：- 1、大厅：600-900元/张 2、过道：400-800元/张 3、小型包厢：300-500元/张 4、大型包厢：500-800元/张 酒店类： 1、大堂（总台）：600-1000元/张 2、过道：300-500元/张 3、客房：300-元/张 4、高级客房：400-600元/张 5、休息大厅：300-700元/张 6、宴会大厅：500-900元/张 7、餐厅包厢：300-600元/张 8、餐厅豪华包厢：500-800元/张 以上所有视具体设计的难易及空间大小定价。 服务说明： 1、需求方需提供所要表达空间完整的平、地、吊以及各立面设计图。 2、同一空间内不同角度效果表现增加一个镜头另增收50% 3、修改局部及色彩免费更改，设计方案大面积变动更改视程度另收费（35%-50%）。 4、谢绝无完整设计图或无设计要求说明制作效果图。 5、以上收费仅限效果成图，不负责打印出图，成图的3D模型恕不提供。
有一种聆听叫收获满满，心灵的洗礼精神的升华 ----听丁榕老师报告有感 周口中英文学校杨卫国 丁榕老师简介： 丁榕，北京市特级教师。曾任北京四中初中、高中班主任、教导主任。获得国务院享受特殊津贴专家、全国优秀班主任、北京市模范班主任、北京市优秀共产党员等称号。现任北京市西城区青少年心理教育研究中心主任、德育教研室主任，中国心理卫生协会青少年心理卫生专业委员会专家委员。 2012年4月20日在校领导的安排下，我有幸参加班主任培训班的学习，聆听一场难得的报告，使自己在繁忙的工作之余有一次自我提升的机会。来自北京四中的著名教育专家、全国优秀班主任丁榕老师的精彩报告会以《做一名幸福、快乐、有成就的班主任》为主题，从更新观念、改进方法、拓宽途径三个方面详尽阐述了为师之道。整场报告会持续了三个多小时，已经67岁的丁老师却一直站在讲台，握着遥控鼠标，用她那沙哑的嗓音，声情并茂地讲述着她从教将近五十载的一个个生动鲜活的事例。丁老师的报告以具体的班主任工作为实例，从她的演讲中，我们除了学到许多班主任工作的技能技巧，更多的是感受到丁老师那伟大的师爱和崇高的人格魅力。 丁老师就如何做一名幸福、快乐、有成就的老师总结为“五步曲”：择业、创业、乐业、敬业和爱业。 （一）择业--找准位置。选择了教师这个职业，你就要选择快乐，因为不快乐的老师会影响学生的一生。接受改变不了的，改变能够改变的。丁老师告诉 我们要做最合适的自己，如果你无法改变现状，你就不要怨声载道，而是努力改变自己。无论是你选择了教师职业，还是教师职业选择了你，接受你改变不了的，改变你能改变的。做不了高山上的青松，就做大树；做不了大树，就做路边的小树；做不了小树，就做灌木；做不了灌木，就做一棵小草。决定成败的不是你的尺寸大小，而是做一个最好的你。所以正如丁老师所说的那样我们应该正视现实，接受改变不了的，改变能够改变的，也就是更新自己的观念，改变做事的态度，让我们随时都能有一个平和的心态，用平和的心态去看待周围发生的一切，做什么都争取做最好的，我想我们就已经为快乐幸福做了最好的铺垫。她的一家三代都搞美术，外公是中央美术学院的教授，妈妈是个画家。１９６３年，她从北京工艺美术
英文助记符德文助记符程序元素分类说明 ---| |--- ---| |--- 位逻辑指令常开接点（地址） ---|/|--- ---|/|--- 位逻辑指令常闭接点（地址） ---( ) ---( ) 位逻辑指令输出线圈 ---(#)--- ---(#)--- 位逻辑指令中间输出 ==0 ---| |--- ==0 ---| |--- 状态位指令结果位等于“0” >0 ---| |--- >0 ---| |--- 状态位指令结果位大于“0” >=0 ---| |--- >=0 ---| |--- 状态位指令结果位大于等于“0”<=0 ---| |--- <=0 ---| |--- 状态位指令结果位小于等于“0” <0 ---| |--- <0 ---| |--- 状态位指令结果位小于“0” <>0 ---| |--- <>0 ---| |--- 状态位指令结果位不等于“0”ABS ABS 浮点算术运算指令浮点数绝对值运算 ACOS ACOS 浮点算术运算指令浮点数反余弦运算 ADD_DI ADD_DI 整数算术运算指令双整数加法 ADD_I ADD_I 整数算术运算指令整数加法 ADD_R ADD_R 浮点算术运算指令实数加法 ASIN ASIN 浮点算术运算指令浮点数反正弦运算 ATAN ATAN 浮点算术运算指令浮点数反正切运算 BCD_DI BCD_DI 转换指令 BCD 码转换为双整数 BCD_I BCD_I 转换指令 BCD 码转换为整数 BR ---| |--- BIE ---| |--- 状态位指令异常位二进制结果 ----(CALL) ----(CALL) 程序控制指令从线圈调用 FC/SFC（无参
校情分析系统 1系统介绍 校情分析系统主要是针对学生线、教职工线、财物线进行分类分析统计，同时对跨部门、跨类型信息增加综合查询部分，系统从多角度和多主题展示高校校情数据的统计与分析，为高校领导、部门领导和老师提供了解学校综合情况的渠道；采用图表（柱状图、线形图、饼状图等）、报表等形式把各种信息直观的展现在用户面前。 系统主要分五种类型用户：学校领导、行政部门领导、教学部门领导、行政部门老师和教学部门老师。用户根据不同的角色具有不同的权限，看到的信息也不同。 2系统主要功能 2.1学生信息服务 2.1.1招生查询 主要功能有： 1.招生录取分析 以柱状图形式展示每年度招生人数、录取人数（年度按从近到远排列），点击年度信息或年度附近的“详细”可查询： 1)本年度每个专业招生人数、录取人数。 查询条件为学生类别，可选择所有类别。 2.专业招生计划 以线形图形式展示每年度各专业招生人数（年度按从近到远排列），可查询本专业每年度招生人数、录取人数。 查询条件为年度，默认为当前年度。 3.录取学生信息 根据院系、专业、班级、学生类别、年级、考生号、学号、、生源省区、民族、政治面貌等查询条件查询学生详细信息，包括照片。具有导出、打印功能。
2.1.2数字迎新 主要功能有： 1.录取学生信息 除根据院系、专业、班级、年级、学生类别、考生号、学号、、生源省区、民族、政治面貌等查询条件外，还可根据是否报到查询。 2.学生报到分析 以柱状图形式展示各年度的学生报到率，可查询： 1)每个院系学生报到率 2)每个专业学生报到率 3)每种学生类别的报到率 查询条件为学生类别，支持选择所有类别。 3.报到实时统计 可根据时间段、学生类别统计院系学生报到情况，报表容包括：录取情况、报到情况、未报到情况和报到率。具体可参考迎新系统中院系报到统计报表。 4.学生人数统计 以柱状图形式展示各年度学生人数，可查询：生源省区分布，政治面貌分布，民族分布，年龄分布，性别分布，国家分布，学科分布，每个院系学生人数，每个专业学生人数，每个学生类别人数。 查询条件为学生类别，可选择所有类别。 2.1.3学生学籍 主要功能有 1.学生学籍信息 根据院系、专业、班级、学生类别、年级、性别、学号、、生源省区、民族、政治面貌、学生当前状态等查询条件查询，数据围为当前在校的所有学生。可查询并导出学生的照片信息。 2.学生人数分析 以柱状图形式展示各年度在校学生人数，可查询：每个学生类别人数，每年级的学生人数，生源省区分布，政治面貌分布，民族分布，年龄分布，性别分布，国家分布，学科分布，每个院系学生人数，每个专业学生人数。 查询条件为学生类别，可选择所有类别。
侦破两起系列性杀人案件的经验教训 吉林公安高等专科学校学报2002年第3期 侦破两起系列性杀人案件的 吉林省公安厅副厅长史历 1996年以来,在我省通化市,延边州先后发生 的在全国有重大影响的柳河系列杀人残害妇女案, 朝阳——延吉系列抢劫杀人案,均被公安部列为全 国挂牌督办案件.在公安部的正确领导和具体指导 下,经过省,市,县三级公安机关奋力攻坚,两起系 列案件分别于2000年11月,2002年1月成功侦 破.总结两起案件侦破工作,我们可以从中获得许 多有益的启示. 一 ,两起系列杀人案件的简要案情 (一)柳河系列杀人残害妇女案件.1996年2 月1日,通化市柳河县一药厂女工张某在一公厕内 被犯罪分子用锐器刺伤臀部.至1997年4月,在该 县公厕,街道和室内等不同部位又发生10余起针 对青年女性的伤害案件.1997年9月至1999年5 月,故意伤害妇女案件开始升级,在柳河县和与其 接壤的梅河口市,辽宁省新宾县先后发生9起杀人 残害妇女案件,12名青年女性被杀死,3人被杀伤. 多名女青年被杀后,腹部被切开,乳房,阴部被割 走.在公安部的指导和协调下,在辽宁省公安机关 的大力配合下,省公安厅,通化市公安局和柳河县 公安局经过连续3年的侦破工作,于2000年11月 11日,在柳河县将犯罪嫌疑人杨洪军(男,38岁,柳 河县林业局向阳林场工人)抓获.杨洪军交待了故 意伤害及杀人残害妇女作案30佘起的犯罪事实. (二)朝阳川——延吉系列抢劫杀人案件.1998年6 月至2001年12月,延边州龙井市朝阳川镇及毗邻 的延吉市河南,延南,延西等街道连续发生多起杀 人,抢劫大案,手段极其残忍,影响十分恶劣.省公 安厅,延边州公安局和延吉,龙井两市公安机关经 过近3年的艰苦工作,于2002年1月21日,在延 吉市长白乡仁坪村抓获犯罪嫌疑人金春日(男,38 岁,朝鲜族,延吉市依兰乡人,暂住该市长白乡仁坪 村,劳改释放人员).经审查,金春日于1998年以 来,在龙井,延吉两市杀人,抢劫,强奸作案24起, 杀死l4人,杀伤14人,强奸11人,抢劫财物价值
室内装饰材料及施工工艺分析报告 班级:2014级12班 学号:2014207681 姓名:张科成 考察小组成员:张科成、王瑞康、明禹帆、解嘉文 前言: 由于人们长时间半生活活动于室内,因此现代室内设计,或称室内环境设计, 相对地就是环境设计系列中与人们关系最为密切的环节。室内设计的总体,包括艺术风格。随着社会发展的历代的室内设计,总就是具有时代的印记,犹如一部无字的史书。这里由于室内设计从设计构思、施工工艺、装饰材料到内部设施, 必须与社会当时的物质生产水平、社会文化与精神生活状况联系在一起;在室内空间组织、平面布局与装饰处理等方面。文中主要就是针对市场上的装饰材料的种类与市场价格进行调查。 首先就是对一组所选室内装饰效果图之中的各种造型结构所用材料名称,具体施工工艺步骤分析: 该室内设计以现代风格为基调,木地板、沙发、挂灯三者皆就是灰色系,起到很好的呼应效果。墙面以白色肌理效果为主,体现出简洁的现代格调。大量家居就是深棕色木质,与浅色木质,无论就是木制的柜子、储物架,带有木纹的地板,使墙面不至于过于呆板,小面积的小家具,画框的使用使空间通透而具有延展性, 金属茶几, 金属器具的摆
放以及大的落地窗更体现出浓浓的现代气息, 卧室也变得简单而不 简约。整个空间给人清新自然,简约时尚的感觉。 其中,窗户为塑钢窗,塑料窗易变形,强度不够。玻璃窗,保温、隔热,封闭性能好。厨房与客厅的灯采用了茶镜(茶晶或茶色玻璃制成的银镜,又指茶色的烤漆玻璃,其材质非常具现代感,广泛应用于室内外装修。在客厅与厨房的接壤处墙面用了少量大理石材质,该材质质地坚硬、耐磨、耐高温,有一定的吸水性,装饰效过极佳,表面易清洗。表面的花纹更就是添加了几分色彩,十分时尚!客厅的化纤地毯(耐磨性能好,并且富有弹性,价格较低,适用于一般建筑物的地面装修整体在大的空间里,设计师利用木纹地板营造清新氛围,带给人亲切感。同时利用窗帘的变化,以及纹理密集的沙发等等来增加空间的趣味性,很好的解决了大空间带给人的距离感。灯与规则的沙发、地毯、柜子、也起到了对比作用,使整个空间设计灵动而富有情趣 接下来就是对分析的几个材料进行市场考察材料, 市场能买到的品牌名称及价格,及优缺点: 一、木地板 1、实木地板就是木材经烘干、加工而成,具有花纹自然,脚感舒适,使用安全的特点,就是卧室、客厅、书房等地面装饰的理想材料。实木的装饰风格返璞归真,质感自然,在森林覆盖率下降、大力提倡环保的今天,实木地板则更显珍贵。 2、实木复合地板分三层实木复合地板、以胶合板为基材的实木复合地板等。三层实木复合地板由表层板、软质实木芯板、与旋切
各种软件开发系统架构图案例介绍
第一章【荐】共享平台架构图与详细说明 1.1.【荐】共享平台逻辑架构设计 (逻辑指的是业务逻辑) 注:逻辑架构图--主要突出子系统/模块间的业务关系, 这里的逻辑指的是业务逻辑如上图所示为本次共享资源平台逻辑架构图，上图整体展现说明包括以下几个方面： 1 应用系统建设 本次项目的一项重点就是实现原有应用系统的全面升级以及新的应用系统的开发，从而建立行业的全面的应用系统架构群。整体应用系统通过SOA面向服务管理架构模式实现应用组件的有效整合，完成应用系统的统一化管理与维护。 2 应用资源采集 整体应用系统资源统一分为两类，具体包括结构化资源和非机构化资源。本次项目就要实现对这两类资源的有效采集和管理。对于非结构化资源，我们将通过相应的资源采集工具完成数据的统一管理与
维护。对于结构化资源，我们将通过全面的接口管理体系进行相应资源采集模板的搭建，采集后的数据经过有效的资源审核和分析处理后进入到数据交换平台进行有效管理。 3 数据分析与展现 采集完成的数据将通过有效的资源分析管理机制实现资源的有效管理与展现，具体包括了对资源的查询、分析、统计、汇总、报表、预测、决策等功能模块的搭建。 4 数据的应用 最终数据将通过内外网门户对外进行发布，相关人员包括局内各个部门人员、区各委办局、用人单位以及广大公众将可以通过不同的权限登录不同门户进行相关资源的查询，从而有效提升了我局整体应用服务质量。 综上，我们对本次项目整体逻辑架构进行了有效的构建，下面我们将从技术角度对相关架构进行描述。
1.2.【荐】技术架构设计 注:技术架构图 --主要突出子系统/模块自身使用的技术和模块接口关联方式 如上图对本次项目整体技术架构进行了设计，从上图我们可以看出，本次项目整体建设内容应当包含了相关体系架构的搭建、应用功能完善可开发、应用资源全面共享与管理。下面我们将分别进行说明。 1.3.【荐】系统整体架构设计(也称为系统总体架构) 上述两节，我们对共享平台整体逻辑架构以及项目搭建整体技术架构进行了分别的设计说明，通过上述设计，我们对整体项目的架构图进行了归纳如下：
三、信息系统的类型 □信息系统的基本类型 信息系统可以是人工的或基于计算机的，独立的或综合的，成批处理的或联机的。通常的信息系统是上述各种类型的组合。当然它不能即是独立的又是综合的。 1.独立的系统是为了满足某个特定的应用领域(如，人事管理)而设计的。独立系统有它自己的文件，这些文件必然带有一定的冗余性。 2.综合的信息系统通过它们使用的数据而被综合在一起。系统利用一个资源共享的数据库来达到综合的目的。例如，工资系统要求正常地从人力资源系统和会计系统中找到数据。 3.以人工系统为基础已经开发出各种各样的计算机信息系统。到目前为止，在进行人工“计算机化”时，仍然缺乏设计经验和(或)缺少信息服务人员与用户之间的交流。也就是说，基于计算机的系统的工作流程直接借鉴了人工系统的工作流程。通常这些系统是独立的，而且把计算机仅仅用作为数据处理机。在设计这些系统时，很少考虑到最终要将它们综合的意图。 4.信息系统也能按成批处理、联机处理或二者组合来分类。在成批处理系统中，将事务和数据分批地处理或产生报表。例如，
银行将大量的支票编码，然后在一天结束时，将所在支票分批、排序并进行处理。又如，为了防止航空公司在塔拉斯一个售票点与在亚特兰大的另一个售票点同时出售从洛杉矶到旧金山的某一航班的最后一张机票，航空公司系统订票必须是联机的，以反映数据库当前的状态。多数联机信息系统也有成批处理的要求。 即使出现了信息资源管理(IRM)系统，而且计算机信息系统的潜力得到了广泛的承认之后，大多数系统仍然是独立的成批处理系统。如今这些系统中多数已经失去了使用价值，而且被重新设计成综合的、联机的系统。通过定义可知，“综合”要求业务领域经理和公司领导密切地合作。信息服务专业人员可以作为顾问，而有关综合信息系统与业务领域的冲突和差异则应该由用户团体来解决。解决这些差异以真正实现综合的环境是信息服务人员向用户经理提出的挑战。 □社会团体的信息系统 在每个社会团体的每个专业领域都能发现数据处理系统或信息系统的潜力。下面我们按社会团体列举出这些实行计算机化的专业或应用领域。对于某种程度在专业上相近的系统多数可以综合在一起(例如，工资，会计和人事)。下面给出的清单只是为了说明可能的应用领域，并不包括所有的应用领域。 1.通用系统：(1)工资 (2)收账 (3)付账 (4)总账 (5)库存管理和控制 (6)人力资源开发 (7)预算 (8)财务分析
为最大限度降低风险，确保业务操作规范，经营依法合规，工商银行江西吉安分行切实加强重点环节的案件防控工作，制止和防范可能引发案件的各种违法违纪行为，为全行业务发展和经营目标的全面实现发挥保障作用。 一是加强重要风险点的防控。重点抓好违规代办业务、办理定期存款业务、票据贴现业务、集体申办信用卡业务、银企对账和自动柜员机管理6个重要风险点的防控工作，加强研究分析，找出风险点防控的关键环节，抓好任务分解、责任落实和检查整改。建立风险点动态评估机制，根据风险点治理情况，动态调整防控重点。关注业务运营改革中柜面业务风险变化情况，及旱发现苗头性问题，提出系统性整改意见。增强科技手段在案防工作中的应用，关注并及时整改信息科技系统可能存在的漏洞，努力从技术层面实现对易发案环节的硬控制。 二是做好对重点机构的督导检查。继续坚持上级行派员参加下级行案防分析会这一行之有效的做法，通过参加重点县支行的案防分析会和直接对案件隐患突出的基层机构开展案防督导检查等方式，努力实现案防工作重心的下移，全面抓好重点机构的案防工作，不断夯实案防基础。 三是强化对特定岗位人员的监管。深刻认识银行工作的特殊性和特定岗位人员涉案的危害性，认真分析案件特点，找准案件易发高发的岗位和业务环节，加大专项治理力度。认真执行关键岗位人员岗位轮换和强制休假等制度，增强轮岗换岗的突然性和随机性，加强对制度落实情况的监督检查，提高制度执行力。加强对特定岗位人员日常行为动态的掌控，通过履职汇报、日常谈话、侧面了解、客户回访以及利用科技手段排查异常资金行为等方式及时准确地掌握他们的行为动态，对发现苗头的问题及时提示，涉嫌违规违纪的严肃处理。 建立“以德为先”的用人机制。我们从事的行业是一个高风险的金融行业，人的因素就显得极其重要，蒙牛集团用人理念是：“有德有才，提拔重要；有德无才，培养使用；有才无德，限制使用；无德无才，坚决不用。”可见，良好的道德是用人的首要前提。综观历年案例，发案岗位大都是金库、会计、信贷员等重要业务岗位。因此，用人要以德为先，否则，如果用人不当，极易埋下案件风险隐患。 建立现身说法制。定期组织全员参观监狱，亲身感受犯人犯罪后的追悔莫及。同时，组织观看案件警示教育片，以血淋淋的案例给广大干部职工视觉以冲击，心灵得以震撼，自觉将审慎经营、合规经营、照章操作、不越雷池半步等，转化成自身血液中的一种基因性、细胞性的东西，时刻绷紧思想道德之弦。 建立一把手谈话制。一把手谈话制是指总行董事长、各部门经理、各支行行长定期与所管干部员工进行谈话。谈话要做好记录、建立程序、形成制度。谈话要涉及方方面面，真正了解被谈对象思想动态，以便上下级相互沟通，促进交流，更好工作。董事长要每季筛选部分员工代表进行一对一谈话，员工代表要覆盖到各个岗位、各个层面，有中层干部，有信贷人员，有临柜人员，同时，各部门经理、各支行行长也要每月对每位员工进行一对一谈话。重点了解他们的工作、学习、家庭情况，对不同性格的员工采取不同的谈话方式，要以关心鼓励为主，鞭策为辅，认真开展此项工作。一把手谈话可以化解职工心理阴影，避免人为道德因素引发案件，起到很好的防控效果，也极大地提高了团队向心力和凝聚力，为企业文化注入新的活力。
如何做好效果图，每个人做图都有自己的一个套路，想法和过程。那么当然想做好图光感，质感，轮廓，冷暖过度，冷暖对比，必须得好（这不废话吗）。总之做好图一定要给自己找到一个套路，下面我就谈谈我的套路，我对图的理解。 一，如何入手 当你拿到一个空间或者刚刚建完模型的时候，你需要做什么？难道你看到有窗户就给个面光，看到有筒灯就给我射灯，看到有地板就从材质库里拖拽一个地板材质覆上就OK了吗？（有人回答：“是啊，就是这样啊，难道不是这样做吗。）那我告诉你，你错了，你第一步就错了。当你拿到一个空间的时候，你应该静下心来去理解这个空间，是什么空间？是什么风格？空间大小？哪个是主要表现的？哪个是次要表现的？哪个是主光？哪个是辅光？当你理解完这些的时候，图最终是什么样，已经就浮现在你脑海里了，而不是盲目去做。 二，布光方式 关于一个空间应该怎样去布光，顾名思义，许多人听了都会说：“哪有灯，就往哪布呗！” 呵呵，我只能说：“行你对”无语中。。。。。。。。。。。。 那么下面我就说一下，我的个人打光方法，我的布光方式向来都不是根据灯的实际灯位走的，而是该亮亮，该暗暗，一盏一盏亮起来，上回说道主次这个词，顾名思义，这个词非常重要，所谓的主次，“主”就是一张图最需要表现的地方，设计最有亮点的地方，是一张图的视觉中心点，“次”就是辅助“主”而出现的地方，也就是到视觉中心点的一个过度。一张图必须有2-3个过度关系。如图1-1 那么怎么才能让最主要的地方跳出来呢， 你可以用几中方式表现出来， 1. 用灯光的亮度去区分。 2. 用灯光的颜色去区分。 3. 用材质的深浅去区分。 4. 用材质的固有属性去区分（所谓的疏密关系） 至于我说的灯光要一盏一盏的亮起来，顾名思义就是主要的地方亮起来了，空间自然就有了一定亮度了。然后在给一些辅光。自然而然空间出来了。 三，冷暖关系 画图画久了的人一定对这个词不陌生吧，一做图就涉及到冷暖关系，想必你也一定对这个词有了深刻的认识了吧。但是对于初学者这个词可是不那么容易理解的。一说到冷暖关系。那些初学者肯定会说：“不就是窗外是冷光室内是暖光吗：” 我回答：“是啊，对啊，说的很正确：”但是你真正的理解吗，难道真的是像你说的那么简单吗？我来回答恰恰不是，冷暖关系是效果图中最不好掌握的，它涉及到一张图的角度，空间大小，窗户大小，材质属性，等一系列问题，
一般来说分以下几大类应用系统： 系统管理平台(SMS) 临床信息系统(CIS) 病人管理系统(PAS) 临床工作站系统(CWS) 管理信息系统(MIS) 决策支持系统(DSS) 知识管理系统(KMS) 公共应用服务(CAS) 协作交互支持服务(TES) 也有医院按各应用系统模块分法，常见的有： HIS (Hospital Information System) 医院信息系统 CIS (Clinical Information System) 临床信息系统 LIS (Laboratory Information System)实验室（检验科）信息系统 PACS (Picture Archiving and Communication Systems) 影像归档和通信系统RIS (Radiology Information System) 放射科信息管理系统 EMR (Electronic Medical Record) 电子病历 OA (Office Automation) 办公自动化 CRM (Customer Relationship Management)客户关系管理 PEIS (Physical Examination Information System) 体检信息系统 ORIS (Operation Room Information System) 手术室信息系统 CCIS (Critical Care Information System) 重症监护信息系统 WMIS (Wireless Medical Information System) 无线医疗信息系统