按键消抖
一、程序（50mhz）
module
xiaodou(clk,clr,key1,key2,key3,key4,key5,key_out1,key_out2,key_out3,key_out4,key_ out5);
input clk,clr;
input key1,key2,key3,key4,key5;
output key_out1,key_out2,key_out3,key_out4,key_out5;
//-------------------------------------------------
reg [4:0] key_rst;
reg [4:0] key_rst_n;
reg [19:0] cnt;
reg [4:0] key_next;
reg [4:0] key_next_n;
reg d1,d2,d3,d4,d5;
wire[4:0] key_flag;
wire [4:0] key_out_n;
reg [23:0] count1;
reg count_flag;
always @(posedge clk or negedge clr) //get the fist value
begin
if(!clr)
begin key_rst<=5'b11111;
end
else
begin key_rst<={key5,key4,key3,key2,key1};
end
end
//---------------------------------------
always @(posedge clk or negedge clr) begin
if(!clr)
begin key_rst_n<=5'b11111;
end
else
begin key_rst_n<=key_rst;
end
end
//---------------------------------------- assign key_flag=key_rst_n&(~key_rst); //--------------jishu------------------- always @(posedge clk or negedge clr) begin
if(!clr)
begin cnt<=20'd0;
end
else if(key_flag)
begin cnt<=20'b0;
end
else
begin cnt<=cnt+1'b1;
end
end
//-----------------20ms after ------------- always @(posedge clk or negedge clr) begin
if(!clr)
begin key_next<=5'b11111;
end
else if(cnt==20'hfffff)
begin
key_next<={key5,key4,key3,key2,key1};
end
end
//----------------------------------
always @(posedge clk or negedge clr)
begin
if(!clr)
begin key_next_n<=5'b11111;
end
else
begin key_next_n<=key_next;
end
end
//-------------------------------------------
assign key_out_n=key_next_n&(~key_next);
//--------------------------------------
always @(posedge clk or negedge clr)
begin
if(!clr)
begin d1<=1'b1;
d2<=1'b1;
d3<=1'b1;
d4<=1'b1;
d5<=1'b1;
count_flag<=1;
end
else //应led止显示一个时钟周期，我们观测不到，
begin //此处有个计数延时，目的是led灯显示能够持续一段时间if(key_out_n[0])
begin d1<=1'b0;count_flag<=1'b0;end
else
if(count1==24'hffffff)
begin d1<=1'b1;count_flag<=1;end
if(key_out_n[1])
begin d2<=1'b0;count_flag<=1'b0;end
else
if(count1==24'hffffff)
begin d2<=1'b1;count_flag<=1;end
if(key_out_n[2])
begin d3<=1'b0;count_flag<=1'b0;end
else
if(count1==24'hffffff)
begin d3<=1'b1;count_flag<=1;end
if(key_out_n[3])
begin d4<=1'b0;count_flag<=1'b0;end
else
if(count1==24'hffffff)
begin d4<=1'b1;count_flag<=1;end
if(key_out_n[4])
begin d5<=1'b0;count_flag<=1'b0;end
else
if(count1==24'hffffff)
begin d5<=1'b1;count_flag<=1;end
end
end
assign key_out1=d1?1'b1:1'b0;
assign key_out2=d2?1'b1:1'b0;
assign key_out3=d3?1'b1:1'b0;
assign key_out4=d4?1'b1:1'b0;
assign key_out5=d5?1'b1:1'b0;
always @(posedge clk or negedge clr) //计数延时，具体时间没有计算begin
if(!clr)
begin count1<=0;end
else
if(count_flag==1'b0)
begin count1<=count1+1'b1;
end
else
begin
count1<=0;
end
end
endmodule
二、
框图