FPGA嵌入式系统设计专题实践
题目：10位序列检测器设计
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一、 设计题目：10位序列检测器设计
二、 设计目标：
1． 掌握序列检测器的工作原理
2. 利用有限状态机实现一般时序逻辑分析的方法，了解一般状态机的设计与应用。
三、 设计原理：
本系统采用实验箱的48MHz时钟作为输入时钟，将其分频得到计数器计数频率和序列检测器检测序列频率，分析题目要求显示“RIGHT”或者“ERROR”，需要五个数码管，所以设计5进制计数器之后再加一个选通器直接连实验箱上数码管的位选；KEY3为待检测序列输入端，KEY4为清零端，序列检测结果有两个，检测正确为‘1111’，检测错误为‘0000’，送到译码端可译出“RIGHT”或“ERROR”相应的段选码。
四、 设计内容
1、 VHDL描述
(1) 分频器
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all; entity pulse1 is
port(clk: in std_logic;
Fout:out std_logic);
end;
architecture one of pulse1 is
signal full:std_logic;
begin
p_reg:process(clk)
variable cnt8:integer range 48000000 downto 0;
begin
if clk'event and clk='1' then
if cnt8=100 then
cnt8:=0;
full<='1';
else cnt8:=cnt8+1;
full<='0';
end if;
end if;
end process p_reg;
p_div:process (full)
variable cnt2:std_logic;
begin
if full'event and full='1' then
cnt2:=not cnt2;
If cnt2='1'then fout<='1';
else fout<='0';
end if;
end if;
end process p_div;
end;
(2) 序列检测器
LIBRARY IEEE;
USE IEEE.STD_logic_1164.all;
Entity SCHK IS
PORT(DIN,CLK,CLR:IN STD_LOGIC;
AB:OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END; ARCHITECTURE BEHAV OF SCHK IS
SIGNAL Q:INTEGER RANGE 0 TO 10;
SIGNAL D:STD_LOGIC_VECTOR(9 DOWNTO 0);
BEGIN
D<="1111111111";
PROCESS(CLK,CLR)
BEGIN
IF CLR='0' THEN Q<=0;
ELSIF CLK'EVENT AND CLK='1' THEN
CASE Q IS
WHEN 0=>IF DIN=D(9) THEN Q<=1 ;ELSE Q<=0;END IF;
WHEN 1=>IF DIN=D(8) THEN Q<=2 ;ELSE Q<=0;END IF;
WHEN 2=>IF DIN=D(7) THEN Q<=3 ;ELSE Q<=0;END IF;
WHEN 3=>IF DIN=D(6) THEN Q<=4 ;ELSE Q<=0;END IF;
WHEN 4=>IF DIN=D(5) THEN Q<=5 ;ELSE Q<=0;END IF;
WHEN 5=>IF DIN=D(4) THEN Q<=6 ;ELSE Q<=0;END IF;
WHEN 6=>IF DIN=D(3) THEN Q<=7 ;ELSE Q<=0;END IF;
WHEN 7=>IF DIN=D(2) THEN Q<=8 ;ELSE Q<=0;END IF;
WHEN 8=>IF DIN=D(1) THEN Q<=9 ;ELSE Q<=0;END IF;
WHEN 9=>IF DIN=D(0) THEN Q<=10 ;ELSE Q<=0;END IF;
WHEN OTHERS=>Q<=0;
END CASE; END IF; END PROCESS;
PROCESS(Q)
BEGIN
IF Q=10 THEN AB<="1111"; ELSE AB<="0000";END IF;
END PROCESS;
END BEHAV;
(3) 五进制计数器
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity CNT5 is
port( clk:in std_logic;
COUT:OUT std_logic_vector(2 downto 0));
end;
architecture one of CNT5 is
signal CNT:std_logic_vector(2 downto 0); begin
p2:process(clk)
begin
if clk'event and clk='0' then CNT<=CNT+1;
if CNT="100" THEN CNT<="000";
end if;
end if;
COUT<=CNT;
end process p2;
END;
(4) 位选
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity XT is
port( cnt8 :IN std_logic_vector(2 downto 0);
bt:out std_logic_vector(7 downto 0);
a :out integer range 0 to 15);
end;
architecture one of XT is
begin
p1:process (cnt8)
begin
case cnt8 is
when "000"=>bt<="11101111";a<=0;--r
when "001"=>bt<="11110111";a<=1;--i
when "010"=>bt<="11111011";a<=2;--g
when "011"=>bt<="11111101";a<=3;--h
when "100"=>bt<="11111110";a<=4;--t
when others=>null;
end case;
end process p1;
END;
(5) 译码器
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity dec17s is
port( a:in std_logic_vector(3 downto 0);
panduan:in std_logic_vector(3 downto 0);
led7s:out std_logic_vector(6 downto 0));
end;
architecture one of dec17s is
begin
p3:process(a)
begin
if panduan="1111" then--rignt
case a is
when "0000"=>led7s<="0001000";
when "0001"=>led7s<="1111001";
when "0010"=>led7s<="1000010";
when "0011"=>led7s<="0001001";
when "0100"=>led7s<="1111000";
when others=>null;
end case;
elsif panduan="0000" then--error
case a is
when "0000"=>led7s<="0000110";
when "0001"=>led7s<="0001000";
when "0010"=>led7s<="0001000";
when "0011"=>led7s<="1000000";
when "0100"=>led7s<="0001000";
when others=>null;
end case;
end if;
end process p3;
end;
