74VHC138MTCX,74VHC138MX,74VHC138M,74VHC138MTC,规格书,Datasheet 资料

1/12November 2004s HIGH SPEED: t PD = 5.7ns (TYP.) at V CC = 5V sLOW POWER DISSIPATION:I CC = 4 µA (MAX.) at T A =25°C sHIGH NOISE IMMUNITY:V NIH = V NIL = 28% V CC (MIN.)s POWER DOWN PROTECTION ON INPUTS sSYMMETRICAL OUTPUT IMPEDANCE:|I OH | = I OL = 8 mA (MIN)sBALANCED PROPAGATION DELAYS:t PLH ≅ t PHLsOPERATING VOLTAGE RANGE:V CC (OPR) = 2V to 5.5VsPIN AND FUNCTION COMPATIBLE WITH 74 SERIES 138sIMPROVED LATCH-UP IMMUNITYDESCRIPTIONThe 74VHC138 is an advanced high-speed CMOS 3 TO 8 LINE DECODER (INVERTING)fabricated with sub-micron silicon gate and double-layer metal wiring C 2MOS technology.If the device is enabled, 3 binary select (A, B, and C) determine which one of the outputs will go low.If enable input G1 is held low or either G2A or G2B is held high, the decoding function is inhibited and all the 8 outputs go to high.Tree enable inputs are provided to ease cascade connection and application of address decoders for memory systems.Power down protection is provided on all inputs and 0 to 7V can be accepted on inputs with no regard to the supply voltage. This device can be used to interface 5V to 3V.All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.74VHC1383 TO 8 LINE DECODER (INVERTING)Figure 1: Pin Connection And IEC Logic SymbolsTable 1: Order CodesPACKAGE T & R SOP 74VHC138MTR TSSOP74VHC138TTR74VHC1382/12Figure 2: Input Equivalent CircuitTable 2: Pin DescriptionTable 3: Truth TableX : Don’t careFigure 3: Logic DiagramThis logic diagram has not be used to estimate propagation delaysPIN N°SYMBOL NAME AND FUNCTION 1, 2, 3A, B, C Address Inputs 4, 5G2A, G2BEnable Inputs 6G1Enable Input 15, 14, 13, 12, 11, 10, 9,7Y0 to Y7Outputs8GND Ground (0V)16V CCPositive Supply VoltageINPUTSOUTPUTS ENABLE SELECTG2B G2A G1C B A Y0Y1Y2Y3Y4Y5Y6Y7X X L X X X H H H H H H H H X H X X X X H H H H H H H H H X X X X X H H H H H H H H L L H L L L L H H H H H H H L L H L L H H L H H H H H H L L H L H L H H L H H H H H L L H L H H H H H L H H H H L L H H L L H H H H L H H H L L H H L H H H H H H L H H L L H H H L H H H H H H L H LLHHHHHHHHHHHL74VHC1383/12Table 4: Absolute Maximum RatingsAbsolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not impliedTable 5: Recommended Operating Conditions1) V IN from 30% to 70% of V CCSymbol ParameterValue Unit V CC Supply Voltage -0.5 to +7.0V V I DC Input Voltage -0.5 to +7.0V V O DC Output Voltage -0.5 to V CC + 0.5V I IK DC Input Diode Current - 20mA I OK DC Output Diode Current ± 20mA I O DC Output Current ± 25mA I CC or I GND DC V CC or Ground Current± 75mA T stg Storage Temperature -65 to +150°C T LLead Temperature (10 sec)300°CSymbol ParameterValue Unit V CC Supply Voltage 2 to 5.5V V I Input Voltage 0 to 5.5V V O Output Voltage 0 to V CC V T op Operating Temperature-55 to 125°C dt/dvInput Rise and Fall Time (note 1) (V CC = 3.3 ± 0.3V) (V CC = 5.0 ± 0.5V)0 to 1000 to 20ns/V74VHC1384/12Table 6: DC SpecificationsTable 7: AC Electrical Characteristics (Input t r = t f = 3ns)(*) Voltage range is 3.3V ± 0.3V (**) Voltage range is 5.0V ± 0.5VSymbolParameterTest ConditionValue UnitV CC (V)T A = 25°C -40 to 85°C -55 to 125°C Min.Typ.Max.Min.Max.Min.Max.V IHHigh Level Input Voltage2.0 1.5 1.5 1.5V3.0 to 5.50.7V CC0.7V CC0.7V CCV ILLow Level Input Voltage2.00.50.50.5V3.0 to 5.50.3V CC0.3V CC0.3V CCV OHHigh Level Output Voltage2.0I O =-50 µA 1.9 2.0 1.9 1.9V3.0I O =-50 µA 2.9 3.0 2.9 2.94.5I O =-50 µA 4.4 4.54.4 4.43.0I O =-4 mA 2.58 2.48 2.44.5I O =-8 mA 3.943.83.7V OLLow Level Output Voltage2.0I O =50 µA 0.00.10.10.1V3.0I O =50 µA 0.00.10.10.14.5I O =50 µA 0.00.10.10.13.0I O =4 mA 0.360.440.554.5I O =8 mA 0.360.440.55I I Input Leakage Current0 to 5.5V I = 5.5V or GND ± 0.1± 1± 1µA I CCQuiescent Supply Current5.5V I = V CC or GND44040µA SymbolParameterTest ConditionValue UnitV CC (V)C L (pF)T A = 25°C -40 to 85°C -55 to 125°C Min.Typ.Max.Min.Max.Min.Max.t PLH t PHLPropagation Delay Time A, B, C, to Y3.3(*)158.211.4 1.013.0 1.013.0ns 3.3(*)5010.015.8 1.018.0 1.018.05.0(**)15 5.78.1 1.09.5 1.09.55.0(**)507.210.1 1.011.5 1.011.5t PLH t PHLPropagation Delay TimeG to Y3.3(*)158.112.8 1.015.0 1.015.0ns 3.3(*)5010.616.3 1.018.5 1.018.55.0(**)15 5.68.1 1.09.5 1.09.55.0(**)507.110.1 1.011.5 1.011.5t PLH t PHLPropagation Delay TimeG2A, G2B to Y3.3(*)158.211.4 1.013.5 1.013.5ns 3.3(*)5010.714.9 1.017.0 1.017.05.0(**)15 5.88.1 1.09.5 1.09.55.0(**)507.310.11.011.51.011.574VHC1385/12Table 8: Capacitive Characteristics1) C PD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I CC(opr) = C PD x V CC x f IN + I CCFigure 4: Test CircuitC L =15/50pF or equivalent (includes jig and probe capacitance)R T = Z OUT of pulse generator (typically 50Ω)Figure 5: Waveform - Propagation Delays For Inverting Outputs (f=1MHz; 50% duty cycle)SymbolParameterTest ConditionValue UnitT A = 25°C -40 to 85°C -55 to 125°C Min.Typ.Max.Min.Max.Min.Max.C IN Input Capacitance 6101010pF C PDPower Dissipation Capacitance (note 1)34pF74VHC138Figure 6: Waveform - Propagation Delays For Non-inverting Outputs (f=1MHz; 50% duty cycle)6/1274VHC1387/12DIM.mm.inch MIN.TYPMAX.MIN.TYP.MAX.A 1.750.068a10.10.250.0040.010a2 1.640.063b 0.350.460.0130.018b10.190.250.0070.010C 0.50.019c145° (typ.)D 9.8100.3850.393E 5.86.20.2280.244e 1.270.050e38.890.350F 3.8 4.00.1490.157G 4.6 5.30.1810.208L 0.5 1.270.0190.050M 0.620.024S8° (max.)SO-16 MECHANICAL DATA0016020D74VHC1388/12DIM.mm.inchMIN.TYPMAX.MIN.TYP.MAX.A 1.20.047A10.050.150.0020.0040.006A20.81 1.050.0310.0390.041b 0.190.300.0070.012c 0.090.200.0040.0079D 4.95 5.10.1930.1970.201E 6.2 6.4 6.60.2440.2520.260E1 4.34.4 4.480.1690.1730.176e 0.65 BSC0.0256 BSCK 0˚8˚0˚8˚L0.450.600.750.0180.0240.030TSSOP16 MECHANICAL DATAcEbA2A E1D1PIN 1 IDENTIFICATIONA1LKe0080338D74VHC138 Tape & Reel SO-16 MECHANICAL DATAmm.inchDIM.MIN.TYP MAX.MIN.TYP.MAX.A33012.992C12.813.20.5040.519D20.20.795N60 2.362T22.40.882Ao 6.45 6.650.2540.262Bo10.310.50.4060.414Ko 2.1 2.30.0820.090Po 3.9 4.10.1530.161P7.98.10.3110.3199/1274VHC138Tape & Reel TSSOP16 MECHANICAL DATAmm.inch DIM.MIN.TYP MAX.MIN.TYP.MAX.A33012.992 C12.813.20.5040.519 D20.20.795N60 2.362T22.40.882 Ao 6.7 6.90.2640.272 Bo 5.3 5.50.2090.217 Ko 1.6 1.80.0630.071 Po 3.9 4.10.1530.161 P7.98.10.3110.31910/1274VHC138 Table 9: Revision HistoryDate Revision Description of Changes 12-Nov-20044Order Codes Revision - pag. 1.11/1274VHC138Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.The ST logo is a registered trademark of STMicroelectronicsAll other names are the property of their respective owners© 2004 STMicroelectronics - All Rights ReservedSTMicroelectronics group of companiesAustralia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America12/12。

74HC138_3-8译码器,输出低电平有效DataSheetDATA SHEETProduct speci?cationFile under Integrated Circuits, IC06September 1993INTEGRATED CIRCUITS74HC/HCT1383-to-8 line decoder/demultiplexer;invertingFor a complete data sheet, please also download:The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications The IC06 74HC/HCT/HCU/HCMOS Logic Package Information ?The IC06 74HC/HCT/HCU/HCMOS Logic Package OutlinesFEATURESDemultiplexing capabilityMultiple input enable for easy expansion Ideal for memory chip select decoding Active LOW mutually exclusive outputs Output capability: standard ?I CC category: MSI GENERAL DESCRIPTIONThe 74HC/HCT138 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A.The 74HC/HCT138 decoders accept three binaryweighted address inputs (A 0, A 1, A 2) and when enabled,provide 8 mutually exclusive active LOW outputs (Y 0to Y 7).The “138” features three enable inputs: two active LOW (E 1and E 2) and one active HIGH (E 3). Every output will be HIGH unless E 1and E 2are LOW and E 3is HIGH.This multiple enable function allows easy parallelexpansion of the “138” to a 1-of-32 (5 lines to 32 lines)decoder with just four “138” ICs and one inverter.The ”138” can be used as an eight output demultiplexer by using one of the active LOW enable inputs as the data input and the remaining enable inputs as strobes. Unused enable inputs must be permanently tied to their appropriate active HIGH or LOW state.The ”138” is identical to the “238” but has inverting outputs.QUICK REFERENCE DATAGND = 0 V; T amb = 25°C; t r = t f = 6 ns Notes1.C PD is used to determine the dynamic power dissipation (P D in µW):P D = C PD ×V CC 2×f i +∑(C L ×V CC 2×f o )where:f i = input frequency in MHz f o = output frequency in MHz ∑(C L ×V CC 2×f o )= sum of outputs C L =output load capacitance in pF V CC =supply voltage in V2.For HC the condition is V I =GND to V CCFor HCT the condition is V I =GND to V CC ?1.5 V ORDERING INFORMATIONSee “74HC/HCT/HCU/HCMOS Logic Package Information”.SYMBOLPARAMETERpropagation delayC L = 15 pF; V CC = 5 Vt PHL / t PLH A n to Y n 1217ns t PHL / t PLH E 3to Y n E n to Y n1419ns C I input capacitance3.5 3.5pF C PD power dissipation capacitance per packagenotes 1 and 26767pFPIN DESCRIPTION PIN NO.SYMBOL NAME AND FUNCTION 1, 2, 3A 0to A 2address inputs4, 5E 1,E 2enable inputs (active LOW)6E 3enable input (active HIGH)8GND ground (0 V)15, 14, 13, 12, 11, 10, 9, 7Y 0 to Y 7outputs (active LOW)16V CCpositive supply voltageFig.1 Pin configuration.Fig.2 Logic symbol.handbook, halfpageMLB312A 0A 1A 212315131179101214Y 0Y 1Y 2Y 3Y 4Y 5Y 6Y 7456E 1E 2E 3Fig.3 IEC logic symbol.(a)(b)Fig.4 Functional diagram.FUNCTION TABLENotes1.H =HIGH voltage levelL =LOW voltage level X =don’t careINPUTSOUTPUTS E 1E 2E 3A 0A 1A 2Y 0Y 1Y 2Y 3Y 4Y 5Y 6Y 7H X X X H X X X L X X X X X X X X X H H H H H H H H H H H H H H H H H H H H H H H H L L L L L L L L H H H H L H L H L L H H L L L L L H H H H L H H H H L H H H H L H H H H H H HL L H HH H H HH H H HH H H HH H H HH H H HL H H HH L H HH H L HH H H LFig.5 Logic diagram.DC CHARACTERISTICS FOR 74HCFor the DC characteristics see“74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: standard I CC category: MSIAC CHARACTERISTICS FOR 74HCGND = 0 V; t r= t f= 6 ns; C L= 50 pFSYMBOL PARAMETERT amb(°C)UNITTEST CONDITIONS74HCV CC(V)WAVEFORMS +25?40to+85?40to+125min.typ.max.min.max.min.max.t PHL/ t PLH propagation delayA n to Y n411512150304538ns2.04.56.0Fig.6t PHL/ t PLH propagation delay E3to Y n471714150302619038332254538ns2.04.56.0Fig.6t PHL/ t PLH propagation delay E n to Y n471738332254538ns2.04.56.0Fig.7t THL/ t TLH output transitiontime19767515139519161102219ns2.04.56.0Figs 6 and 7DC CHARACTERISTICS FOR 74HCTI CC per input, multiply this value by the unit load coefficient shown in the table below.AC CHARACTERISTICS FOR 74HCT GND = 0 V; t r = t f = 6 ns; C L = 50 pFINPUT UNIT LOAD COEFFICIENT A n 1.50E n 1.25E 31.00SYMBOL PARAMETERT amb (°C)UNITTEST CONDITIONS 74HCTV CC (V)WAVEFORMS +25?40to +85?40to +125min.typ.max.min.max.min.max.t PHL / t PLH propagation delay A n to Y n20354453ns 4.5Fig.6t PHL / t PLH propagation delay E 3to Y n18405060ns 4.5Fig.6t PHL / t PLH propagation delay E n to Y n19405060ns 4.5Fig.7t THL / t TLHoutput transition time7151922ns4.5Figs 6 and 7AC WAVEFORMS(1)HC: V M= 50%; V I= GND to V CC.HCT:V M= 1.3 V; V I=GND to 3 V.Fig.6Waveforms showing the address input (A n)and enable input (E3) to output (Y n) propagation delays and the output transition times.(1)HC: V M= 50%; V I= GND to V CC.HCT:V M= 1.3 V; V I=GND to 3 V.Fig.7Waveforms showing the enable input (E n) to output (Y n)propagation delays and the output transition times. PACKAGE OUTLINESSee“74HC/HCT/HCU/HCMOS Logic Package Outlines”.。

红色标记为实验室有的芯片74系列芯片的型号区别与功能略表2010-05-31 16:3974HC/LS/HCT/F系列芯片的区别：1、 LS是低功耗肖特基，HC 是高速COMS。

LS的速度比HC略快。

HCT输入输出与LS兼容，但是功耗低；F是高速肖特基电路；2、 LS是TTL电平，HC是COMS 电平。

3、 LS输入开路为高电平，HC输入不允许开路， hc 一般都要求有上下拉电阻来确定输入端无效时的电平。

LS 却没有这个要求4、 LS输出下拉强上拉弱，HC上拉下拉相同。

5、工作电压不同，LS只能用5V，而HC一般为2V到6V；而HCT的工作电压一般为4.5V～5.5V。

6、电平不同。

LS是TTL电平，其低电平和高电平分别为0.8和V2.4，而CMOS在工作电压为5V时分别为0.3V和3.6V，所以CMOS可以驱动TTL，但反过来是不行的7、驱动能力不同，LS一般高电平的驱动能力为5mA，低电平为20mA；而CMOS的高低电平均为5mA；8、 CMOS器件抗静电能力差，易发生栓锁问题，所以CMOS的输入脚不能直接接电源。

74系列集成电路大致可分为6大类：.74××（标准型）；.74LS××（低功耗肖特基）；.74S××（肖特基）；.74ALS××（先进低功耗肖特基）；.74AS××（先进肖特基）；.74F××（高速）。

近年来还出现了高速CMOS电路的74系列，该系列可分为3大类：.HC为COMS工作电平；.HCT为TTL工作电平，可与74LS系列互换使用；.HCU适用于无缓冲级的CMOS电路。

这9种74系列产品，只要后边的标号相同，其逻辑功能和管脚排列就相同。

根据不同的条件和要求可选择不同类型的74系列产品，比如电路的供电电压为3V就应选择74HC 系列的产品系列电平典型传输延迟ns 最大驱动电流(-Ioh/Lol)mAAHC CMOS 8.5 -8/8AHCT COMS/TTL 8.5 -8/8HC COMS 25 -8/8HCT COMS/TTL 25 -8/8ACT COMS/TTL 10 -24/24F TTL 6.5 -15/64ALS TTL 10 -15/64LS TTL 18 -15/24注：同型号的74系列、74HC系列、74LS系列芯片，逻辑功能上是一样的。

74VHC14Hex Schmitt InverterGeneral DescriptionThe VHC14 is an advanced high speed CMOS Hex Schmitt Inverter fabricated with silicon gate CMOS technol-ogy. It achieves the high speed operation similar to equiva-lent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. Pin configuration and function are the same as the VHC04 but the inputs have hysteresis between the positive-going and negative-going input thresholds, which are capable of transforming slowly changing input signals into sharply defined, jitter-free out-put signals, thus providing greater noise margin than con-ventional inverters.An input protection circuit ensures that 0V to 7V can be applied to the input pins without regard to the supply volt-age. This device can be used to interface 5V to 3V systems and two supply systems such as battery back up. This cir-cuit prevents device destruction due to mismatched supply and input voltages.Features■High Speed: t PD= 5.5 ns (typ) at V CC= 5V■Low power dissipation: I CC= 2 μA (Max) at T A= 25°C ■High noise immunity: V NIH= V NIL= 28% V CC (Min)■Power down protection is provided on all inputs■Low noise: V OLP= 0.8V (Max)■Pin and function compatible with 74HC14Ordering Code:Order Number PackageNumberPackage Description74VHC14M(Note 1)M14A14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow74VHC14MX_NL (Note 2)M14A Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150"Narrow74VHC14SJ(Note 1)M14D Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide74VHC14MTC(Note 1)MTC1414-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide74VHC14MTC_NL (Note 3)MTC14Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,4.4mm Wide74VHC14MTCX_NL (Note 2)MTC14Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,4.4mm Wide74VHC14N(Obsolete)N14A14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" WidePb-Free package per JEDEC J-STD-020B.Note 1: Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.Note 2: “_NL” indicates Pb-Free product (per JEDEC J-STD-020B). Device is available in Tape and Reel only.Note 3: “_NL” indicates Pb-Free product (per JEDEC J-STD-020B).© 2010 Fairchild Semiconductor Corporation Logic Symbol/sIEEE/IECPin DescriptionsPin Names DescriptionA n InputsO n OutputsConnection Diagram/sTruth Table/sA OL HH L2Absolute Maximum Ratings(Note 4)Supply Voltage (V CC)−0.5V to +7.0V DC Input Voltage (V IN)−0.5V to +7.0V DC Output Voltage (V OUT)−0.5V to V CC+ 0.5V Input Diode Current (I IK)−20 mA Output Diode Current (I OK)±20 mA DC Output Current (I OUT)±25 mA DC V CC/GND Current (I CC)±50 mA Storage Temperature (T STG)−65°C to +150°C Lead Temperature (T L)Soldering (10 seconds)260°C Recommended Operating Conditions (Note 5)Supply Voltage (V CC)+2.0V to +5.5V Input Voltage (V IN)0V to +5.5V Output Voltage (V OUT)0V to V CC Operating Temperature (T OPR)−40°C to +85°C Note 4: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. The data book specifica-tions should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading vari-ables. Fairchild does not recommend operation outside databook specifica-tions.Note 5: Unused inputs must be held HIGH or LOW. They may not float.DC Electrical CharacteristicsSymbol Parameter V CCT A= 25°C T A=−40°C to +85°CUnits Conditions Min Typ Max Min MaxV P Positive Threshold Voltage 3.0 2.20 2.204.5 3.15 3.15V5.5 3.85 3.85V N Negative Threshold Voltage 3.00.900.904.5 1.35 1.35V5.5 1.65 1.65V H Hysteresis Voltage 3.00.30 1.200.30 1.204.50.40 1.400.40 1.40V5.50.50 1.600.50 1.60V OH HIGH Level Output Voltage 2.0 1.9 2.0 1.9V IN=V IL3.0 2.9 3.0 2.9V I OH=−50 μA4.5 4.4 4.5 4.43.0 2.58 2.48V I OH=−4 mA4.5 3.94 3.80I OH=−8 mA V OL LOW Level Output Voltage 2.00.00.10.1V IN= V IH3.00.00.10.1V I OL= 50 μA4.50.00.10.13.00.360.44V I OL= 4 mA4.50.360.44I OL= 8 mAI IN Input Leakage Current0–5.5±0.1±1.0μA V IN= 5.5V or GNDI CC Quiescent Supply Current 5.5 2.020.0μA V IN= V CC or GND Noise CharacteristicsSymbol Parameter V CCT A= 25°CUnits Conditions Typ LimitsV OLP (Note 6)Quiet Output Maximum Dynamic V OL5.00.40.8VC L= 50 pFV OLV (Note 6)Quiet Output Minimum Dynamic V OL5.0−0.4−0.8VC L= 50 pFV IHD (Note 6)Minimum HIGH Level Dynamic Input Voltage5.0 3.5VC L= 50 pFV ILD (Note 6)Maximum LOW Level Dynamic Input Voltage5.0 1.5VC L= 50 pFNote 6: Parameter guaranteed by design.AC Electrical CharacteristicsSymbol Parameter V CCT A= 25°C T A=−40°C to +85°CUnits Conditions Min Typ Max Min Maxt PLH Propagation Delay 3.3 ± 0.38.312.8 1.015.0ns C L= 15 pFt PHL Time10.816.3 1.018.5C L= 50 pF5.0 ± 0.5 5.58.6 1.010.0ns C L= 15 pF7.010.6 1.012.0C L= 50 pFC IN Input Capacitance41010pF V CC= OpenC PD Power Dissipation Capacitance21pF(Note 7)Note 7: C PD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: I CC (Opr) = C PD * V CC * f IN+ I CC/6 (per Gate)468。

74系列集成电路大全74系列集成电路大致可分为6大类：74××（标准型）；74LS××（低功耗肖特基）；74S××（肖特基）；74ALS××（先进低功耗肖特基）；74AS××（先进肖特基）；74F××（高速）。

HC为COMS工作电平；HCT为TTL工作电平，可与74LS系列互换使用；HCU适用于无缓冲级的CMOS电路。

这9种74系列产品，只要后边的标号相同，其逻辑功能和管脚排列就相同。

根据不同的条件和要求可选择不同类型的74系列产品，比如电路的供电电压为3V就应选择74HC系列的产品。

补充:．74 –系列这是早期的产品，现仍在使用，但正逐渐被淘汰。

2．74H –系列这是74 –系列的改进型，属于高速TTL产品。

其“与非门”的平均传输时间达10ns左右，但电路的静态功耗较大，目前该系列产品使用越来越少，逐渐被淘汰。

3．74S –系列这是TTL的高速型肖特基系列。

在该系列中，采用了抗饱和肖特基二极管，速度较高，但品种较少。

4．74LS –系列这是当前TTL类型中的主要产品系列。

品种和生产厂家都非常多。

性能价格比比较高，目前在中小规模电路中应用非常普遍。

5．74ALS –系列这是“先进的低功耗肖特基”系列。

属于74LS –系列的后继产品，速度（典型值为4ns）、功耗（典型值为1mW）等方面都有较大的改进，但价格比较高。

6．74AS –系列这是74S –系列的后继产品，尤其速度（典型值为1.5ns）有显著的提高，又称“先进超高速肖特基”系列。

7．74HC –系列54/74HC –系列是高速CMOS标准逻辑电路系列，具有与74LS –系列同等的工作度和CMOS集成电路固有的低功耗及电源电压范围宽等特点。

74HCxxx是74LSxxx同序号的翻版，型号最后几位数字相同，表示电路的逻辑功能、管脚排列完全兼容，为用74HC替代74LS提供了方便。

November 1992Revised April 199974VHC138 3-to-8 Decoder/Demultiplexer © 1999 Fairchild Semiconductor Corporation DS011537.prf 74VHC1383-to-8 Decoder/DemultiplexerGeneral DescriptionThe VHC138 is an advanced high speed CMOS 3-to-8decoder/demultiplexer fabricated with silicon gate CMOStechnology. It achieves the high speed operation similar toequivalent Bipolar Schottky TTL while maintaining theCMOS low power dissipation.When the device is enabled, 3 binary select inputs (A0, A1and A2) determine which one of the outputs (O0–O7) will goLOW. When enable input E3 is held LOW or either E1 or E2is held HIGH, decoding function is inhibited and all outputsgo HIGH. E3, E1 and E2 inputs are provided to ease cas-cade connection and for use as an address decoder formemory systems. An input protection circuit ensures that0V to 7V can be applied to the input pins without regard tothe supply voltage. This device can be used to interface 5Vto 3V systems and two supply systems such as batteryback up. This circuit prevents device destruction due tomismatched supply and input voltages.Featuress High Speed: t PD= 5.7ns (typ) at T A= 25°Cs Low power dissipation: I CC= 4 µA (max.) at T A= 25°Cs High noise immunity: V NIH= V NIL= 28% V CC (min.)s Power down protection provided on all inputss Pin and function compatible with 74HC138Ordering Code:Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.Logic SymbolsIEEE/IECConnection DiagramPin DescriptionsOrder Number Package Number Package Description74VHC138M M16A16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow74VHC138SJ M16D16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide74VHC138MTC MTC1616-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide74VHC138N N16E16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” WidePin Names DescriptionA0–A2Address InputsE1–E2Enable InputsE3Enable InputO0–O7Outputs 274V H C 138Truth TableH = HIGH Voltage Level L = LOW Voltage Level X = ImmaterialInputsOutputs E 1E 2E 3A 0A 1A 2O 0O 1O 2O 3O 4O 5O 6O 7H X X X X X H H H H H H H H X H X X X X H H H H H H H H XXLXXXHHHHHHHHL L H L L L L H H H H H H H L L H H L L H L H H H H H H L L H L H L H H L H H H H H LLHHHLHHHLHHHHL L H L L H H H H H L H H H L L H H L H H H H H H L H H L L H L H H H H H H H H L H LLHHHHHHHHHHHL74VHC138Absolute Maximum Ratings (Note 1)Recommended Operating Conditions (Note 2)Note 1: Absolute Maximum Ratings are values beyond which the device may be damaged or have its useful life impaired. The databook specifica-tions should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading vari-ables. Fairchild does not recommend operation outside databook specifica-tions.Note 2: Unused inputs must be held HIGH or LOW. They may not float.DC Electrical CharacteristicsSupply Voltage (V CC )−0.5V to +7.0V DC Input Voltage (V IN )−0.5V to +7.0V DC Output Voltage (V OUT )−0.5V to V CC + 0.5VInput Diode Current (I IK )−20 mA Output Diode Current (I OK )±20 mA DC Output Current (I OUT )±25 mA DC V CC /GND Current (I CC )±75 mAStorage Temperature (T STG )−65°C to +150°CLead Temperature (T L )(Soldering, 10 seconds)260°CSupply Voltage (V CC ) 2.0V to +5.5V Input Voltage (V IN )0V to +5.5V Output Voltage (V OUT )0V to V CCOperating Temperature (T OPR )−40°C to +85°CInput Rise and Fall Time (t r , t f )V CC = 3.3V ± 0.3V 0 ∼ 100 ns/V V CC = 5.0V ± 0.5V0 ∼ 20 ns/V Symbol ParameterV CC (V)T A = 25°CT A = −40°C to +85°C Units ConditionsMin TypMaxMin MaxV IH HIGH Level Input Voltage 2.0 1.50 1.50V 3.0 − 5.50.7 V CC0.7 V CCV IL LOW Level Input Voltage 2.00.500.50V3.0 − 5.50.3 V CC0.3 V CC V OHHIGH Level Output Voltage2.0 1.9 2.0 1.9V IN = V IH I OH = −50 µA3.0 2.9 3.0 2.9Vor V IL4.5 4.4 4.5 4.43.0 2.58 2.48VI OH = −4 mA 4.53.943.80I OH = −8 mA V OLLOW Level Output Voltage2.00.00.10.1V IN = VIH IOL= 50 µA3.00.00.10.1V or V IL4.50.00.10.13.00.360.44V I OL = 4 mA4.50.360.44I OL = 8 mAI IN Input Leakage Current 0 − 5.5±0.1±1.0µA V IN = 5.5V or GND I CCQuiescent Supply Current5.54.040.0µAV IN = V CC or GND 474V H C 138AC Electrical CharacteristicsNote 3: C PD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: I CC (opr.) = C PD * V CC * f IN + I CC .Symbol ParameterV CC (V)T A = 25°CT A = −40°C to +85°C Units Conditions MinTyp Max Min Max t PLH Propagation Delay 3.3 ± 0.38.211.4 1.013.5ns C L = 15 pF t PHLA n to O n10.015.8 1.018.0C L = 50 pF 5.0 ± 0.55.78.1 1.09.5ns C L = 15 pF 7.210.1 1.011.5C L = 50 pF t PLH Propagation Delay 3.3 ± 0.38.112.8 1.015.0ns C L = 15 pF t PHLE 3 to O n10.616.3 1.018.5C L = 50 pF 5.0 ± 0.55.68.1 1.09.5ns C L = 15 pF 7.110.1 1.011.5C L = 50 pF t PLH Propagation Delay 3.3 ± 0.38.211.4 1.013.5ns C L = 15 pF t PHLE 1 or E 2 to O n10.714.9 1.017.0C L = 50 pF 5.0 ± 0.55.88.1 1.09.5ns C L = 15 pF 7.310.1 1.011.5C L = 50 pF C IN Input Capacitance 41010pF V CC = Open C PDPower Dissipation 34pF(Note 3)Capacitance74VHC138Physical Dimensions inches (millimeters) unless otherwise noted16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” NarrowPackage Number M16A16-Lead Small Outline Package (SOP) EIAJ TYPE II, 5.3mm WidePackage Number M16D 674V H C 138Physical Dimensionsinches (millimeters) unless otherwise noted (Continued)16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm WidePackage Number MTC16Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.74VHC138 3-to-8 Decoder/DemultiplexerLIFE SUPPORT POLICYFAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:1.Life support devices or systems are devices or systemswhich, (a) are intended for surgical implant into thebody, or (b) support or sustain life, and (c) whose failureto perform when properly used in accordance withinstructions for use provided in the labeling, can be rea-sonably expected to result in a significant injury to the user.2. A critical component in any component of a life support device or system whose failure to perform can be rea-sonably expected to cause the failure of the life support device or system, or to affect its safety or Physical Dimensions inches (millimeters) unless otherwise noted (Continued)16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” WidePackage Number N16E。

74HC00 四 2 输入与非门国际通用符号54/7400 ， 54/74H00 , 54L 00 ， 54/74S00 ， 54/74LS00 , 54/74ALS00 ， 54/ 74F 00 , 54/74HC00 , 54/ 74AC 00 ， 54/74HCT00 ， 54/74ACT00 ， 54/74AHC00 ， 54/74AHCT00 ，74LV00 , 74LVC00。

74HC02 四 2 输入或非门国际通用符号54/7402 ， 54L 02 , 54/74S02 , 54/74LS02 , 54/74AS02 ， 54/74ALS02 ， 54/ 74F 02 ，54/74HC02 ， 74AC 02 ， 54/74HCT02 ， 54/74ACT02 ， 54/74AHC02 ， 54/AHCT02 ， 74LV02 , 74LVC02。

74HC04 六反相器国际通用符号54/7404 ， 54L 04 ， 54/74H04 ， 54/74S04 ， 54/74LS04 ， 54/74AS04 ， 54/74ALS04 ，54/ 74F 04 ， 54/74HCU04 ， 54/74HC04 ， 54/ 74AC 04 ， 54/74HCT04 , 54/74ACT04 ，54/74AHC04 ， 54/74AHCT04 ， 74LV04 ， 74LVC04 , 54/74AHCU04 ， 74LVU04 ， 74LVCU04 .74HC08 四 2 输入与门国际通用符号54/7408 ， 54/74S08 ， 54/74LS08 ， 54/74AS08 ， 54/74ALS08 ， 54/ 74F 08 ， 54/74HC08 ，54/74HCT08 ， 54/ 74AC 08 ， 54/74ACT08 ， 54/74AHC08 ， 54/74AHCT08 , 74LV08 ， 74LVC08。

74HC138中文资料引脚布局概述138是一款高速CMOS器件，74HC138引脚兼容低功耗肖特基TTL（LSTTL）系列。

138译码器可接受3位二进制加权地址输入（A0,A1和A3），并当使能时，提供8个互斥的低有效输出（Y0至Y7）。

74HC138特有3个使能输入端：两个低有效（E1和E2）有效（E3）。

除非E1和E2置低且E3置高，否则74HC138将保持所有输出为高。

利用这种复合使能特性，仅需4片74HC138芯片和1个反相器，即可轻松实现并行扩展，组个1-32（5线到32线）译码器。

任选一个低有效使能输入端作为数据输入，而把其余的使能输入端作为选通端，则74HC138亦可充当一个8输出多路分配器，未使用的使能输入持绑定在各自合适的高有效或低有效状态。

138与74HC238逻辑功能一致，只不过74HC138为反相输出。

74HC138参数74HC138基本参数电压 2.0～6.0V驱动电流+/-5.2mA传输延迟12ns@5V74HC138其他特性逻辑电平CMOS功耗考量低功耗或电池74HC138封装与引脚SO16,SSOP16,DIP16,TSSO特性多路分配功能复合使能输入，轻松实现扩展兼容JEDEC标准no.7A存储器芯片译码选择的理想选择低有效互斥输出SD保护o HBM EIA/JESD22-A114-C超过2000V o MM EIA/JESD22-A115-A超过200V 温度范围o-40～+85℃o-40～+125℃引脚布局概述74HC165是一款高速CMOS器件，74HC165遵循JEDEC标准no.7A。

74HC165引脚兼容低功耗肖特基TTL（LSTTL）系列。

74HC165参数74HC165基本参数电压 2.0～6.0V74HC165是8位并行读取或串行输入移位寄存器，可在末级得到互斥的串行输出（Q7和Q7），当并行读取（PL）输入为低时，7口输入的并行数据将被异步地读取进寄存器内。