半导体制造技术(1)

半导体⼯艺讲解半导体⼯艺讲解(1)--掩模和光刻（上）概述光刻⼯艺是半导体制造中最为重要的⼯艺步骤之⼀。

主要作⽤是将掩膜板上的图形复制到硅⽚上，为下⼀步进⾏刻蚀或者离⼦注⼊⼯序做好准备。

光刻的成本约为整个硅⽚制造⼯艺的1/3，耗费时间约占整个硅⽚⼯艺的40～60%。

光刻机是⽣产线上最贵的机台，5～15百万美元/台。

主要是贵在成像系统（由15～20个直径为200～300mm的透镜组成）和定位系统（定位精度⼩于10nm）。

其折旧速度⾮常快，⼤约3～9万⼈民币/天，所以也称之为印钞机。

光刻部分的主要机台包括两部分：轨道机（Tracker），⽤于涂胶显影；扫描曝光机（Scanning )光刻⼯艺的要求：光刻⼯具具有⾼的分辨率；光刻胶具有⾼的光学敏感性；准确地对准；⼤尺⼨硅⽚的制造；低的缺陷密度。

光刻⼯艺过程⼀般的光刻⼯艺要经历硅⽚表⾯清洗烘⼲、涂底、旋涂光刻胶、软烘、对准曝光、后烘、显影、硬烘、刻蚀、检测等⼯序。

1、硅⽚清洗烘⼲（Cleaning and Pre-Baking）⽅法：湿法清洗＋去离⼦⽔冲洗＋脱⽔烘焙（热板150～2500C,1～2分钟，氮⽓保护）⽬的：a、除去表⾯的污染物（颗粒、有机物、⼯艺残余、可动离⼦）；b、除去⽔蒸⽓，是基底表⾯由亲⽔性变为憎⽔性，增强表⾯的黏附性（对光刻胶或者是HMDS-〉六甲基⼆硅胺烷）。

2、涂底（Priming)⽅法：a、⽓相成底膜的热板涂底。

HMDS蒸⽓淀积，200～2500C,30秒钟；优点：涂底均匀、避免颗粒污染； b、旋转涂底。

缺点：颗粒污染、涂底不均匀、HMDS⽤量⼤。

⽬的：使表⾯具有疏⽔性，增强基底表⾯与光刻胶的黏附性。

3、旋转涂胶（Spin-on PR Coating）⽅法：a、静态涂胶（Static）。

硅⽚静⽌时，滴胶、加速旋转、甩胶、挥发溶剂（原光刻胶的溶剂约占65～85%,旋涂后约占10～20%）；b、动态（Dynamic）。

低速旋转（500rpm_rotation per minute）、滴胶、加速旋转（3000rpm）、甩胶、挥发溶剂。

第一章测试1.“摩尔定律”是（）提出的？A:1965年B:1958年C:1960D:1970年答案:A2.第一个晶体管是（）材料晶体管？A:锗B:硅C:碳答案:A3.戈登摩尔是（）科学家。

A:德国B:美国C:法国D:英国答案:B4.第一个集成电路在（）被研制。

A:1960B:1955C:1965D:1958答案:D5.（）被称为中国“芯片之父”。

1、A:邓中翰B:许居衍C:沈绪榜D:吴德馨答案:A第二章测试1.硅在地壳中的储量为（）。

A:第四B:第二C:第三D:第一答案:B2.脱氧后的沙子主要以（）的形式。

A:碳化硅B:硅C:二氧化硅答案:C3.半导体级硅的纯度（）。

A:99.99999％B:99.999999％C:99.999％D:99.9999999％答案:D4.西门子工艺制备得到的硅为单晶硅。

（）A:对B:错答案:B5.一片硅片只有一个定位边。

（）A:错B:对答案:A6.晶面指数（m1 m2 m3）： m1 、m2 、m3分别为晶面在X、Y、Z轴上截距的倒数。

（）A:错B:对答案:B第三章测试1.通过薄膜淀积方法生长薄膜不消耗衬底的材料。

（）A:对B:错答案:A2.热氧化法在硅衬底上制备二氧化硅需要消耗硅衬底。

（）A:错B:对答案:B3.二氧化硅可以与氢氟酸发生反应。

（）A:错B:对答案:B4.薄膜的密度越大，表明致密性越低。

（）A:对B:错答案:B5.电阻率，表征导电能力的参数，同一种物质的电阻率在任何情况下都是不变的。

（）A:错B:对答案:A第四章测试1.光刻本质上是光刻胶的光化学反应。

（）A:错B:对答案:B2.一个透镜的数值孔径越大就能把更少的衍射光会聚到一点。

（）A:错B:对答案:A3.使用正胶进行光刻时，晶片上所得到的图形与掩膜版图形相同。

（）A:错B:对答案:B4.使用负胶进行光刻时，晶片上得到的图形与掩膜版上的图形相反。

（）A:对B:错答案:A5.正性光刻胶经过曝光后，可以溶解于显影液。

Semiconductor Manufacturing Technology半导体制造技术Instructor’s ManualMichael QuirkJulian SerdaCopyright Prentice HallTable of Contents目录OverviewI. Chapter1. Semiconductor industry overview2. Semiconductor materials3. Device technologies—IC families4. Silicon and wafer preparation5. Chemicals in the industry6. Contamination control7. Process metrology8. Process gas controls9. IC fabrication overview10. Oxidation11. Deposition12. Metallization13. Photoresist14. Exposure15. Develop16. Etch17. Ion implant18. Polish19. Test20. Assembly and packagingII. Answers to End-of-Chapter Review QuestionsIII. Test Bank (supplied on diskette)IV. Chapter illustrations, tables, bulleted lists and major topics (supplied on CD-ROM)Notes to Instructors:1)The chapter overview provides a concise summary of the main topics in each chapter.2)The correct answer for each test bank question is highlighted in bold. Test bankquestions are based on the end-of-chapter questions. If a student studies the end-of-chapter questions (which are linked to the italicized words in each chapter), then they will be successful on the test bank questions.2Chapter 1Introduction to the Semiconductor Industry Die:管芯 defective:有缺陷的Development of an Industry•The roots of the electronic industry are based on the vacuum tube and early use of silicon for signal transmission prior to World War II. The first electronic computer, the ENIAC, wasdeveloped at the University of Pennsylvania during World War II.•William Shockley, John Bardeen and Walter Brattain invented the solid-state transistor at Bell Telephone Laboratories on December 16, 1947. The semiconductor industry grew rapidly in the 1950s to commercialize the new transistor technology, with many early pioneers working inSilicon Valley in Northern California.Circuit Integration•The first integrated circuit, or IC, was independently co-invented by Jack Kilby at Texas Instruments and Robert Noyce at Fairchild Semiconductor in 1959. An IC integrates multiple electronic components on one substrate of silicon.•Circuit integration eras are: small scale integration (SSI) with 2 - 50 components, medium scale integration (MSI) with 50 – 5k components, large scale integration (LSI) with 5k to 100kcomponents, very large scale integration (VLSI) with 100k to 1M components, and ultra large scale integration (ULSI) with > 1M components.1IC Fabrication•Chips (or die) are fabricated on a thin slice of silicon, known as a wafer (or substrate). Wafers are fabricated in a facility known as a wafer fab, or simply fab.•The five stages of IC fabrication are:Wafer preparation: silicon is purified and prepared into wafers.Wafer fabrication: microchips are fabricated in a wafer fab by either a merchant chip supplier, captive chip producer, fabless company or foundry.Wafer test: Each individual die is probed and electrically tested to sort for good or bad chips.Assembly and packaging: Each individual die is assembled into its electronic package.Final test: Each packaged IC undergoes final electrical test.•Key semiconductor trends are:Increase in chip performance through reduced critical dimensions (CD), more components per chip (Moore’s law, which predicts the doubling of components every 18-24 months) andreduced power consumption.Increase in chip reliability during usage.Reduction in chip price, with an estimated price reduction of 100 million times for the 50 years prior to 1996.The Electronic Era•The 1950s saw the development of many different types of transistor technology, and lead to the development of the silicon age.•The 1960s were an era of process development to begin the integration of ICs, with many new chip-manufacturing companies.•The 1970s were the era of medium-scale integration and saw increased competition in the industry, the development of the microprocessor and the development of equipment technology. •The 1980s introduced automation into the wafer fab and improvements in manufacturing efficiency and product quality.•The 1990s were the ULSI integration era with the volume production of a wide range of ICs with sub-micron geometries.Career paths•There are a wide range of career paths in semiconductor manufacturing, including technician, engineer and management.2Chapter 2 Characteristics of Semiconductor MaterialsAtomic Structure•The atomic model has three types of particles: neutral neutrons（不带电的中子）, positively charged protons（带正电的质子）in the nucleus and negatively charged electrons（带负电的核外电子） that orbit the nucleus. Outermost electrons are in the valence shell, and influence the chemical and physical properties of the atom. Ions form when an atom gains or loses one or more electrons.The Periodic Table•The periodic table lists all known elements. The group number of the periodic table represents the number of valence shell electrons of the element. We are primarily concerned with group numbers IA through VIIIA.•Ionic bonds are formed when valence shell electrons are transferred from the atoms of one element to another. Unstable atoms (e.g., group VIIIA atoms because they lack one electron) easily form ionic bonds.•Covalent bonds have atoms of different elements that share valence shell electrons.3Classifying Materials•There are three difference classes of materials:ConductorsInsulatorsSemiconductors•Conductor materials have low resistance to current flow, such as copper. Insulators have high resistance to current flow. Capacitance is the storage of electrical charge on two conductive plates separated by a dielectric material. The quality of the insulation material between the plates is the dielectric constant. Semiconductor materials can function as either a conductor or insulator.Silicon•Silicon is an elemental semiconductor material because of four valence shell electrons. It occurs in nature as silica and is refined and purified to make wafers.•Pure silicon is intrinsic silicon. The silicon atoms bond together in covalent bonds, which defines many of silicon’s properties. Silicon atoms bond together in set, repeatable patterns, referred to asa crystal.•Germanium was the first semiconductor material used to make chips, but it was soon replaced by silicon. The reasons for this change are:Abundance of siliconHigher melting temperature for wider processing rangeWide temperature range during semiconductor usageNatural growth of silicon dioxide•Silicon dioxide (SiO2) is a high quality, stable electrical insulator material that also serves as a good chemical barrier to protect silicon from external contaminants. The ability to grow stable, thin SiO2 is fundamental to the fabrication of Metal-Oxide-Semiconductor (MOS) devices. •Doping increases silicon conductivity by adding small amounts of other elements. Common dopant elements are from trivalent, p-type Group IIIA (boron) and pentavalent, n-type Group VA (phosphorus, arsenic and antimony).•It is the junction between the n-type and p-type doped regions (referred to as a pn junction) that permit silicon to function as a semiconductor.4Alternative Semiconductor Materials•The alternative semiconductor materials are primarily the compound semiconductors. They are formed from Group IIIA and Group VA (referred to as III-V compounds). An example is gallium arsenide (GaAs).•Some alternative semiconductors come from Group IIA and VIA, referred to as II-VI compounds. •GaAs is the most common III-V compound semiconductor material. GaAs ICs have greater electron mobility, and therefore are faster than ICs made with silicon. GaAs ICs also have higher radiation hardness than silicon, which is better for space and military applications. The primary disadvantage of GaAs is the lack of a natural oxide.5Chapter 3Device TechnologiesCircuit Types•There are two basic types of circuits: analog and digital. Analog circuits have electrical data that varies continuously over a range of voltage, current and power values. Digital circuits have operating signals that vary about two distinct voltage levels – a high and a low.Passive Component Structures•Passive components such as resistors and capacitors conduct electrical current regardless of how the component is connected. IC resistors are a passive component. They can have unwanted resistance known as parasitic resistance. IC capacitor structures can also have unintentional capacitanceActive Component Structures•Active components, such as diodes and transistors can be used to control the direction of current flow. PN junction diodes are formed when there is a region of n-type semiconductor adjacent to a region of p-type semiconductor. A difference in charge at the pn junction creates a depletion region that results in a barrier voltage that must be overcome before a diode can be operated. A bias voltage can be configured to have a reverse bias, with little or no conduction through the diode, or with a forward bias, which permits current flow.•The bipolar junction transistor (BJT) has three electrodes and two pn junctions. A BJT is configured as an npn or pnp transistor and biased for conduction mode. It is a current-amplifying device.6• A schottky diode is formed when metal is brought in contact with a lightly doped n-type semiconductor material. This diode is used in faster and more power efficient BJT circuits.•The field-effect transistor (FET), a voltage-amplifying device, is more compact and power efficient than BJT devices. A thin gate oxide located between the other two electrodes of the transistor insulates the gate on the MOSFET. There are two categories of MOSFETs, nMOS (n-channel) and pMOS (p-channel), each which is defined by its majority current carriers. There is a biasing scheme for operating each type of MOSFET in conduction mode.•For many years, nMOS transistors have been the choice of most IC manufacturers. CMOS, with both nMOS and pMOS transistors in the same IC, has been the most popular device technology since the early 1980s.•BiCMOS technology makes use of the best features of both CMOS and bipolar technology in the same IC device.•Another way to categorize FETs is in terms of enhancement mode and depletion mode. The major different is in the way the channels are doped: enhancement-mode channels are doped opposite in polarity to the source and drain regions, whereas depletion mode channels are doped the same as their respective source and drain regions.Latchup in CMOS Devices•Parasitic transistors can create a latchup condition(???????) in CMOS ICs that causes transistors to unintentionally（无心的） turn on. To control latchup, an epitaxial layer is grown on the wafer surface and an isolation barrier（隔离阻障）is placed between the transistors. An isolation layer can also be buried deep below the transistors.Integrated Circuit Productsz There are a wide range of semiconductor ICs found in electrical and electronic products. This includes the linear IC family, which operates primarily with anal3og circuit applications, and the digital IC family, which includes devices that operate with binary bits of data signals.7Chapter 4Silicon and Wafer Preparation8z Semiconductor-Grade Silicon•The highly refined silicon used for wafer fabrication is termed semiconductor-grade silicon (SGS), and sometimes referred to as electronic-grade silicon. The ultra-high purity of semiconductor-grade silicon is obtained from a multi-step process referred to as the Siemens process.Crystal Structure• A crystal is a solid material with an ordered, 3-dimensional pattern over a long range. This is different from an amorphous material that lacks a repetitive structure.•The unit cell is the most fundamental entity for the long-range order found in crystals. The silicon unit cell is a face-centered cubic diamond structure. Unit cells can be organized in a non-regular arrangement, known as a polycrystal. A monocrystal are neatly arranged unit cells.Crystal Orientation•The orientation of unit cells in a crystal is described by a set of numbers known as Miller indices.The most common crystal planes on a wafer are (100), (110), and (111). Wafers with a (100) crystal plane orientation are most common for MOS devices, whereas (111) is most common for bipolar devices.Monocrystal Silicon Growth•Silicon monocrystal ingots are grown with the Czochralski (CZ) method to achieve the correct crystal orientation and doping. A CZ crystal puller is used to grow the silicon ingots. Chunks of silicon are heated in a crucible in the furnace of the puller, while a perfect silicon crystal seed is used to start the new crystal structure.• A pull process serves to precisely replicate the seed structure. The main parameters during the ingot growth are pull rate and crystal rotation. More homogeneous crystals are achieved with a magnetic field around the silicon melt, known as magnetic CZ.•Dopant material is added to the melt to dope the silicon ingot to the desired electrical resistivity.Impurities are controlled during ingot growth. A float-zone crystal growth method is used toachieve high-purity silicon with lower oxygen content.•Large-diameter ingots are grown today, with a transition underway to produce 300-mm ingot diameters. There are cost benefits for larger diameter wafers, including more die produced on a single wafer.Crystal Defects in Silicon•Crystal defects are interruptions in the repetitive nature of the unit cell. Defect density is the number of defects per square centimeter of wafer surface.•Three general types of crystal defects are: 1) point defects, 2) dislocations, and 3) gross defects.Point defects are vacancies (or voids), interstitial (an atom located in a void) and Frenkel defects, where an atom leaves its lattice site and positions itself in a void. A form of dislocation is astacking fault, which is due to layer stacking errors. Oxygen-induced stacking faults are induced following thermal oxidation. Gross defects are related to the crystal structure (often occurring during crystal growth).Wafer Preparation•The cylindrical, single-crystal ingot undergoes a series of process steps to create wafers, including machining operations, chemical operations, surface polishing and quality checks.•The first wafer preparation steps are the shaping operations: end removal, diameter grinding, and wafer flat or notch. Once these are complete, the ingot undergoes wafer slicing, followed by wafer lapping to remove mechanical damage and an edge contour. Wafer etching is done to chemically remove damage and contamination, followed by polishing. The final steps are cleaning, wafer evaluation and packaging.Quality Measures•Wafer suppliers must produce wafers to stringent quality requirements, including: Physical dimensions: actual dimensions of the wafer (e.g., thickness, etc.).Flatness: linear thickness variation across the wafer.Microroughness: peaks and valleys found on the wafer surface.Oxygen content: excessive oxygen can affect mechanical and electrical properties.Crystal defects: must be minimized for optimum wafer quality.Particles: controlled to minimize yield loss during wafer fabrication.Bulk resistivity(电阻系数): uniform resistivity from doping during crystal growth is critical. Epitaxial Layer•An epitaxial layer (or epi layer) is grown on the wafer surface to achieve the same single crystal structure of the wafer with control over doping type of the epi layer. Epitaxy minimizes latch-up problems as device geometries continue to shrink.Chapter 5Chemicals in Semiconductor FabricationEquipment Service Chase Production BayChemical Supply Room Chemical Distribution Center Holding tank Chemical drumsProcess equipmentControl unit Pump Filter Raised and perforated floorElectronic control cablesSupply air ductDual-wall piping for leak confinement PumpFilterChemical control and leak detection Valve boxes for leak containment Exhaust air ductStates of Matter• Matter in the universe exists in 3 basic states (宇宙万物存在着三种基本形态): solid, liquid andgas. A fourth state is plasma.Properties of Materials• Material properties are the physical and chemical characteristics that describe its unique identity.• Different properties for chemicals in semiconductor manufacturing are: temperature, pressure andvacuum, condensation, vapor pressure, sublimation and deposition, density, surface tension, thermal expansion and stress.Temperature is a measure of how hot or cold a substance is relative to another substance. Pressure is the force exerted per unit area. Vacuum is the removal of gas molecules.Condensation is the process of changing a gas into a liquid. Vaporization is changing a liquidinto a gas.Vapor pressure is the pressure exerted by a vapor in a closed container at equilibrium.Sublimation is the process of changing a solid directly into a gas. Deposition is changing a gas into a solid.Density is the mass of a substance divided by its volume.Surface tension of a liquid is the energy required to increase the surface area of contact.Thermal expansion is the increase in an object’s dimension due to heating.Stress occurs when an object is exposed to a force.Process Chemicals•Semiconductor manufacturing requires extensive chemicals.• A chemical solution is a chemical mixture. The solvent is the component of the solution present in larger amount. The dissolved substances are the solutes.•Acids are solutions that contain hydrogen and dissociate in water to yield hydronium ions. A base is a substance that contains the OH chemical group and dissociates in water to yield the hydroxide ion, OH-.•The pH scale is used to assess the strength of a solution as an acid or base. The pH scale varies from 0 to 14, with 7 being the neutral point. Acids have pH below 7 and bases have pH values above 7.• A solvent is a substance capable of dissolving another substance to form a solution.• A bulk chemical distribution (BCD) system is often used to deliver liquid chemicals to the process tools. Some chemicals are not suitable for BCD and instead use point-of-use (POU) delivery, which means they are stored and used at the process station.•Gases are generally categorized as bulk gases or specialty gases. Bulk gases are the relatively simple gases to manufacture and are traditionally oxygen, nitrogen, hydrogen, helium and argon.The specialty gases, or process gases, are other important gases used in a wafer fab, and usually supplied in low volume.•Specialty gases are usually transported to the fab in metal cylinders.•The local gas distribution system requires a gas purge to flush out undesirable residual gas. Gas delivery systems have special piping and connections systems. A gas stick controls the incoming gas at the process tool.•Specialty gases may be classified as hydrides, fluorinated compounds or acid gases.Chapter 6Contamination Control in Wafer FabsIntroduction•Modern semiconductor manufacturing is performed in a cleanroom, isolated from the outside environment and contaminants.Types of contamination•Cleanroom contamination has five categories: particles, metallic impurities, organic contamination, native oxides and electrostatic discharge. Killer defects are those causes of failure where the chip fails during electrical test.Particles: objects that adhere to a wafer surface and cause yield loss. A particle is a killer defect if it is greater than one-half the minimum device feature size.Metallic impurities: the alkali metals found in common chemicals. Metallic ions are highly mobile and referred to as mobile ionic contaminants (MICs).Organic contamination: contains carbon, such as lubricants and bacteria.Native oxides: thin layer of oxide growth on the wafer surface due to exposure to air.Electrostatic discharge (ESD): uncontrolled transfer of static charge that can damage the microchip.Sources and Control of Contamination•The sources of contamination in a wafer fab are: air, humans, facility, water, process chemicals, process gases and production equipment.Air: class number designates the air quality inside a cleanroom by defining the particle size and density.Humans: a human is a particle generator. Humans wear a cleanroom garment and follow cleanroom protocol to minimize contamination.Facility: the layout is generally done as a ballroom (open space) or bay and chase design.Laminar airflow with air filtering is used to minimize particles. Electrostatic discharge iscontrolled by static-dissipative materials, grounding and air ionization.Ultrapure deiniozed (DI) water: Unacceptable contaminants are removed from DI water through filtration to maintain a resistivity of 18 megohm-cm. The zeta potential represents a charge on fine particles in water, which are trapped by a special filter. UV lamps are used for bacterial sterilization.Process chemicals: filtered to be free of contamination, either by particle filtration, microfiltration (membrane filter), ultrafiltration and reverse osmosis (or hyperfiltration).Process gases: filtered to achieve ultraclean gas.Production equipment: a significant source of particles in a fab.Workstation design: a common layout is bulkhead equipment, where the major equipment is located behind the production bay in the service chase. Wafer handling is done with robotic wafer handlers. A minienvironment is a localized environment where wafers are transferred on a pod and isolated from contamination.Wafer Wet Cleaning•The predominant wafer surface cleaning process is with wet chemistry. The industry standard wet-clean process is the RCA clean, consisting of standard clean 1 (SC-1) and standard clean 2 (SC-2).•SC-1 is a mixture of ammonium hydroxide, hydrogen peroxide and DI water and capable of removing particles and organic materials. For particles, removal is primarily through oxidation of the particle or electric repulsion.•SC-2 is a mixture of hydrochloric acid, hydrogen peroxide and DI water and used to remove metals from the wafer surface.•RCA clean has been modified with diluted cleaning chemistries. The piranha cleaning mixture combines sulfuric acid and hydrogen peroxide to remove organic and metallic impurities. Many cleaning steps include an HF last step to remove native oxide.•Megasonics(兆声清洗) is widely used for wet cleaning. It has ultrasonic energy with frequencies near 1 MHz. Spray cleaning will spray wet-cleaning chemicals onto the wafer. Scrubbing is an effective method for removing particles from the wafer surface.•Wafer rinse is done with overflow rinse, dump rinse and spray rinse. Wafer drying is done with spin dryer or IPA(异丙醇) vapor dry (isopropyl alcohol).•Some alternatives to RCA clean are dry cleaning, such as with plasma-based cleaning, ozone and cryogenic aerosol cleaning.Chapter 7Metrology and Defect InspectionIC Metrology•In a wafer fab, metrology refers to the techniques and procedures for determining physical and electrical properties of the wafer.•In-process data has traditionally been collected on monitor wafers. Measurement equipment is either stand-alone or integrated.•Yield is the percent of good parts produced out of the total group of parts started. It is an indicator of the health of the fabrication process.Quality Measures•Semiconductor quality measures define the requirements for specific aspects of wafer fabrication to ensure acceptable device performance.•Film thickness is generally divided into the measurement of opaque film or transparent film. Sheet resistance measured with a four-point probe is a common method of measuring opaque films (e.g., metal film). A contour map shows sheet resistance deviations across the wafer surface.•Ellipsometry is a nondestructive, noncontact measurement technique for transparent films. It works based on linearly polarized light that reflects off the sample and is elliptically polarized.•Reflectometry is used to measure a film thickness based on how light reflects off the top and bottom surface of the film layer. X-ray and photoacoustic technology are also used to measure film thickness.•Film stress is measured by analyzing changes in the radius of curvature of the wafer. Variations in the refractive index are used to highlight contamination in the film.•Dopant concentration is traditionally measured with a four-point probe. The latest technology is the thermal-wave system, which measures the lattice damage in the implanted wafer after ion implantation. Another method for measuring dopant concentration is spreading resistance probe. •Brightfield detection is the traditional light source for microscope equipment. An optical microscope uses light reflection to detect surface defects. Darkfield detection examines light scattered off defects on the wafer surface. Light scattering uses darkfield detection to detectsurface particles by illuminating the surface with laser light and then using optical imaging.•Critical dimensions (CDs) are measured to achieve precise control over feature size dimensions.The scanning electron microscope is often used to measure CDs.•Conformal step coverage is measured with a surface profiler that has a stylus tip.•Overlay registration measures the ability to accurately print photoresist patterns over a previously etched pattern.•Capacitance-voltage (C-V) test is used to verify acceptable charge conditions and cleanliness at the gate structure in a MOS device.Analytical Equipment•The secondary-ion mass spectrometry (SIMS) is a method of eroding a wafer surface with accelerated ions in a magnetic field to analyze the surface material composition.•The atomic force microscope (AFM) is a surface profiler that scans a small, counterbalanced tip probe over the wafer to create a 3-D surface map.•Auger electron spectroscopy (AES) measures composition on the wafer surface by measuring the energy of the auger electrons. It identifies elements to a depth of about 2 nm. Another instrument used to identify surface chemical species is X-ray photoelectron spectroscopy (XPS).•Transmission electron microscopy (TEM) uses a beam of electrons that is transmitted through a thin slice of the wafer. It is capable of quantifying very small features on a wafer, such as silicon crystal point defects.•Energy-dispersive spectrometer (EDX) is a widely used X-ray detection method for identifying elements. It is often used in conjunction with the SEM.• A focused ion beam (FIB) system is a destructive technique that focuses a beam of ions on the wafer to carve a thin cross section from any wafer area. This permits analysis of the wafermaterial.Chapter 8Gas Control in Process ChambersEtch process chambers••The process chamber is a controlled vacuum environment where intended chemical reactions take place under controlled conditions. Process chambers are often configured as a cluster tool. Vacuum•Vacuum ranges are low (rough) vacuum, medium vacuum, high vacuum and ultrahigh vacuum (UHV). When pressure is lowered in a vacuum, the mean free path(平均自由行程) increases, which is important for how gases flow through the system and for creating a plasma.Vacuum Pumps•Roughing pumps are used to achieve a low to medium vacuum and to exhaust a high vacuum pump. High vacuum pumps achieve a high to ultrahigh vacuum.•Roughing pumps are dry mechanical pumps or a blower pump (also referred to as a booster). Two common high vacuum pumps are a turbomolecular (turbo) pump and cryopump. The turbo pump is a reliable, clean pump that works on the principle of mechanical compression. The cryopump isa capture pump that removes gases from the process chamber by freezing them.。

半导体制造技术
半导体制造技术是指以半导体材料为基础，利用先进的设备、工艺和测试技术，在晶圆上制作各种尺寸、形状和功能的集成电路（IC）元件。

半导体制造技术包括晶圆生产、片上集成、封装、测试等一系列步骤。

晶圆生产技术是半导体制造的核心步骤，其目的是在晶圆表面形成一层导电层，用于在其表面制作微纳米尺寸的元件及连接线路。

常用的晶圆生产技术有光刻、电镀、气相沉积、激光刻蚀、无损整形、金属化学气相沉积等。

片上集成技术是将器件与线路集成在一个晶片上，实现信号传输及功能实现。

目前，在片上集成中使用的技术主要有光刻、激光刻蚀和激光加工等。

封装技术是指将晶片封装到一个容器中，以便将其与外部电路和环境完全隔离，并保护其内部结构。

一般来说，封装技术可以分为焊接、固化、涂覆、压合和滴胶等。

测试技术是检查半导体元件及集成电路性能的手段，如功耗测试、性能测试、动态测试、稳态测试等。

半导体sgt工艺(一)半导体sgt工艺介绍•半导体sgt工艺是一种重要的制程技术，用于制造先进的半导体器件。

•SGT是Selective Growth Transistor的缩写，选择性生长晶体管。

•它通过控制晶体管的生长方向和材料特性，使得器件性能更优秀。

工艺流程1.接收基片–首先，选择合适的半导体基片作为起始材料。

–基片的选择要符合所需器件的特定要求。

2.清洗准备–对基片进行严格的清洗准备，以去除表面的杂质和污染物。

–清洗过程中使用特定的溶液和工艺参数，确保表面的纯净度和平整度。

3.预先处理–对基片进行一系列的预处理步骤，以增强材料的表面活性和吸附能力。

–预处理通常包括化学气相沉积（CVD）或物理气相沉积（PVD）等工艺。

4.蚀刻处理–利用化学蚀刻或物理蚀刻的方式，对基片进行局部削减和形状调整。

–蚀刻处理会在基片表面形成必要的结构和凹陷，以便后续的生长步骤。

5.晶体管生长–在设计好的区域上进行晶体管的选择性生长。

–借助CVD或其他生长工艺，沉积特定材料在预定位置上，形成晶体管结构。

6.后续处理–对晶体管进行后续的清洗和退火处理，提高材料的结晶质量和界面特性。

–还可能包括沉积其他材料层、刻蚀、光刻等工艺，以完成整个器件的制造。

应用领域•SGT工艺广泛应用于高性能和先进的半导体器件制造，特别是：–高频器件：如射频放大器、微波器件等。

–低功耗CMOS器件：如功耗控制电路、片上系统等。

–光电器件：如光电二极管、光电传感器等。

优势和挑战•优势：–半导体sgt工艺能够提高器件性能，如频率响应、开关速度、功耗等。

–可实现精确的材料控制和器件结构设计。

–适应性强，可以应用于不同材料和器件类型。

•挑战：–工艺复杂，需要精确的控制和长时间的优化。

–成本较高，对设备和材料的投入要求较高。

–需要与其他工艺相结合，以实现完整的器件制造。

结论•半导体sgt工艺作为一种先进的制程技术，在半导体器件制造领域发挥着重要作用。

一．论述1、例出光刻的8个步骤，并对每一步做出简要解释。

（P316）第一步：气相成底膜处理，光刻的第一步是清洗、脱水和硅片表面成底膜处理，其目的是增强硅片和光刻胶之间的粘附性。

脱水烘干以去除吸附在硅片表面大部分水汽。

脱水烘干后硅片立即要用六甲基二硅胺烷（HMDS）进行成膜处理，起到粘附促进剂的作用。

第二步：旋转涂胶，成底膜处理后，硅片要立即采用旋转涂胶的方法涂上液相光刻胶材料。

将硅片被固定在真空载片台上，它是一个表面上有很多真空孔以便固定硅片的平的金属或聚四氯乙烯盘。

一定数量的液体光刻胶滴在硅片上，然后硅片旋转得到一层均匀的光刻胶图层第三步：软烘，去除光刻胶中的溶剂第四步：对准和曝光，把掩膜版图形转移到涂胶的硅片上第五步：曝光后烘培，将光刻胶在100到110的热板上进行曝光后烘培第六步：显影，在硅片表面光刻胶中产生图形。

光刻胶上的可溶解区域被化学显影剂溶解，将可见的岛或者窗口图形留在硅片表面。

最通常的显影方法是旋转、喷雾、浸润，然后显影，硅片用去离子水（DI）冲洗后甩干。

第七步：坚膜烘培，挥发掉存留的光刻胶溶剂，提高光刻胶对硅片表面的粘附性第八步：显影后检查，检查光刻胶图形的质量，找出有质量问题的硅片，描述光刻胶工艺性能以满足规范要求2.解释发生刻蚀反应的化学机理和物理机理。

（P412）干法刻蚀系统中，刻蚀作用是通过化学作用或物理作用，或者化学和物理的共同作用来实现的。

在纯化学机理中，等离子体产生的反应元素（自由基和反应原子）与硅片表面的物质发生反应。

物理机理的刻蚀中，等离子体产生的能带粒子（轰击的正离子）在强电场下朝硅片表面加速，这些离子通过溅射刻蚀作用去除未被保护的硅片表面材料。

3.描述CVD反应中的8个步骤。

(P247)1) 气体传输至淀积区域：反应气体从反应腔入口区域流动到硅片表面的淀积区域；2) 膜先驱物的形成：气相反应导致膜先驱物（将组成最初的原子和分子）和副产物的形成；3) 膜先驱物附着在硅片表面：大量膜先驱物输运到硅片表面；4)膜先驱物粘附：膜先驱物粘附在硅片表面；5) 膜先驱物扩散：膜先驱物向膜生长区域的表面扩散；6) 表面反应：表面化学反应导致膜淀积和副产物的生成；7) 副产物从表面移除：吸附（移除）表面反应的副产物8）副产物从反应腔移除：反应副产物从淀积区域随气体流动到反应腔出口并排出5.离子注入设备的5个主要子系统。

半导体制造技术题库一1、问答题画出侧墙转移工艺和self-aligned double patterning（SADP）的工艺流程图。

解析：2、问答题从寄生电阻和电容、电迁移两方面说明后道工艺中（Back-End-Of-Line，BEOL）采用铜（Cu）互连和低介电常数（low-k）材料的必要性。

解析：寄生电阻和寄生电容造成的延迟。

电子在导电过程中会撞击导体中的离子，将动量转移给离子从而推动离子发生缓慢移动。

该现象称为电迁移。

在导电过程中，电迁移不断积累，并最终在导体中产生分散的缺陷。

这些缺陷随后集合成大的空洞，造成断路。

因此，电迁移直接影响电路的可靠性。

采用铜互连可大幅降低金属互连线的电阻从而减少互连造成的延迟。

铜的电迁移比铝材料小很多：铜的晶格扩散的激活能为2.2eV，晶界扩散结合能在0.7到1.2eV之间；而铝分别为1.4eV和0.4-0.8eV.采用低介电常数材料填充平行导线之间的空间可降低金属互连线之间的电容从而减少延迟。

采用铜/low-k互连可大幅减小互连pitch，从而减少互连金属层数。

3、问答题简述APCVD、LPCVD、PECVD的特点。

解析：APCVD——一些最早的CVD工艺是在大气压下进行的，由于反应速率快，CVD系统简单，适于较厚的介质淀积。

APCVD缺点：台阶覆盖性差；膜厚均匀性差；效率低。

常压下扩散系数小，hg<<ks，apcvd一般是由质量输运控制淀积速率一个主要问题是颗粒的形成。

在气体注入器处可能发生异质淀积，在淀积了若干晶圆片后，颗粒变大剥落并落在晶圆片表面。

为避免这一问题可采用多通道的喷头设计。

lpcvd——低压化学气相淀积系统淀积的某些薄膜，在均匀性和台阶覆盖等方面比apcvd系统的要好，而且污染也少。

另外，在不使用稀释气体的情况下，通过降低压强就可以降低气相成核。

br="">在LPCVD系统中，因为低压使得扩散率增加，因此PECVD——等离子体增强化学气相淀积（PECVD.是目前最主要的化学气相淀积系统。

【关键字】技术半导体制造技术-半导体天地半导体论坛1.扩散工艺的性能指标有哪些啊主要是方块电阻和结深，这两个指标达到了，其他的方面也就满足要求了多晶硅的方块电阻和结深对于生产线来说，主要监控片内和片间的均匀性和方块大小，结深测试是破坏性的仅有在开发阶段进行验证正常只要方阻和片内及片间的均与性，测试结深一般需要破坏圆片的，正常是在试验期做，批量生产时也可以利用陪片来测量。

片子的均匀性是指电阻分布的均匀性，RS测量包括49个点及9点的测量类型，均匀性就是这49个点或9点的电阻的均方差3.为什么注入的深，方块电阻小？注入菜单仅能量不一样。

谁来说说？一直没明白。

是因为注入的浅点的话，退火时外扩散，剂量损失？载流子浓度越大，电阻低。

可以想象成导线直径越大，电阻越小就是注入越深PN结就越窄以前在书上有看到过关于注入时浓度最高的地方不是在最上和最底下是在靠中间的位置，这样分析的话可能深度越深的话高的浓度越易产生吧，不敢肯定是这样有问题大家指正哈！注入相同剂量,注入能量越大,激活后纵向分布越宽广,区域浓度变淡,相应的迁移率变大,综合下来电阻变小.RS=P(resisitivity)/t(thickness) 深度增加，RS减小注入相同剂量,注入能量越大,激活后纵向分布越宽广,区域浓度变淡,相应的迁移率变大,综合下来电阻变小.例举一下吧，你扩散的越深，载流子越多，导电性越强，电阻自然会变小了4. AP和LP炉管的区别AP表示常压process,LP表示低压下processAP有reactive tube,通常gas由上至下流下經由控压至exhaustLP gas由下往上流.經由pump抽真空作process.AP制程是靠晶片本身氧化作用LP制程是GAS反映depo在晶片上.APCVD是常压CVD, 好像没有炉管可以做APCVD的，LPCVD是低压CVD,一般process时压力达到200mmtor，水平或垂直炉管都可以实现，有PUMP抽气，APC实现压力的控制AP 管主要是thermal 和氧化SI SUBSTRACE 长OX 而LP 管主要是通过反应在SI 上面长film5.氧化层厚度如何控制好?我觉得只能是试验的问题了,多试几次,保证重复性.炉管温度是能稳定得很好的,气流流量自然也能控制得比较好.每次氧化这两个量都能比较好的重复.推进和拉出的时间也要每次一致.所能做的就是降低氧化速度,这样的话控制起来会更容易一点,不过就增加了时间,高温过程时间变长是很不利的.所以就中和考虑一下,在能容忍的时间范围内尽量降低氧化速度.个人意见,不知道对不对,6.另外还有个问题,在掺杂的硅片上为什么掺B氧化层厚度与Rs成反比,而掺P的成反比!分凝系数不一样,B趋向于向氧化层混合,而P趋向于远离氧化层,至于为什么分凝系数不一样,就从材料内部Si和二氧化硅的晶格结构上解释简单说::就是长氧化层后,B有一部分会向氧化层中扩散,而P向背向氧化层扩散sio2会排磷吸硼因磷和硼分子大小不同，穿透oxide的能力不同，亦即主要穿透方式不同(P motion by vacancy ; B motion by interstitialcy)对呀,硼的分凝系数(杂质在硅中的平恒浓度/杂质在二氧化硅中的平恒浓度)m1.不过真的有正反比的关系吗7.求教:二氧化硅问题(隔离机制) 我看到一篇关于二氧化硅的材料:1,若杂质比硅更可溶于氧化物,则杂质氧化过程中会迁移到氧化物中,如硼.相反,杂质更易溶于硅,氧化界面会把杂质推移到硅中.如磷.在硅----二氧化硅界面会有较高浓度.也就是所谓的隔离机制(亲硼排磷)吧.2,杂质(硼,磷,砷等)在氧化层中的扩散系数远小于在硅中的扩散系数，因此氧化层具有阻挡杂质向半导体中扩散的能力.请问这两者有矛盾吗?没矛盾啊,隔离主要发生在interface,而后面的扩散是指在si或者sio2内的.是呀,我问过公司前辈了.阻挡层主要是注入时的屏蔽作用.扩散隔离机制是在si或者sio2内时,才考虑分凝系数的.在Si和SiO2界面，B会向SiO2和Si两个方向扩散，但B在SiO2中的扩散系数、固溶度比P等其他元素大，所以这种分凝系数就大，在考虑浓度时就要考虑B在SiO2中扩散的那一部分，相对没有氧化层的浓度低很多。

第1篇一、引言半导体制造工艺是半导体产业的核心技术，它是将半导体材料制备成各种电子器件的过程。

随着科技的飞速发展，半导体产业在电子信息、通信、计算机、国防等领域发挥着越来越重要的作用。

本文将从半导体制造工艺的基本概念、主要工艺步骤、常用设备等方面进行阐述。

二、半导体制造工艺的基本概念1. 半导体材料半导体材料是指导电性能介于导体和绝缘体之间的材料。

常用的半导体材料有硅、锗、砷化镓等。

其中，硅是半导体产业中最常用的材料。

2. 半导体器件半导体器件是指利用半导体材料的电学特性制成的各种电子元件，如二极管、晶体管、集成电路等。

3. 半导体制造工艺半导体制造工艺是指将半导体材料制备成各种电子器件的过程，包括材料制备、器件结构设计、器件制造、封装测试等环节。

三、半导体制造工艺的主要步骤1. 原料制备原料制备是半导体制造工艺的第一步，主要包括单晶生长、外延生长等。

（1）单晶生长：通过化学气相沉积（CVD）、物理气相沉积（PVD）等方法，将半导体材料制备成单晶硅。

（2）外延生长：在外延衬底上生长一层或多层半导体材料，形成具有特定结构和性能的薄膜。

2. 器件结构设计器件结构设计是根据器件的功能需求，确定器件的结构和参数。

主要包括器件类型、结构尺寸、掺杂浓度等。

3. 器件制造器件制造是半导体制造工艺的核心环节，主要包括光刻、蚀刻、离子注入、化学气相沉积、物理气相沉积等。

（1）光刻：利用光刻机将器件图案转移到半导体材料上。

（2）蚀刻：利用蚀刻液或等离子体将半导体材料上不需要的部分去除。

（3）离子注入：将掺杂剂以高能离子形式注入半导体材料中，改变其电学特性。

（4）化学气相沉积：利用化学反应在半导体材料表面沉积一层薄膜。

（5）物理气相沉积：利用物理过程在半导体材料表面沉积一层薄膜。

4. 封装测试封装测试是将制造好的半导体器件进行封装，并进行性能测试的过程。

（1）封装：将半导体器件封装在保护壳中，以防止外界环境对器件的影响。

半导体制造技术1.列举出在一个单晶硅衬底上制作电阻器的三种方法。

答：集成电路电阻可以通过金属膜，掺杂的多晶硅，或者通过杂质扩散到衬底的特定区域中产生。

2.什么是平面电容器？描述在硅衬底上制作这种元件的四种技术。

答：平面电容器可由金属薄层,掺杂的多晶硅,或者衬底的扩散区形成.通常衬底上的电容器由4种基本工艺组成。

3.什么是CMOS器件的闩锁效应?它能引起什么样的不希望情况？答：CMOS器件中的pn结能产生寄生晶体管，它能在CMOS集成电路中产生闩锁效应以致引起晶体管的无意识开启.4.为什么掺杂材料要在CZ法中加入到熔体中？答：5.描述或画出4种硅片定位边的图。

在200mm及以上硅片中用什么代替了定位边？答:在硅锭上做一个定位边来标明晶体结构和硅片的晶向。

主定位边标明了晶体结构的晶向,次定位边标明了硅片的晶向和导电类型.四种定位边分别为P型（111），P型（100),N型（111），N型(100）.在200mm及以上硅片中用定位槽代替了定位边。

6.描述在硅片厂中使用的去离子水的概念。

答：去离子水是在半导体制造过程中广泛使用的溶剂，在它里面没有任何导电的离子。

它的PH值为7,既不是酸也不是碱，是中性的。

它能溶解其他物质，包括许多离子化合物和共价化合物。

当水分子溶解离子化合物时，它们通过克服离子间离子键使离子分离，然后包围离子,最后扩散到液体中.7.对净化间做一般性描述。

答：8.说明五类净化间沾污。

答：净化间沾污分为五类:1）颗粒2）金属杂质3)有机物沾污4）自然氧化层5）静电释放。

9.什么是颗粒？什么是浮质？为什么颗粒是半导体制造的一个问题？答：颗粒是能粘附在硅片表面的小物体。

悬浮在空气中传播的颗粒被称为浮质。

对于半导体制造，我们的目标是控制并减少硅片与颗粒的接触。

在硅片制造过程中，颗粒能引起电路开路或短路。

它们能在相邻导体间引起短路。

颗粒还可以是其他类型沾污的来源.10.解释自然氧化层。

识别由自然氧化层引起的三种问题。