EDA数字钟程序代码

摘要利用MAX+PLUSⅡ软件，设计一个能进行时、分、秒计时的24制多功能数字钟，使其具有定时与闹钟功能，且能在设定的时间发出闹铃音，能非常方便地对时、分、秒进行手动调节以校准时间，每逢整点，产生报时音效，并在实验板上成功下载，验证后满足要求。

关键词：EDA ； MAX+PLUS2 ；数字钟；0 引言随着科学技术的发展，现代电子设计技术已进入一个全新的阶段，传统的电子设计方法、工具和器件在更大的程度上被EDA所取代。

在EDA技术中，最为瞩目的是以现代电子技术为特征的逻辑设计仿真测试技术，该技术的出现，使电子系统设计发生了质的变化,设计速度快、体积小、重量轻、功耗小的集成电路已成为趋势。

本文利用EDA 技术,选用ALTERA公司的CPLD器件EPF10K10LC84-4和软件MAX+PLUS2，设计了一个多功能数字钟，提高了系统的整体性能和可靠性，并通过编译、仿真、下载，经验证后已满足要求。

1 多功能数字钟设计任务1.1 数字钟设计要求（1）、设计一个能显示1/10秒、秒、分、时的12小时数字钟。

（2）、熟练掌握各种计数器的使用。

（3）、能用计数器构成十进制、六十进制、十二进制等所需进制的计数器。

（4）、能用低位的进位输出构成高位的计数脉冲。

1.2 设计思路此设计可分为主控电路、计数器模块和扫描显示三大模块。

1.2.1 主控电路模块主控电路状态用表格显示，如下表所列：模式选择秒、时、分、计数器脉冲输出状态备注Reset Reset1 A B Turn LD-h LD-m LD-alert0 X X X X X 0 0 0 系统复位1 X 0 0 X CLK 0 0 0 系统计时1 X 0 1 0 Change=分计数器加1 0 1 0手动1 X 0 1 1 Change=时计数器加1 1 0 0校时1 1 1 0 0 Change=分计数器加1 0 1 1 设置闹钟1 1 1 0 1 Change=时计数器加11 0 11 0 X X X X 0 0 0 关闭闹钟1.2.2 计数器模块计数器模块中，分钟和秒用带进位位的60进制功能模块，小时用不带进位位的24进制功能模块（如果考虑到日期的问题，在24进制模块加进位输出即可实现）。

1、计时模块的源程序如下：1）秒计数VHDL源程序：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity second60 isport( clk,rst,en: in std_logic; --rst为复位控制信号，en为时钟开关s1: out std_logic_vector(3 downto 0); --秒十位s0: out std_logic_vector(3 downto 0); --秒个位co: out std_logic); --进位输出end second60;architecture rtl of second60 issignal s0_0,s1_1:std_logic_vector(3 downto 0);begins1<=s1_1;s0<=s0_0;process(clk,rst) --该进程处理秒的个位beginif(rst='0') then --异步复位s0_0<="0000";elsif(clk'event and clk='1') thenif(en='1') thenif(s0_0="1001") then --当秒个位为9时，个位清零s0_0<="0000";elses0_0<=s0_0+1; --秒个位加1end if;end if;end if;end process;process(clk,rst) --该进程处理秒的十位beginif(rst='0') then --异步复位s1_1<="0000";elsif(clk'event and clk='1') thenif(en='1' and s0_0="1001") then --如果秒的个位等于9if(s1_1="0101") then --且秒的十位等于5s1_1<="0000"; --秒十位清零elses1_1<=s1_1+1; --秒十位加1end if;end if;end if;end process;--------------------------------------------------------------------------------process(s0_0,s1_1,en) --该进程处理秒的进位beginif(en='1' and s0_0="1001" and s1_1="0101") then --当秒的个位等于9，十位等于5时，产生进位co<='1';elseco<='0';end if;end process;end rtl;2）分计数VHDL源程序：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity minute60 isport( clk,en,rst: in std_logic; --rst为复位控制信号，en为时钟开关m1: out std_logic_vector(3 downto 0); --分十位m0: out std_logic_vector(3 downto 0); --分个位co: out std_logic); --进位输出end minute60;architecture rtl of minute60 issignal m0_0,m1_1:std_logic_vector(3 downto 0);beginm1<=m1_1;m0<=m0_0;process(clk,rst) --该进程处理分的个位beginif(rst='0') then --异步复位m0_0<="0000";elsif(clk'event and clk='1') thenif(en='1') thenif(m0_0="1001") then --当分个位为9时，个位清零m0_0<="0000";elsem0_0<=m0_0+1; --分个位加1end if;end if;end if;end process;process(clk,rst) --该进程处理分的十位beginif(rst='0') then --异步复位m1_1<="0000";elsif(clk'event and clk='1') thenif(en='1' and m0_0="1001") then --如果分的个位等于9 if(m1_1="0101") then --且分的十位等于5m1_1<="0000"; --分十位清零elsem1_1<=m1_1+1; --分十位加1end if;end if;end if;end process；process(m0_0,m1_1,en) --该进程处理分的进位beginif(en='1' and m0_0="1001" and m1_1="0101") thenco<='1';elseco<='0';end if;end process;end rtl;3）小时计数器的VHDL源程序：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity hour24 isport( clk,en,rst: in std_logic; --rst清零控制，en启动控制h1: out std_logic_vector(3 downto 0); --小时的十位h0: out std_logic_vector(3 downto 0)); --小时的个位end hour24;architecture rtl of hour24 issignal h0_0,h1_1:std_logic_vector(3 downto 0);beginh1<=h1_1;h0<=h0_0;------------------------------------------------------------------------ process(clk,rst) --该进程处理小时的个位beginif(rst='0') then --异步复位h0_0<="0000";elsif(clk'event and clk='1') thenif(en='1') thenif(h0_0="1001" or(h1_1="0010" and h0_0="0011")) thenh0_0<="0000";elseh0_0<=h0_0+1;end if;end if;end if;end process;------------------------------------------------------------------------------- process(clk,rst) --该进程处理小时的十位beginif(rst='0') then --异步复位h1_1<="0000";elsif(clk'event and clk='1') thenif(en='1' and h1_1="0010" and h0_0="0011") thenh1_1<="0000";elsif(h0_0="1001") then --当个位等于9时十位加1h1_1<=h1_1+1;end if;end if;end process;end rtl;/view/0f97c880e53a580216fcfe89.html。

EDA技术应用课程设计报告题目名称：多功能数字钟专业班级：_________________________姓名：_______________学号：_______________小组成员：_____________________指导教师：_______________设计时间：15-12-01 〜15-12-25、设计目的1. 使得更加了解EDA的应用2. 熟悉VHDL的编程。

3. 对于编程语句的编辑与纠错有较大的提升4. 提升对于设计方面的能力二、设计要求1. 数字钟具有“时”、“分”、“秒”显示功能，其中时功能为24小时制。

2. 数字钟具有校时和校分功能。

3. 数字钟具有整点报时功能。

七段译码管通过分别作出秒模块、分钟模块、小时模块、整点报时模块，导入动态扫描模块，再由其输出到数码管输出四、模块设计1. 秒程序模块inst① 有3输入3输出② reset 为异步清零当没有信号时清零秒模块的计数③ setmin 为校分 当有信号时想分模块进一位④ daout_a 与daout_b 为输出的信号分别为秒的高位与低位 ⑤ enmin 负责向下一个模块进位⑥ elk 为时钟信号2. 分钟程序模块1.4 ■ lisadii 4 ・ I =・■■>・ E i a !■■■■・・ i a ■■IB *・ :fen.i insti [... ... . . . . .② 3输入3输出② reset 为异步清零当没有信号时清零分模块的计数③ sethour 为校分 当有信号时向时模块进一位④ daout_ma 分daout_mb 为输出的信号分别为分的高位与 低位rstJ ⑧elk 为时钟信号3. 小时程序模块-xiaoshi■ resetdaout_ha[7..4] elk daout_hb[3..0]■ !■inst24 -有2输入2输出② reset 为异步清零当没有信号时清零时模块的计数③ elk 为时钟信号⑤daout_ha daout_hb 为输出的信号分别为时的高位与低位4. 动态扫描模块① 有八个输入端，两个输出端② reset 为异步清零当没有信号时清零时模块的计数5. 七段译码管模块sbijian_g[3..O]ffrn_5j7. .4；叫卩.0] Xiaos卜」1： .4]XHDS I"I _3J1. .3]加U 眼q 詢陀.0]①有1输入8输出②S为用来接收秒分时模块输出的信号③A~H为转化后的信号用来接数码管6. 整点报时模块①有5输入2输出②Clkspk为时钟信号③Miao_h Miao」fen_h fen_h 为从秒模块时模块接收的信号④Speak接蜂鸣器，⑤Lamp接LED作为报时时的闪烁灯五、模块程序1. 秒模块设计（60计时制）library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_ un sig ned.all;en tity shijia n is port(reset,clk,setmi n:i n std_logic;daout_a:out std」o gic_vector(7 dow nto 4);--- 输出高位daout_adaout_b:out std_logic_vector(3 dow nto 0);------- 输出低位daou_benmin :out std_logic);----------- e nmin是向分位进位信号end shijia n;architecture behav of shijia n issig nal coun t:std_logic_vector(3 dow nto 0);sig nal coun ter:std_logic_vector(3 dow nto 0);signal carry_out1:std_logic; -------------------- 59 秒时的进位信号sig nal carry_out2:std_logic;begi np1:process(reset,clk)begi nif reset='O'then ----------- 59秒时的进位信号cou nt<="OOOO";cou nter<="OOOO";――若reset为0时，则高、低位异步清零elsif(clk'eve nt and clk='1')the n――否则clk为上升沿时if(co un ter<5)the nif(co un t=9)the ncou nt<="0000"coun ter<=co un ter+1;elsecoun t<=co un t+1;end if;carry_out1<='0：--- 若高位counter<5,低位count=9，则低位清零，高位进否则低位进一，59秒时的进位信号carry_out1为0。

调时：shi加1，fen加1，miao清0；报时：59分50、52、54、56、58秒500HZ,0分0秒1000HZ; (一百八十多个警告……)分频器1HZ：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity fpq1 isport(clk_in:in std_logic;clk_out:out std_logic);end ;architecture one of fpq1 isbeginprocess(clk_in)constant counter_len:integer:=19999999;variable cnt:integer range 0 to counter_len;beginif clk_in'event and clk_in='1' thenif cnt=counter_len thencnt:=0;elsecnt:=cnt+1;end if;case cnt iswhen 0 to counter_len/2=>clk_out<='0';when others =>clk_out<='1';end case;end if;end process;end one;分频器500HZ：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity fpq500 isport(clk_in:in std_logic;clk_out:out std_logic);end ;architecture one of fpq500 isbeginprocess(clk_in)constant counter_len:integer:=19999;variable cnt:integer range 0 to counter_len;beginif clk_in'event and clk_in='1' thenif cnt=counter_len thencnt:=0;elsecnt:=cnt+1;end if;case cnt iswhen 0 to counter_len/2=>clk_out<='0';when others =>clk_out<='1';end case;end if;end process;end one;分频器1000HZ：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity fpq1000 isport(clk_in:in std_logic;clk_out:out std_logic);end ;architecture one of fpq1000 isbeginprocess(clk_in)constant counter_len:integer:=9999;variable cnt:integer range 0 to counter_len;beginif clk_in'event and clk_in='1' thenif cnt=counter_len thencnt:=0;elsecnt:=cnt+1;end if;case cnt iswhen 0 to counter_len/2=>clk_out<='0';when others =>clk_out<='1';end case;end if;end process;end one;位选：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity wei isport ( clk1000 : in std_logic;q : buffer std_logic_vector(2 downto 0 ));end;architecture one of wei issignal q1: std_logic_vector(2 downto 0 );beginprocess( clk1000 )beginif rising_edge(clk1000) thenif q1="111" then q1<="000";else q1<=q1+1;end if;end if;q<=q1;end process;end;段选：library ieee;use ieee.std_logic_1164.all;entity duan isport(clk1:in std_logic;clk500:in std_logic;clk1000:in std_logic;shi:in std_logic;fen:in std_logic;miao:in std_logic;duan:out std_logic_vector(6 downto 0);wei:out std_logic_vector(2 downto 0);rang:out std_logic);end;architecture one of duan issignal duan1,duan2,duan3,duan4,duan5,duan6,duan7,duan8:std_logic_vector(6 downto 0); beginprocess(clk1)variable s:integer:=0;variable f:integer:=0;variable m:integer:=0;variable guan:integer:=0;beginif clk1'event and clk1='1' thenm:=m+1;if m=60 then m:=0 ;f:=f+1;end if;if f=60 then f:=0 ;s:=s+1;end if;if s=24 then s:=0 ;end if;end if;case m iswhen 0|10|20|30|40|50|60|70|80|90 => duan1<="0111111"; when 1|11|21|31|41|51|61|71|81|91 => duan1<="0000110"; when 2|12|22|32|42|52|62|72|82|92 => duan1<="1011011"; when 3|13|23|33|43|53|63|73|83|93 => duan1<="1001111"; when 4|14|24|34|44|54|64|74|84|94 => duan1<="1100110"; when 5|15|25|35|45|55|65|75|85|95 => duan1<="1101101"; when 6|16|26|36|46|56|66|76|86|96 => duan1<="1111101"; when 7|17|27|37|47|57|67|77|87|97 => duan1<="0000111"; when 8|18|28|38|48|58|68|78|88|98 => duan1<="1111111"; when 9|19|29|39|49|59|69|79|89|99 => duan1<="1101111"; when others => duan1<=null;end case;case m iswhen 0|1|2|3|4|5|6|7|8|9 => duan2<="0111111"; when 10|11|12|13|14|15|16|17|18|19 => duan2<="0000110"; when 20|21|22|23|24|25|26|27|28|29 => duan2<="1011011"; when 30|31|32|33|34|35|36|37|38|39 => duan2<="1001111"; when 40|41|42|43|44|45|46|47|48|49 => duan2<="1100110"; when 50|51|52|53|54|55|56|57|58|59 => duan2<="1101101"; when 60|61|62|63|64|65|66|67|68|69 => duan2<="1111101"; when 70|71|72|73|74|75|76|77|78|79 => duan2<="0000111"; when 80|81|82|83|84|85|86|87|88|89 => duan2<="1111111"; when 90|91|92|93|94|95|96|97|98|99 => duan2<="1100111";when others => duan2<=null;end case;duan3<="1000000";case f iswhen 0|10|20|30|40|50|60|70|80|90 => duan4<="0111111"; when 1|11|21|31|41|51|61|71|81|91 => duan4<="0000110"; when 2|12|22|32|42|52|62|72|82|92 => duan4<="1011011"; when 3|13|23|33|43|53|63|73|83|93 => duan4<="1001111"; when 4|14|24|34|44|54|64|74|84|94 => duan4<="1100110"; when 5|15|25|35|45|55|65|75|85|95 => duan4<="1101101"; when 6|16|26|36|46|56|66|76|86|96 => duan4<="1111101"; when 7|17|27|37|47|57|67|77|87|97 => duan4<="0000111"; when 8|18|28|38|48|58|68|78|88|98 => duan4<="1111111"; when 9|19|29|39|49|59|69|79|89|99 => duan4<="1101111"; when others => duan4<=null;end case;case f iswhen 0|1|2|3|4|5|6|7|8|9 => duan5<="0111111"; when 10|11|12|13|14|15|16|17|18|19 => duan5<="0000110"; when 20|21|22|23|24|25|26|27|28|29 => duan5<="1011011"; when 30|31|32|33|34|35|36|37|38|39 => duan5<="1001111"; when 40|41|42|43|44|45|46|47|48|49 => duan5<="1100110"; when 50|51|52|53|54|55|56|57|58|59 => duan5<="1101101"; when 60|61|62|63|64|65|66|67|68|69 => duan5<="1111101"; when 70|71|72|73|74|75|76|77|78|79 => duan5<="0000111"; when 80|81|82|83|84|85|86|87|88|89 => duan5<="1111111"; when 90|91|92|93|94|95|96|97|98|99 => duan5<="1100111"; when others => duan5<=null;end case;duan6<="1000000";case s iswhen 0|10|20|30|40|50|60|70|80|90 => duan7<="0111111"; when 1|11|21|31|41|51|61|71|81|91 => duan7<="0000110";when 2|12|22|32|42|52|62|72|82|92 => duan7<="1011011"; when 3|13|23|33|43|53|63|73|83|93 => duan7<="1001111"; when 4|14|24|34|44|54|64|74|84|94 => duan7<="1100110"; when 5|15|25|35|45|55|65|75|85|95 => duan7<="1101101"; when 6|16|26|36|46|56|66|76|86|96 => duan7<="1111101"; when 7|17|27|37|47|57|67|77|87|97 => duan7<="0000111"; when 8|18|28|38|48|58|68|78|88|98 => duan7<="1111111"; when 9|19|29|39|49|59|69|79|89|99 => duan7<="1101111"; when others => duan7<=null;end case;case s iswhen 0|1|2|3|4|5|6|7|8|9 => duan8<="0111111"; when 10|11|12|13|14|15|16|17|18|19 => duan8<="0000110"; when 20|21|22|23|24|25|26|27|28|29 => duan8<="1011011"; when 30|31|32|33|34|35|36|37|38|39 => duan8<="1001111"; when 40|41|42|43|44|45|46|47|48|49 => duan8<="1100110"; when 50|51|52|53|54|55|56|57|58|59 => duan8<="1101101"; when 60|61|62|63|64|65|66|67|68|69 => duan8<="1111101"; when 70|71|72|73|74|75|76|77|78|79 => duan8<="0000111"; when 80|81|82|83|84|85|86|87|88|89 => duan8<="1111111"; when 90|91|92|93|94|95|96|97|98|99 => duan8<="1100111"; when others => duan8<=null;end case;if clk1000'event and clk1000='1' then guan:=guan+1;if guan=8 then guan:=0;end if ;end if;case guan iswhen 0 =>duan<=duan1;when 1 =>duan<=duan2;when 2 =>duan<=duan3;when 3 =>duan<=duan4;when 4 =>duan<=duan5;when 5 =>duan<=duan6;when 6 =>duan<=duan7;when 7 =>duan<=duan8;when others =>duan<=null;end case;if shi='1' and clk1000='1' then s:=s+1;end if;if fen='1' and clk1000='1' then f:=f+1;end if;if miao='1' and clk1000='1' then m:=0; end if;if f=59 and (m=50 or m=52 or m=54 or m=56 or m=58) thenrang<=clk500;end if;if f=0 and m=0 thenrang<=clk1000;end if;end process;end one;---------------------------------------------------------------------------------------------- 顶层：library ieee;use ieee.std_logic_1164.all;entity ding isPort (clk:in std_logic;shi:in std_logic;fen:in std_logic;miao:in std_logic;duan7:out std_logic_vector(6 downto 0);wei3:out std_logic_vector(2 downto 0);rang1:out std_logic);end;architecture one of ding iscomponent duanport(clk1:in std_logic;clk500:in std_logic;clk1000:in std_logic;shi:in std_logic;fen:in std_logic;miao:in std_logic;duan:out std_logic_vector(6 downto 0);wei:out std_logic_vector(2 downto 0);rang:out std_logic);end component;component fpq1port(clk_in:in std_logic;clk_out:out std_logic);end component;component fpq500port(clk_in:in std_logic;clk_out:out std_logic);end component;component fpq1000port(clk_in:in std_logic;clk_out:out std_logic);end component;component weiport(clk1000 : in std_logic;q : buffer std_logic_vector(2 downto 0 ));end component;signal y1,y500,y1000:std_logic;beginu1:fpq1 port map(clk_in=>clk,clk_out=>y1);u2:fpq500 port map(clk_in=>clk,clk_out=>y500);u3:fpq1000 port map(clk_in=>clk,clk_out=>y1000);u4:duan port map(clk1=>y1,clk500=>y500,clk1000=>y1000,duan=>duan7,rang=>rang1,shi=>shi,fen=>fen,miao=>miao);u5:wei port map(clk1000=>y1000,q=>wei3);end ;。

EDA数字时钟源代码设计核准通过，归档资料。

未经允许，请勿外传～module tim(clk,modkey,key1,key2,dis,leg,line,row);input clk;//输入的频率20MHz input modkey,key1,key2;//输入的三个按键output [7:0]dis,leg;//打印输出output [7:0]line,row;//闹钟相应输出wire f1;//1Hz的频率wire f100;//0.01Hz的频率wire fs;//刷新频率1kHzwire [1:0]mkoo;//状态键控制四种状态//1.正常计时(00)//2.跑表(01)//3.调时(10)//4.闹钟(11)wire [3:0]a,b,c,d,e,f; //正常计时的输出秒.分.时//a:秒的低位//b:秒的高位//c:分的低位//d:分的高位//e:时的低位//f:时的低位 wire [3:0]a2,b2,c2,d2,e2,f2;//跑表的输出秒.分.时//a2:秒的低位//b2:秒的高位//c2:分的低位//d2:分的高位//e2:时的低位//f2:时的低位wire [3:0]cc,dd,ee,ff;//闹钟的输出分.时//cc:分的低位//dd:分的高位//ee:时的低位//ff:时的低位wire [7:0]leg1,dis1;//正常计时的打印输出wire [7:0]leg2,dis2;//跑表的打印输出wire [7:0]leg3,dis3; //闹钟的打印输出(LED显示)wire [1:0]k1;//调时时启动闪烁状态wire [1:0]kk1;//调闹钟时启动闪烁状态wire linerow;// 闹钟的打印输出(矩阵显示)zhuangtai(modkey,fs,mkoo);//判断键的状态模块(mkoo4种模式)正常计时.跑表.调时，闹钟modchose mc(leg1,dis1,leg2,dis2,leg3,dis3,fs,mkoo,leg,dis);//选择模式输出模块fenpin fen(clk,f1,f100,fs); //分频:秒表，跑表，刷新3个频率。

部件一：60进制程序LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY CLOCK60 ISPORT( CLK: IN STD_LOGIC; ---时钟信号NRESET: IN STD_LOGIC; ---复位端LOAD: IN STD_LOGIC; ---置数端D: IN STD_LOGIC_VECTOR(7 DOWNTO 0); ---输入端CI:IN STD_LOGIC; ---始能端CO: OUT STD_LOGIC; ---进位脉冲QH: BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0);QL: BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0));END CLOCK60;ARCHITECTURE ARTCLOCK60 OF CLOCK60 ISBEGINCO<='1'WHEN(QH="0101" AND QL="1001" AND CI='1')ELSE'0';----进位输出PROCESS(CLK,NRESET)BEGINIF(NRESET='0')THEN -----异步复位QH<="0000";QL<="0000";ELSIF(CLK'EVENT AND CLK='1')THEN------同步置数IF(LOAD='1')THENQH<=D(7 DOWNTO 4);QL<=D(3 DOWNTO 0);ELSIF(CI='1')THENIF(QL=9)THENQL<="0000";IF(QH=5)THENQH<="0000";ELSEQH<=QH+1;END IF;ELSEQL<=QL+1;END IF;END IF;END IF;END PROCESS;END ARTCLOCK60;60进制波形图如下：部件二：24进制程序LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY CLOCK24 ISPORT( CLK: IN STD_LOGIC; ---时钟信号NRESET: IN STD_LOGIC; ---复位端LOAD: IN STD_LOGIC; ---置数端D: IN STD_LOGIC_VECTOR(7 DOWNTO 0); ---输入端CI:IN STD_LOGIC; ---始能端CO: OUT STD_LOGIC; ---进位脉冲QH: BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0);QL: BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0));END CLOCK24;ARCHITECTURE ARTCLOCK24 OF CLOCK24 ISBEGINCO<='1'WHEN(QH="0101" AND QL="1001" AND CI='1')ELSE'0';----进位输出PROCESS(CLK,NRESET)BEGINIF(NRESET='0')THEN -----异步复位QH<="0000";QL<="0000";ELSIF(CLK'EVENT AND CLK='1')THEN------同步置数IF(LOAD='1')THENQH<=D(7 DOWNTO 4);QL<=D(3 DOWNTO 0);ELSIF(CI='1')THENIF(QL=9 or (QH=2 AND QL=3))THENQL<="0000";IF(QH=2)THENQH<="0000";ELSEQH<=QH+1;END IF;ELSEQL<=QL+1;END IF;END IF;END IF;END PROCESS;END ARTCLOCK24;24进制的波形图如下：数字钟的全部程序如下：LIBRARY IEEE; ---秒信号USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY CLOCK60s ISPORT( CLK: IN STD_LOGIC; ---时钟信号NRESET: IN STD_LOGIC; ---复位端LOAD: IN STD_LOGIC; ---置数端D: IN STD_LOGIC_VECTOR(7 DOWNTO 0); ---输入端CI:IN STD_LOGIC; ---始能端CO: OUT STD_LOGIC; ---进位脉冲QH: BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0);QL: BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0));END CLOCK60s;ARCHITECTURE ARTCLOCK60s OF CLOCK60s ISBEGINCO<='1'WHEN(QH="0101" AND QL="1001" AND CI='1')ELSE'0'; --进位输出PROCESS(CLK,NRESET)BEGINIF(NRESET='0')THEN ---异步复位QH<="0000";QL<="0000";ELSIF(CLK'EVENT AND CLK='1')THEN --同步置数IF(LOAD='1')THENQH<=D(7 DOWNTO 4);QL<=D(3 DOWNTO 0);ELSIF(CI='1')THENIF(QL=9)THENQL<="0000";IF(QH=5)THENQH<="0000";ELSEQH<=QH+1;END IF;ELSEQL<=QL+1;END IF;END IF;END IF;END PROCESS;END ARTCLOCK60s;LIBRARY IEEE; ---分信号USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY CLOCK60m ISPORT( CLK: IN STD_LOGIC; ---时钟信号NRESET: IN STD_LOGIC; ---复位端LOAD: IN STD_LOGIC; ---置数端D: IN STD_LOGIC_VECTOR(7 DOWNTO 0); ---输入端CI:IN STD_LOGIC; ---始能端CO: OUT STD_LOGIC; ---进位脉冲QH: BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0);QL: BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0));END CLOCK60m;ARCHITECTURE ARTCLOCK60m OF CLOCK60m ISBEGINCO<='1'WHEN(QH="0101" AND QL="1001" AND CI='1')ELSE'0'; --进位输出PROCESS(CLK,NRESET)BEGINIF(NRESET='0')THEN --异步复位QH<="0000";QL<="0000";ELSIF(CLK'EVENT AND CLK='1')THEN ---同步置数IF(LOAD='1')THENQH<=D(7 DOWNTO 4);QL<=D(3 DOWNTO 0);ELSIF(CI='1')THENIF(QL=9)THENQL<="0000";IF(QH=5)THENQH<="0000";ELSEEND IF;ELSEQL<=QL+1;END IF;END IF;END IF;END PROCESS;END ARTCLOCK60m;LIBRARY IEEE; ---时信号USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY CLOCK24 ISPORT( CLK: IN STD_LOGIC; ---时钟信号NRESET: IN STD_LOGIC; ---复位端LOAD: IN STD_LOGIC; ---置数端D: IN STD_LOGIC_VECTOR(7 DOWNTO 0); ---输入端CI:IN STD_LOGIC; ---始能端CO: OUT STD_LOGIC; --进位脉冲QH: BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0);QL: BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0));END CLOCK24;ARCHITECTURE ARTCLOCK24 OF CLOCK24 ISBEGINCO<='1'WHEN(QH="0101" AND QL="1001" AND CI='1')ELSE'0'; ---进位输出PROCESS(CLK,NRESET)BEGINIF(NRESET='0')THEN ---异步复位QH<="0000";QL<="0000";ELSIF(CLK'EVENT AND CLK='1')THEN ---同步置数IF(LOAD='1')THENQH<=D(7 DOWNTO 4);QL<=D(3 DOWNTO 0);ELSIF(CI='1')THENIF(QL=9 or (QH=2 AND QL=3))THENQL<="0000";IF(QH=2)THENQH<="0000";ELSEQH<=QH+1;END IF;ELSEEND IF;END IF;END IF;END PROCESS;END ARTCLOCK24;LIBRARY IEEE; ---时信号USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY hour ISPORT( CLK: IN STD_LOGIC; ---时钟信号NRESETS: IN STD_LOGIC; ---复位端LOADS: IN STD_LOGIC; ---置数端NRESETM: IN STD_LOGIC; ---复位端LOADM: IN STD_LOGIC; ---置数端NRESETH: IN STD_LOGIC; ---复位端LOADH: IN STD_LOGIC; ---置数端DS: IN STD_LOGIC_VECTOR(7 DOWNTO 0); ---输入端DM: IN STD_LOGIC_VECTOR(7 DOWNTO 0); ---输入端DH: IN STD_LOGIC_VECTOR(7 DOWNTO 0); ---输入端CI:IN STD_LOGIC; ---始能端CO: OUT STD_LOGIC; ---进位脉冲QH1: BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0);QL1: BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0);QH2: BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0);QL2: BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0);QH3: BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0);QL3: BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0));END hour;ARCHITECTURE ART OF hour ISCOMPONENT CLOCK60SPORT( CLK: IN STD_LOGIC; ---时钟信号NRESET: IN STD_LOGIC; ---复位端LOAD: IN STD_LOGIC; ---置数端D: IN STD_LOGIC_VECTOR(7 DOWNTO 0); ---输入端CI:IN STD_LOGIC; ---始能端CO: OUT STD_LOGIC; ---进位脉冲QH: BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0);QL: BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0));END COMPONENT;COMPONENT CLOCK60MPORT( CLK: IN STD_LOGIC; ---时钟信号NRESET: IN STD_LOGIC; ---复位端LOAD: IN STD_LOGIC; ---置数端D: IN STD_LOGIC_VECTOR(7 DOWNTO 0); ---输入端CI:IN STD_LOGIC; ---始能端CO: OUT STD_LOGIC; ---进位脉冲QH: BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0);QL: BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0));END COMPONENT;COMPONENT CLOCK24PORT( CLK: IN STD_LOGIC; ---时钟信号NRESET: IN STD_LOGIC; ---复位端LOAD: IN STD_LOGIC; ---置数端D: IN STD_LOGIC_VECTOR(7 DOWNTO 0); ---输入端CI:IN STD_LOGIC; --始能端CO: OUT STD_LOGIC; ---进位脉冲QH: BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0);QL: BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0));END COMPONENT;SIGNAL Z1,Z2:STD_LOGIC;BEGINU1: CLOCK60S PORT MAP(CLK,NRESETS,LOADS,DS,CI,Z1,QH1,QL1);U2: CLOCK60M PORT MAP(CLK,NRESETM,LOADM,DM,Z1,Z2,QH2,QL2);U3: CLOCK24 PORT MAP(CLK,NRESETH,LOADH,DH,Z2,CO,QH3,QL3);END ARCHITECTURE ART;电子钟全部引脚显示波形：00：00：59波形显示如下：00：59：59波形图如下，进位后为01：00：00 23:59:59波形图如下：调时间波形如下：用置位端进行调时，调到02：51：15波形如下：经验证，以上设计完全符合题目要求！。

多功能数字时钟设计说明:1．系统顶层框图:各模块电路功能如下:1.秒计数器、分计数器、时计数器组成最基本的数字钟,其计数输出送7段译码电路由数码管显示.2.基准频率分频器可分频出标准的1HZ频率信号,用于秒计数的时钟信号;分频出4HZ频率信号,用于校时、校分的快速递增信号;分频出64HZ频率信号,用于对按动“校时”,“校分”按键的消除抖动.2.多功能数字钟结构框图:一、系统功能概述已完成功能1.完成时／分／秒的依次显示并正确计数,利用六位数码管显示;2.时／分／秒各段个位满10正确进位,秒／分能做到满60向前进位,有系统时间清零功能;3.定时器:实现整点报时,通过扬声器发出高低报时声音;4.时间设置,也就是手动调时功能:当认为时钟不准确时,可以分别对分／时钟进行调整;5.闹钟:实现分/时闹钟设置,在时钟到达设定时间时通过扬声器响铃.有静音模式.待改进功能:1. 系统没有万年历功能,正在思考设计方法.2. 应添加秒表功能.二、系统组成以及系统各部分的设计1.时计数模块时计数模块就是一个2位10进制计数器,记数到23清零.VHDL的RTL描述如下:----cnt_h.vhdlibrary ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity cnt_h isport(en,clk,clr:in std_logic;dout:out std_logic_vector(7 downto 0);c:out std_logic);end cnt_h;architecture rtl of cnt_h issignal t:std_logic_vector(7 downto 0);beginprocess(en,clk,clr)variable t:std_logic_vector(7 downto 0);beginif en='1' then --异步使能if clk 'event and clk='1' thent:=t+1;if t(3 downto 0)=X"A" then --个位等于10则十位加1t(7 downto 4):=t(7 downto 4)+1;t(3 downto 0):=X"0"; --个位清零end if;if t>X"23" then --大于23清零t:=X"00";end if;end if;if clr='1' then --异步清零t:=X"00";end if;end if;dout<=t;end process;end rtl;时计数器模块仿真波形如下从仿真波形可知,当计数到23时,下一个时钟上升沿到来时就清零了,符合设计要求.时计数模块框图如下2.分及秒计数模块分及秒计数模块也是一个2位10进制计数器,记数到59清零.VHDL的RTL描述如下:library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity cnt_s isport(en,clk,clr:in std_logic;dout:buffer std_logic_vector(7 downto 0);c:out std_logic);end cnt_s;architecture rtl of cnt_s isbeginprocess(en,clk,clr)beginif en='1' thenif clr='1' then --异步清零dout<=X"00";elsif clk 'event and clk='1' thenif dout(3 downto 0)<9 thendout(3 downto 0)<=dout(3 downto 0)+1;c<='0';elsif dout(7 downto 4)<5 thendout(3 downto 0)<=X"0";dout(7 downto 4)<=dout(7 downto 4)+1;elsedout<=X"00";c<='1';end if;end if;else dout<="ZZZZZZZZ";end if;end process;end rtl;分和秒计数器模块仿真波形如下从仿真波形可知,当计数到59时,下一个时钟上升沿到来时就清零了,并且产生进位信号,符合设计要求.分和秒计数模块框图如下3.按键消抖动模块按键消抖动有很多方案,这里选择的是计数消抖,即只当有效电平到来后开始计数,当计数值大于一定值后再输出该有效电平,否则不输出,从而达到消抖目的. VHDL的RTL描述如下:library ieee;use ieee.std_logic_1164.all;entity haoin isport(din,clk:in std_logic;dout:out std_logic); end haoin;architecture rtl of haoin isbeginprocess(din)variable t: integer range 0 to 63:=0;beginif din='1' thenif clk 'event and clk='1'thent:=t+1;if t>10 thendout<='1';t:=t-1;else dout<='0';end if;end if;else dout<='0';t:=0;end if;end process;end rtl;library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity ring isport(clk: in std_logic;clk500: in std_logic;clk1k:in std_logic;beep:out std_logic);end ring;architecture rtl of ring isbeginprocess(clk)variable t: std_logic;variable n: integer range 0 to 15:=0;beginif clk 'event and clk='1' thent:=not t;n:=n+1;end if;if t='1' and n<11 thenbeep<=clk500;elsif n=11 thenbeep<=clk1k;else beep<='Z';end if;end process;end rtl;library IEEE;use IEEE.std_logic_1164.all;use IEEE.std_logic_arith.all;use IEEE.std_logic_unsigned.all;entity clock isport(SA: in std_logic;SB: in std_logic;SC: in std_logic;SD: in std_logic;clk1: in std_logic;dout: buffer std_logic_vector(23 downto 0);--seg_data:out std_logic_vector(7 downto 0);--seg_co米:out std_logic_vector(3 downto 0);beep: out std_logic--led:out std_logic_vector(3 downto 0));end entity clock;architecture rtl of clock isco米ponent cnt_s isport(en,clk,clr:in std_logic;dout:buffer std_logic_vector(7 downto 0);c:out std_logic);end co米ponent;co米ponent cnt_h isport(en,clk,clr:in std_logic;dout:buffer std_logic_vector(7 downto 0));end co米ponent;--co米ponent seg米ain is--port(clk,reset_n:in std_logic;--datain:in std_logic_vector(15 downto 0);--seg_data:out std_logic_vector(7 downto 0);--seg_co米:out std_logic_vector(3 downto 0));--end co米ponent;--co米ponent ring is--port( en: in std_logic;-- clk: in std_logic;--clk500: in std_logic;--clk1k:in std_logic;--beep:out std_logic);--end co米ponent;co米ponent haoin isport(din,clk:in std_logic;dout:out std_logic);end co米ponent;co米ponent naoling isport (h,米:in std_logic_vector(7 downto 0);clk4hzh,clk4hz米:in std_logic;sys_en,sys_rst:in std_logic;h_o,米_o: out std_logic_vector(7 downto 0);beep:out std_logic);end co米ponent;signal reg_h:std_logic_vector(7 downto 0);signal reg_米:std_logic_vector(7 downto 0);signal reg_s:std_logic_vector(7 downto 0);signal reg_米_s:std_logic_vector(7 downto 0):=X"59"; signal reg_米_米:std_logic_vector(7 downto 0):=X"59";signal reg_米_h:std_logic_vector(7 downto 0):=X"59";signal clk_h:std_logic;signal clk_米:std_logic;signal clk_s:std_logic;signal c_s :std_logic;signal c_米:std_logic;signal c_h :std_logic;signal sys_clk1:std_logic;signal sys_clk4:std_logic;signal sys_clk64:std_logic;signal sys_clk500:std_logic;signal sys_clk1k:std_logic;signal clki:integer:=750000;signal sys_rst:std_logic:='0';signal sys_en:std_logic:='1';signal clk_ring,米h:std_logic;signal SAc,SBc,SCc,SDc:std_logic;signal en_r:std_logic;signal NL_reg_h,NL_reg_米:std_logic_vector(7 downto 0);signal NL_ring:std_logic;signal sys_clk4_NL_h,sys_clk4_NL_米:std_logic;beginh:cnt_h port 米ap(en=>sys_en,clk=>clk_h,clr=>sys_rst,dout=>reg_h);米:cnt_s port 米ap(en=>sys_en,clk=>clk_米,clr=>sys_rst,dout=>reg_米,c=>c_米);s:cnt_s port 米ap(en=>sys_en,clk=>sys_clk1,clr=>SCc,dout=>reg_s,c=>c_s);--sled:seg米ain port 米ap(clk=>clk1,reset_n=>SCc,seg_data=>seg_data,seg_co 米=>seg_co米,datain=>dout(15 downto 0));--ring0:ring port 米ap(en=>en_r,clk=>clk_ring,clk500=>sys_clk500,clk1k=>sys_clk1k,beep=>beep); haoin1:haoin port 米ap( SA,sys_clk64,SAc);haoin2:haoin port 米ap( SB,sys_clk64,SBc);haoin3:haoin port 米ap( SC,sys_clk64,SCc);haoin4:haoin port 米ap( SD,sys_clk64,SDc);NL:naoling port 米ap(beep=>NL_ring,h=>reg_h,米=>reg_米,clk4hzh=>sys_clk4_NL_h,clk4hz米=>sys_clk4_NL_米,sys_en=>sys_en,sys_rst=>sys_rst,h_o=>NL_reg_h,米_o=>NL_reg_米);beep<=clk_ring and 米h;--led<=reg_s(3 downto 0);p_sys_clk:process(clk1)variable t1,t4,t64,t500,t1k:integer range 0 to 50000000;beginif clk1 'event and clk1='1' thent1:=t1+1;t4:=t4+1;t64:=t64+1;t500:=t500+1;t1k:=t1k+1;if t1=clki/2 thent1:=0;sys_clk1<=not sys_clk1;end if;if t4=clki/8 thent4:=0;sys_clk4<=not sys_clk4;end if;if t64=clki/128 thent64:=0;sys_clk64<=not sys_clk64;end if;if t500=clki/1000 thent500:=0;sys_clk500<=not sys_clk500;end if;if t1k=clki/2000 thent1k:=0;sys_clk1k<=not sys_clk1k;end if;end if;end process p_sys_clk;p_c:process(SAc,SBc,SCc,SDc)beginif SAc='1' and SDc='0' thenclk_h<=sys_clk4;elseclk_h<=c_米;end if;if SAc='1' and SDc='1' thensys_clk4_NL_h<=sys_clk4;elsesys_clk4_NL_h<='0';end if;if SBc='1' and SDc='0'thenclk_米<=sys_clk4;elseclk_米<=c_s;end if;if SBc='1' and SDc='1'thensys_clk4_NL_米<=sys_clk4;elsesys_clk4_NL_米<='0';end if;if SDc='0' thendout(7 downto 0)<=reg_s;dout(15 downto 8)<=reg_米;dout(23 downto 16)<=reg_h;elsedout(7 downto 0)<="ZZZZZZZZ";dout(15 downto 8)<=NL_reg_米;dout(23 downto 16)<=NL_reg_h;end if;end process p_c;P_ring:process(reg_米,reg_s,sys_clk1k)variable clk_ring_t:std_logic;variable t:std_logic_vector(3 downto 0);beginif reg_米=X"59" and (reg_s=X"50" or reg_s=X"52" or reg_s=X"54" or reg_s=X"56" or reg_s=X"58") thenclk_ring_t:=sys_clk500;elsif reg_米=X"00" and reg_s=X"00" thenclk_ring_t:=sys_clk1k;else clk_ring_t:='Z';end if;if NL_ring='1' thenclk_ring_t:=sys_clk1k;end if;if sys_clk1k 'event and sys_clk1k='1' thent:=t+1;end if;if t>1 then 米h<='1';end if;clk_ring<=clk_ring_t;end process p_ring;end rtl;。

由于要实现快速调时，所以这就要求在“计数”时用一个时钟频率，在“较时”时有需要一个频率，这就会出现一个问题，那就是：一个进程（即process）中，不能出现两个时钟，否则就会出现error（100028）……，所以如果“较时”和“计数”在一个process时，就需要避免在一个进程中采用两个时钟输入（即将两个时钟频率作为敏感信号），所以这也就是这里需要解决的问题了，考虑到计数和调时不是同时进行的，因此可以考虑在一个进程中，采用一个时钟输入进行类似于分时复用的原理，即计数时clk信号输出计数频率，校时时输出计数频率频率。

而在设计时由于采用了EN信号进行计数和校时的切换（即EN为1时计数，为0时校时），因此可以利用EN信号作为时钟分频模块（即下图中的CLK_TWO 模块）中的CLK_low输出的高低频切换。

具体程序如下（主要看一下CLK_TWO 模块中的红色程序部分即能明白）。

顶层原理图CLK_TWO模块程序LIBRARY ieee;USE ieee.std_logic_1164.all;USE ieee.std_logic_unsigned.all;ENTITY CLK_TWO ISPORT(CLK,CHAG: IN STD_LOGIC ;CLK_low,CLK_high : OUT STD_LOGIC);END CLK_TWO;ARCHITECTURE BEHAV OF CLK_TWO ISBEGINPROCESS(CLK,CHAG)VARIABLE A,B :INTEGER := 0;VARIABLE H,L :STD_LOGIC ;BEGINIF CLK'EVENT AND CLK='1' THENIF A<10000THEN A :=A+1;IF A<5000 THEN H :='0';ELSE H :='1';END IF;ELSE A :=0;END IF;if CHAG ='1' thenIF B< THEN B :=B+1;------24MHz分频为1Hz用于计数IF B<1200000 THEN L :='0';ELSE L :='1';END IF;ELSE B :=0;END IF;elseIF B<5000000 THEN B :=B+1;-----------24MHz分频，分频比为5 000 000。

EDA 时钟一、程序代码(Verilog)module jishi(clk1,clk2,a,b,k0,k1,k2,k3,k4,k5,k6);input clk1;//1HZinput clk2;//100KHZinput k0,k1,k2,k3,k4,k5,k6;output[7:0] a;output[7:0] b;reg[7:0] a;reg[7:0] b;reg[3:0] secL;reg[2:0] secH;reg[3:0] minL;reg[2:0] minH;reg[3:0] houL;reg[1:0] houH;reg[3:0] segsel;reg[2:0] count;reg[3:0] x;reg[8:0] delay;always@(posedge clk1)begin//24小时计数器if(k0==0)beginsecL<=secL+1'b1;if(secL==4'b1001)beginsecL<=4'b0;secH<=secH+1'b1;if(secH==3'b101)beginsecH<=3'b0;minL<=minL+1'b1;if(minL==4'b1001)beginminL<=4'b0;minH<=minH+1'b1;if(minH==3'b101)beginminH<=3'b0;houL<=houL+1'b1;if(houL==4'b1001)beginhouL<=4'b0;houH<=houH+1'b1;endendendendendelse if(houH==2'b10)beginif(houL==4'b0100)beginhouL<=4'b0;houH<=2'b0;endendendx=4'b1010;if(k0==1)begin//调秒if(k1==1)//++beginsecL<=secL+1'b1;if(secL==4'b1001)beginsecL<=4'b0;secH<=secH+1'b1;if(secH==3'b101)beginsecH<=3'b0;endendendif(k2==1)//--beginsecL<=secL-1'b1;if(secL==4'b0)beginsecL<=4'b1001;secH<=secH-1'b1;beginsecH<=3'b101;endendend//调分if(k3==1)//++beginminL<=minL+1'b1;if(minL==4'b1001)beginminL<=4'b0;minH<=minH+1'b1;if(minH==3'b101)beginminH<=3'b0;endendendif(k4==1)//--beginminL<=minL-1'b1;if(minL==4'b0)beginminL<=4'b1001;minH<=minH-1'b1;if(minH==3'b0)beginminH<=3'b101;endendend//调时if(k5==1)//++beginhouL<=houL+1'b1;if(houL==4'b1001)beginhouL<=4'b0;houH<=houH+1'b1;endbeginif(houL==4'b0100)beginhouL<=4'b0;houH<=2'b0;endendendif(k6==1)//--beginhouL<=houL-1'b1;if(houL==4'b0)beginhouL<=4'b1001;houH<=houH-1'b1;endelse if(houH==2'b0)beginif(houL==4'b0)beginhouL<=4'b0011;houH<=2'b01;endendendendendalways@(posedge clk2)begincount<=count+1'b1;delay<=delay+1'b1;case(count)3'b000:begin a=8'b00000001;segsel=houH; end 3'b001:begin a=8'b00000010;segsel=houL; end3'b010:begin a=8'b00000100;segsel=x; end3'b011:begin a=8'b00001000;segsel=minH; end 3'b100:begin a=8'b00010000;segsel=minL; end3'b101:begin a=8'b00100000;segsel=x; end3'b110:begin a=8'b01000000;segsel=secH; end3'b111:begin a=8'b10000000;segsel=secL; endendcasecase(segsel)//循环显示4'b0000:b=8'b00111111;4'b0001:b=8'b00000110;4'b0010:b=8'b01011011;4'b0011:b=8'b01001111;4'b0100:b=8'b01100110;4'b0101:b=8'b01101101;4'b0110:b=8'b01111101;4'b0111:b=8'b00000111;4'b1000:b=8'b01111111;4'b1001:b=8'b01101111;4'b1010:b=8'b01000000;endcaseendendmodule二、仿真结果：三、硬件结果：。

--------------------------------------- Title:多功能数字钟---- Author:Pan hongtao ---- Data: 2006-10-1 ---------------------------------------library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;--------------------------------------------------------------------entity digital isport( Clk : in std_logic; --时钟输入Rst : in std_logic; --复位输入S1,S2 : in std_logic; --时间调节输入led : out std_logic_vector(3 downto 0); --整点输报时输出spk : out std_logic;Display : out std_logic_vector(7 downto 0); --八段码管显示输出SEG_SEL : buffer std_logic_vector(2 downto 0) –八段码管扫描驱动);end digital;--------------------------------------------------------------------architecture behave of digital issignal Disp_Temp : integer range 0 to 15; -- 定义整数signal Disp_Decode : std_logic_vector( 7 downto 0);signal SEC1,SEC10 : integer range 0 to 9;signal MIN1,MIN10 : integer range 0 to 9;signal HOUR1,HOUR10 : integer range 0 to 9;signal clk1khz : std_logic;--数码管扫描时钟signal clk1hz : std_logic;--时钟计时时钟signal led_count : std_logic_vector(2 downto 0);signal led_display : std_logic_vector(3 downto 0);signal spkcout : std_logic;beginPROCESS(clk) --产生1hz信号variable cnt : INTEGER RANGE 0 TO 19999999; --产生1Hz时钟的分频计数器BEGINIF clk='1' AND clk'event THENIF cnt=19999999 THEN cnt:=0;ELSEIF cnt<10000000 THEN clk1hz<='1';ELSE clk1hz<='0';END IF;cnt:=cnt+1;END IF;END IF;end process;PROCESS(clk) --产生1khz信号variable cnt1 : INTEGER RANGE 0 TO 19999; --产生1KHz时钟的分频计数器BEGINIF clk='1' AND clk'event THENIF cnt1=19999 THEN cnt1:=0;ELSEIF cnt1<10000 THEN clk1khz<='1';ELSE clk1khz<='0';END IF;cnt1:=cnt1+1;END IF;END IF;end process;process(Clk1Hz,Rst)beginif(Rst='0') then --系统复位SEC1<='0';SEC10<='0';MIN1<='0';MIN10<='0';HOUR1<='0';HOUR10<='0';elsif(Clk1Hz'event and Clk1Hz='1') then --正常运行if(S1='0') then --调节小时if(HOUR1='9') thenHOUR1<='0'; --个位HOUR10<=HOUR10+1; --十位elsif(HOUR10='2' and HOUR1='3') then –在23时HOUR1<='0';HOUR10<='0';elseHOUR1<=HOUR1+1;end if;elsif(S2='0') then --调节分钟if(MIN1='9') thenMIN1<='0';if(MIN10='5') thenMIN10<='0';elseMIN10<=MIN10+1;end if;elseMIN1<=MIN1+1;end if;elsif(SEC1='9') thenSEC1<='0';if(SEC10='5') thenSEC10<='0';if(MIN1='9') thenMIN1<='0';if(MIN10='5') thenMIN10<='0';if(HOUR1='9') thenHOUR1<='0';HOUR10<=HOUR10+1;elsif(HOUR10='2' and HOUR1='3') thenHOUR1<='0';HOUR10<='0';elseHOUR1<=HOUR1+1;end if;elseMIN10<=MIN10+1;end if;elseMIN1<=MIN1+1;end if;elseSEC10<=SEC10+1;end if;elseSEC1<=SEC1+1;end if;end if;end process;process(Clk)--整点报时beginif(Clk1hz'event and Clk1hz='1') thenif(MIN10='5' and MIN1='9' and SEC10='5' and SEC1='5') then --在59分55秒开始提示led_Count<=led_Count+1; spkcout<=not spkcout;elseled_count<="000";spkcout<='0';end if;spk<=spkcout;end if;end process;process(led_count)--整点报时LED灯的闪烁begincase (led_count) iswhen "000"=>led_display<="0000";when "001"=>led_display<="1111";when "010"=>led_display<="0111";when "011"=>led_display<="0011";when "100"=>led_display<="0001";when "101"=>led_display<="1111";when others=>led_display<="0000";end case;led<=led_display;end process;process(SEG_SEL)begincase (SEG_SEL+1) iswhen "111"=>Disp_Temp<=HOUR10;when "110"=>Disp_Temp<=HOUR1;when "101"=>Disp_Temp<=10;when "100"=>Disp_Temp<=MIN10;when "011"=>Disp_Temp<=MIN1;when "010"=>Disp_Temp<=10;when "001"=>Disp_Temp<=SEC10;when "000"=>Disp_Temp<=SEC1;end case;end process;process(Clk1khz)beginif(Clk1khz'event and Clk1khz='1') then --扫描累加SEG_SEL<=SEG_SEL+1;Display<=Disp_Decode;end if;end process;process(Disp_Temp) --显示转换begincase Disp_Temp iswhen '0'=>Disp_Decode<="00111111"; --0when '1'=>Disp_Decode<="00000110"; --1when '2'=>Disp_Decode<="01011011"; --2when '3'=>Disp_Decode<="01001111"; --3when '4'=>Disp_Decode<="01100110"; --4when '5'=>Disp_Decode<="01101101"; --5when '6'=>Disp_Decode<="01111101"; --6when '7'=>Disp_Decode<="00000111"; --7when '8'=>Disp_Decode<="01111111"; --8when '9'=>Disp_Decode<="01101111"; --9when others=>Disp_Decode<="00000000"; --全灭end case;end process;end behave;。

EDA实验报告Clock设计姓名：专业：电子信息科学与技术班级：10级1 班学号：1001050903信息科学与工程学院电子信息系2012 年7 月3 日一、实验目的通过本次实验设计，提高学生Verilog语言编写能力，加深对Quartus ΙΙ、modelsim等仿真软件的了解并进一步熟悉和使用。

二、实验要求1.设计一个时钟，具有显示时、分的功能；2.时钟有暂停、复位等功能。

三、实验内容1.clock程序代码module clock(clk,seg,reset,cin,ocom,count);output[3:0] ocom;output[7:0] seg;output count;input cin,clk,reset;reg [7:0] out_s;reg[7:0] out_min;reg[7:0] seg;reg[3:0] ocom;reg[3:0] display;reg clk_m,clk_n;reg[1:0] select;reg count;integer count_clk,count_cp;always @(posedge clk)if (count_cp == 50000)begincount_cp = 0;clk_n = ~clk_n;endelsecount_cp = count_cp + 1;always @(posedge clk)if (count_clk == 25000000)begincount_clk = 0;clk_m = ~clk_m;endelsecount_clk = count_clk + 1;always @(posedge clk_n)select=select + 1;always @(select)begincase(select)2'b00 : begin ocom[3:0]=4'b1110;display = out_s[3:0]; end2'b01 : begin ocom[3:0]=4'b1101;display = out_s[7:4]; end2'b10 : begin ocom[3:0]=4'b1011;display = out_min[3:0]; end2'b11 : begin ocom[3:0]=4'b0111;display = out_min[7:4]; end endcaseendalways @(posedge clk_m)beginif(!reset)out_s <= 0;else if(cin)beginif(out_s[3:0]==9)beginout_s[3:0] <= 0;if(out_s[7:4]==5)out_s[7:4] <= 0;elseout_s[7:4] <= out_s[7:4]+1;endelseout_s[3:0] <= out_s[3:0]+1;endendalways @(out_s)if ((out_s == 8'h59) & cin)count = 1;else#1 count = 0;always @(posedge clk_m)beginif(!reset)out_min <= 0;else if(count)if(out_min[3:0]==9)beginout_min[3:0] <= 0;if(out_min[7:4]==5)out_min[7:4] <= 0;elseout_min[7:4] <= out_min[7:4]+1;endelseout_min[3:0] = out_min[3:0] + 1;endalways @(display)begincase(display)4'b0000 : seg[7:0]=8'b10010000;4'b0001 : seg[7:0]=8'b10011111;4'b0010 : seg[7:0]=8'b01011000;4'b0011 : seg[7:0]=8'b00011001;4'b0100 : seg[7:0]=8'b00010111;4'b0101 : seg[7:0]=8'b00110001;4'b0110 : seg[7:0]=8'b00110000;4'b0111 : seg[7:0]=8'b10011101;4'b1000 : seg[7:0]=8'b00010000;4'b1001 : seg[7:0]=8'b00010001;default : seg[7:0]=8'b11111111;endcaseendendmodule2.测试代码`timescale 1ns/1nsmodule clock_test;wire [3:0] ocom;wire [7:0] seg;wire count;reg cin,clk,reset;always #10 clk=~clk;initialbeginclk=0;cin=1;reset=0;#42reset=1;#100000 $stop;endclock m(.ocom(ocom),.seg(seg),.count(count),.cin(cin),.clk(clk),.reset(reset)); endmodule3.引脚绑定4.程序下载1.Quartus编译2.modelsim仿真五．实验总结这次课程设计让同学们懂得了Verilog语言的重要性，没有好的理论基础就不可能有实践的正确性。

module zonghe (clkl,clkh,reset,q,w,p,kr,kc,a,b,c,d,e,f,g,sa,sb,sc,ds);input clkl,clkh,reset; //计数时钟脉冲、扫描频率脉冲与复位信号input q,w,p; //启动设置的控制信号、设置时间的控制信号及设置闹钟的控制信号inout [3:0]kr; //4*4键盘的行输入/输出信号inout [3:0]kc; //4*4键盘的列输入/输出信号output a,b,c,d,e,f,g,sa,sb,sc,ds; //LED的7个片选信号与3个位选信号rega,b,c,d,e,f,g,sa,sb,sc,ds;reg [3:0]kr,kc;reg [6:0] display ;reg [2:0] dcount,kcount;reg [3:0]keyr,keyc;reg kflag1,kflag2;reg [6:0] buff7 ;reg [3:0] shiwei1,gewei1,shiwei2,gewei2,shiwei3,gewei3;reg[5:0] hour,minute,second,Ahour,Aminute,Hour,Minute; //储存当前时间的时分秒、闹钟的时分及设置的时间的时分always@(posedgeclkh) //累加两个计数值begindcount<=dcount+1;kcount<=kcount+1;endalways @(posedgeclkh) //扫描键盘beginif(kcount==0)beginkr<=4'b1111;kc<=4'b0000;endelse if(kcount==1)beginkeyr<=kr;kr<=4'bZZZZ;endelse if(kcount==2)beginkr<=4'b0000;kc<=4'b1111;endelse if(kcount==3)beginkeyc<=kc;kc<=4'bZZZZ;endendalways@(posedgeclkh) //改变键的标志位beginif(kcount==4 &keyr==4'b1111)kflag1<=0;else if(kcount==4)kflag1<=1;kflag2<=kflag1;endalways@(posedgeclkh) // 获取相应按键按下的结果beginif(kcount==5)if(keyr==4'b1110)case (keyc)4'b1110:buff7<=7'b0111111; //在LED上显示04'b1101:buff7<=7'b0000110; //在LED上显示14'b1011:buff7<=7'b1011011; //在LED上显示24'b0111:buff7<=7'b1001111; //在LED上显示3default :buff7<=buff7; //无变化endcaseelse if (keyr==4'b1101)case (keyc)4'b1110:buff7<=7'b1100110; //在LED上显示44'b1101:buff7<=7'b1101101; //在LED上显示54'b1011:buff7<=7'b1111101; //在LED上显示64'b0111:buff7<=7'b0000111; //在LED上显示7default :buff7<=buff7; // 无变化endcaseelse if(keyr==4'b1011)case (keyc)4'b1110:buff7<=7'b1111111; // 在LED上显示84'b1101:buff7<=7'b1101111; // 在LED上显示94'b1011:buff7<=7'b1110111; //在LED上显示a4'b0111:buff7<=7'b1111100; //在LED上显示bdefault :buff7<=buff7; // 无变化endcaseelse if(keyr==4'b0111)case (keyc)4'b1110:buff7<=7'b0111001; //在LED上显示c4'b1101:buff7<=7'b1011110; //在LED上显示d4'b1011:buff7<=7'b1111001; //在LED上显示e4'b0111:buff7<=7'b1110001; // 在LED上显示fdefault:buff7<=buff7; //无变化endcaseendalways@(posedgeclkh) //显示过程beginsa<=dcount[0]; //将dcount赋给LED的三个片选信号sb<=dcount[1];sc<=dcount[2];shiwei1=hour/10;gewei1=hour%10;shiwei2=minute/10;gewei2=minute%10;shiwei3=second/10;gewei3=second%10;if(dcount==3'b111)//判断位选dcount的值，并将此位上的值输出到数码管case(shiwei1) //在第一数码管上显示时钟的十位4'b0000: display <= 7'b0111_111;4'b0001: display<= 7'b0000_110;4'b0010: display <= 7'b1011_011;4'b0011: display <= 7'b1001_111;4'b0100: display <= 7'b1100_110;4'b0101: display <= 7'b1101_101;4'b0110: display <= 7'b1111_101;4'b0111: display <= 7'b0000_111;4'b1000: display <= 7'b1111_111;4'b1001: display <= 7'b1101_111;default: display <= 7'b0000_000;endcaseif(dcount==3'b000) //在第二个数码管上显示时钟的个位case(gewei1)4'b0000: display <= 7'b0111_111;4'b0001: display <= 7'b0000_110;4'b0010: display <= 7'b1011_011;4'b0011: display <= 7'b1001_111;4'b0100: display <= 7'b1100_110;4'b0101: display <= 7'b1101_101;4'b0110: display <= 7'b1111_101;4'b0111: display <= 7'b0000_111;4'b1000: display <= 7'b1111_111;4'b1001: display <= 7'b1101_111;default: display <= 7'b0000_000;endcaseif(dcount==3'b001) //在第三个数码管上显示分钟的十位case(shiwei2)4'b0000: display <= 7'b0111_111;4'b0001: display <= 7'b0000_110;4'b0010: display <= 7'b1011_011;4'b0011: display <= 7'b1001_111;4'b0100: display <= 7'b1100_110;4'b0101: display <= 7'b1101_101;4'b0110: display <= 7'b1111_101;4'b0111: display <= 7'b0000_111;4'b1000: display <= 7'b1111_111;4'b1001: display <= 7'b1101_111;default: display <= 7'b0000_000;endcaseif(dcount==3'b010) //在第四个数码管上显示分钟的个位case(gewei2)4'b0000: display <= 7'b0111_111;4'b0001: display <= 7'b0000_110;4'b0010: display <= 7'b1011_011;4'b0011: display <= 7'b1001_111;4'b0100: display <= 7'b1100_110;4'b0101: display <= 7'b1101_101;4'b0110: display <= 7'b1111_101;4'b0111: display <= 7'b0000_111;4'b1000: display <= 7'b1111_111;4'b1001: display <= 7'b1101_111;default: display <= 7'b0000_000;endcaseif(dcount==3'b011) //在第五个数码管上显示秒钟的十位case(shiwei3)4'b0000: display <= 7'b0111_111;4'b0001: display <= 7'b0000_110;4'b0010: display <= 7'b1011_011;4'b0011: display <= 7'b1001_111;4'b0100: display <= 7'b1100_110;4'b0101: display <= 7'b1101_101;4'b0110: display <= 7'b1111_101;4'b0111: display <= 7'b0000_111;4'b1000: display <= 7'b1111_111;4'b1001: display <= 7'b1101_111;default: display <= 7'b0000_000;endcaseif(dcount==3'b100) //在第六个数码管上显示秒钟的个位case(gewei3)4'b0000: display <= 7'b0111_111;4'b0001: display <= 7'b0000_110;4'b0010: display <= 7'b1011_011;4'b0011: display <= 7'b1001_111;4'b0100: display <= 7'b1100_110;4'b0101: display <= 7'b1101_101;4'b0110: display <= 7'b1111_101;4'b0111: display <= 7'b0000_111;4'b1000: display <= 7'b1111_111;4'b1001: display <= 7'b1101_111;default: display <= 7'b0000_000;endcaseif(dcount==3'b101) display <=7'b1000_000; //在第七个数码管上显示“—”if(dcount==3'b110) display <=buff7; //在第八个数码管上显示按下的键值endalways @(posedgeclkh) //将display中存的值赋给LED的七个片选信号begina<=display[0];b<=display[1];c<=display[2];d<=display[3];e<=display[4];f<=display[5];g<=display[6];endalways@(posedgeclkl) //计时过程clkl的频率为1Hzbeginhour<=Hour;minute<=Minute; //将设置的时间（时、分）赋给hour和minute if(reset)begin hour<=0;minute<=0;second<=0;end //当reset为1时，将时间清零即为00：00：00else //正常计时if(second==59)if(minute==59)if(hour ==23)begin second<=0;minute<=0;hour<=0;endelse begin second<=0;minute<=0;hour<=hour+1;endelse begin second<=0;minute<=minute+1;endelse second<=second+1;endinteger i; //记录按键按下的次数reg [3:0]num1,num2,num3,num4; //储存按键的键值always @(posedgeclkh)//储存按下的键值beginif(q==1)//启动设置begini=0;if(keyc!=4'b1111) i=i+1; //当有键按下时，i自动加1if(i==1) //将第一个按下的按键值存入num1 begincase ({keyr,keyc})4'b1110_1110:num1=0;4'b1110_1101:num1=1;4'b1110_1011:num1=2;4'b1110_0111:num1=3;4'b1101_1110:num1=4;4'b1101_1101:num1=5;4'b1101_1011:num1=6;4'b1101_0111:num1=7;4'b1011_1110:num1=8;4'b1011_1101:num1=9;default:num1=num1;endcaseendif(i==2) //将第二个按下的按键值存入num2 begincase ({keyr,keyc})4'b1110_1110:num2=0;4'b1110_1101:num2=1;4'b1110_1011:num2=2;4'b1110_0111:num2=3;4'b1101_1110:num2=4;4'b1101_1101:num2=5;4'b1101_1011:num2=6;4'b1101_0111:num2=7;4'b1011_1110:num2=8;4'b1011_1101:num2=9;default:num2=num2;endcaseendif(i==3) //将第三个按下的按键值存入num3 begincase ({keyr,keyc})4'b1110_1110:num3=0;4'b1110_1101:num3=1;4'b1110_1011:num3=2;4'b1110_0111:num3=3;4'b1101_1110:num3=4;4'b1101_1101:num3=5;4'b1101_1011:num3=6;4'b1101_0111:num3=7;4'b1011_1110:num3=8;4'b1011_1101:num3=9;default:num3=num3;endcaseendif(i==4) //将第四个按下的按键值存入num4 begincase ({keyr,keyc})4'b1110_1110:num4=0;4'b1110_1101:num4=1;4'b1110_1011:num4=2;4'b1110_0111:num4=3;4'b1101_1110:num4=4;4'b1101_1101:num4=5;4'b1101_1011:num4=6;4'b1101_0111:num4=7;4'b1011_1110:num4=8;4'b1011_1101:num4=9;default:num4=num4;endcaseendendendalways @(posedgeclkh) //设置部分beginif(w==1)//设置时间begin Hour=num1*10+num2; Minute=num3*10+num4; end else if(p==1) //设置闹钟时间begin Ahour=num1*10+num2; Aminute=num3*10+num4; endendalways @(posedgeclkh)//闹钟响beginif((hour==Ahour)&&(minute==Aminute)) ds=1; //当设置的闹钟时间与当前时间相同时发出警报else ds=0;endendmodule。

WHEN "1110" => SEG_DA<=x"79";
WHEN "1111" => SEG_DA<=x"00";
END CASE;
END PROCESS;
U1 : CNT10 PORT MAP (CLK=>CLK5,RST=>RST1,CNT_VAL=>SEG_BUF1,COUT=>COUT(0),CIN=>'1');
SIGNAL SEG_TEMP:STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL COUT:STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL CLK:STD_C;
BEGIN
PROCESS (CLK3)
BEGIN
END PROCESS;
PROCESS (SEG_TEMP)
BEGIN
CASE SEG_TEMP IS
WHEN "0000" => SEG_DA<=x"3F";
WHEN "0001" => SEG_DA<=x"06";
);
END TIMER;
ARCHITECTURE ADO OF TIMER IS
COMPONENT CNT10
PORT(CLK:IN STD_LOGIC;
RST:IN STD_LOGIC;
CIN:IN STD_LOGIC;
CNT_VAL:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);

module s60 (/*******************************************///输入PORT 说明/*******************************************/input wire pin_clk_in , //输入时钟input wire pin_rst_n , //输入复位input wire pin_s_set , //秒设定input wire pin_m_set , //分设定input wire pin_h_set , //shi设定/*******************************************///输出PORT 说明/*******************************************/output wire [2:0] pin_sel , //输出8位数码管子3-8选择线output wire [7:0] pin_disp_led //输出8位数码管子);parameter U_DLY = 1;/****************************************************************************** **/// Counter/****************************************************************************** **/wire [31:0] counter_32 ; count32u_counter_32 (.asyn_clr_n ( pin_rst_n ) , //input, 异步清零信号.syn_clr ( !pin_rst_n ) , //input, 同步清零信号.clk ( pin_clk_in ) , //input, 全局时钟信号.en ( 1'b1 ) , //input, 计数使能信号, 计数器的门控开关，计数器关闭后，保持数值不变。

--分频器library ieee;use ieee.std_logic_1164.all;entity fenpin isport(clk:in std_logic;qH: buffer std_logic;qout:buffer std_logic);end entity;architecture c20 of fenpin isbeginprocess(clk)variable num : integer :=1;variable num1 : integer :=1beginif clk'event and clk='0'thenif(num=2)--0000000) --1HZ--10000000 to timer then num:=1;qout<=not qout;elsenum:=num+1;end if;if(num1=1)--000000) --1000HZ--10000 to weithen num1:=1;qH<=not qH;elsenum1:=num1+1;end if;end if;end process;end c20;--timerlibrary ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity Clock3 isport(clk:in std_logic;duan: out std_logic_vector(3 downto 0);wei: in std_logic_vector(2 downto 0);wei2: out std_logic_vector(2 downto 0));end entity;architecture clo of Clock3 issignal clk2:std_logic ;signal keys: std_logic_vector(2 downto 0);beginkeys<=key_h&key_m&key_s;clk2<=clk or flag;process(key_que)beginif key_que'event and key_que='0'then flag<= not flag;end if;end process;process(clk2,keys)--如果用拨码开关，就将clk2 改为clk begincase flag iswhen '0' =>if clk2'event and clk2='0'then ---正常计时if scn=59 and min=59 and hor=23then scn:=0;min:=0;hor:=0;elsif scn=59 and min=59then scn:=0;min:=0;hor:=hor+1;elsif scn=59then scn:=0;min:=min+1;else scn:=scn+1;end if;if min=59 ---整点报时500hzthen if scn=50 or scn=52 or scn=54 or scn=56 or scn=58then music_out<=musicL;else music_out<='0';end if;elsif min=0 and scn=0---整点报时1000HZthen music_out<=musicH;else music_out<='0';end if;end if;when '1' =>case keys iswhen "011" =>if hor=23then hor:=0;else hor:=hor+1;end if;--keys<="00";when "101" =>if min=59then min:=0;else min:=min+1;end if;-- keys<="00";when "110" =>if scn=59then scn:=0;else scn:=scn+1;end if;-- keys<="00";when others => null;-- keys<="00";end case;end case;h:=hor/10; --除法，特别是取余数运算会占用很多逻辑资源hH<="0000"+h;hL<="0000"+(hor-10*h);m:=min/10;mH<="0000"+m;mL<="0000"+(min-10*m);s:=scn/10;sH<="0000"+s;sL<="0000"+(scn-10*s);end process;end clo;去抖library ieee;--去抖电路use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity qudou isport( clk,key_in:in std_logic;key_out:out std_logic);end entity;architecture key_qudou of qudou isbeginprocess(clk)--5msvariable num: integer :=0;variable s: integer :=0;beginif clk'event and clk='0'thencase s iswhen 0 =>key_out<='1';if key_in='0'then num:=num+1;--用状态机思路更清晰，但是程序体积更庞大if num=3then num:=0;s:=1;end if;else num:=0;end if;when 1 =>key_out<='0';if key_in='1'then s:=0;end if;when others=> null;end case;end if;end process;key_qudou;--顶层文件library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity Clock isport( clk:in std_logic;music_out:out std_logic;key_in:in std_logic;keyh_in:in std_logic;keym_in:in std_logic;keys_in:in std_logic;duan: out std_logic_vector(6 downto 0);wei: buffer std_logic_vector(2 downto 0));end entity;architecture clo of Clock iscomponent fenpinport(clk:in std_logic;musicH: buffer std_logic;musicL: buffer std_logic;qH: buffer std_logic;qM: buffer std_logic;qout:buffer std_logic);end component;component counter_8port( clk: in std_logic;count: buffer std_logic_vector(2 downto 0));end component;component Clock3port(clk:in std_logic;key_que:in std_logic;key_h:in std_logic;key_m:in std_logic;key_s:in std_logic;musicH:in std_logic;musicL:in std_logic;music_out:out std_logic;duan: out std_logic_vector(3 downto 0);wei: in std_logic_vector(2 downto 0);wei2: out std_logic_vector(2 downto 0));end component;component seg7decport( din: in std_logic_vector(3 downto 0);qout:out std_logic_vector(6 downto 0));--a,b,c...f,gend component;component qudouport( clk,key_in:in std_logic;keyh_in:in std_logic;keym_in:in std_logic;keys_in:in std_logic;key_out:out std_logic;keyh_out:out std_logic;keym_out:out std_logic;keys_out:out std_logic);end component;beginu1: fenpin port map(clk=>clk,qH=>clkH,qout=>clkL,qM=>clkM,musicH=>c_m_H,musicL=>c_m_L);u2: counter_8 port map(clk=>clkH,count=>wei_in);u3: seg7dec port map(din=>duan_in,qout=>duan);u4: Clock3 port map(clk=>clkL,duan=>duan_in,wei=>wei_in,wei2=>wei,key_que=>key0,key_h=>key1,key_m=>key2,key_s=>k ey3,musicH=>c_m_H,musicL=>c_m_L,music_out=>music_out);u5: qudou port map(clk=>clkM,key_in=>key_in,keyh_in=>keyh_in,keym_in=>keym_in,keys_in=>keys_in,key_out=>key0,keyh _out=>key1,keym_out=>key2,keys_out=>key3);end clo;。

六十进制计数器LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY CNT60 ISPORT(CLK,EN,CR :IN STD_LOGIC;CO : OUT STD_LOGIC;QH,QL :OUT STD_LOGIC_VECTOR(3 DOWNTO 0) );END CNT60;ARCHITECTURE a OF CNT60 ISSIGNAL QNH,QNL :STD_LOGIC_VECTOR(3 DOWNTO 0);BEGINPROCESS(CLK,CR)BEGINIF (CR='0')THENQNH<="0000";QNL<="0000";ELSIF (CLK'EVENT AND CLK='1') THENIF(EN='1') THENIF QNL=9 THENQNL<="0000";CO<='0';IF QNH=5 THENQNH<="0000";CO<='1';ELSEQNH<=QNH+1;CO<='0';END IF;ELSEQNL<=QNL+1;CO<='0';END IF ;END IF;END IF ;END PROCESS;QH<=QNH;QL<=QNL;END a;24进制计数器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity cnt24h isport(cp,en,rd :in std_logic;co :out std_logic;q1,q2 :out std_logic_vector(3 downto 0)); end cnt24h;architecture str of cnt24h issignal qn:std_logic_vector(7 downto 0);beginco<='1' when (qn=X"23" and en='1')else'0';process(cp,rd)beginif(rd='0')thenqn<=X"00";elsif(cp'event and cp='1') THENif en='1'thenif qn=X"23" then qn<=X"00";elsif qn(3 downto 0)=9 thenqn(3 downto 0)<="0000";if qn(7 downto 4)=2 thenqn(7 downto 4)<="0000";elseqn(7 downto 4)<=qn(7 downto 4)+1;end if;elseqn(3 downto 0)<=qn(3 downto 0)+1;end if;end if;end if;end process;q1<=qn(7 downto 4);q2<=qn(3 downto 0);end str;二选一选择器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity mux isport(clk,kp: in std_logic;sel: in std_logic;y: out std_logic);end mux;architecture behav of mux isbeginprocess(sel)begincase sel iswhen '0'=>y<=clk;when '1'=>y<=kp;when others=>y<=clk;end case;end process;end behav;主选模块library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity mux6 isport(cnthh,cnthl,cntmh,cntml,cntsh,cntsl: in std_logic_vector(3 downto 0);sel: in std_logic_vector(2 downto 0);cntout: out std_logic_vector(3 downto 0));end mux6;architecture behav of mux6 isbeginprocess(sel)begincase sel iswhen "000"=>cntout<=cntsl(3 downto 0);when "001"=>cntout<=cntsh(3 downto 0);when "010"=>cntout<=cntml(3 downto 0);when "011"=>cntout<=cntmh(3 downto 0);when "100"=>cntout<=cnthl(3 downto 0);when "101"=>cntout<=cnthh(3 downto 0);when others=>cntout<="0000";end case;end process;end behav;六选一数据选择library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity cnt6a isport(cp,reset: in std_logic;sel: out std_logic_vector(2 downto 0));end cnt6a;architecture behav of cnt6a issignal sec : std_logic_vector(2 downto 0);beginprocess(reset,cp)beginif(reset='0') thensec<="000";elsif(cp'event and cp='1') thenif(sec="101") thensec<="000";elsesec<=sec+1;end if;end if;end process;sel<=sec;end behav;BCD译码器LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY BCDDECODER ISPORT(BCD :IN STD_LOGIC_VECTOR(3 DOWNTO 0);SEGOUT :OUT STD_LOGIC_VECTOR(0 TO 6));END BCDDECODER;ARCHITECTURE a OF BCDDECODER ISBEGINPROCESS(BCD)BEGINCASE BCD ISWHEN"0000"=>SEGOUT<="1111110";WHEN"0001"=>SEGOUT<="0110000";WHEN"0010"=>SEGOUT<="1101101";WHEN"0011"=>SEGOUT<="1111001";WHEN"0100"=>SEGOUT<="0110011";WHEN"0101"=>SEGOUT<="1011011";WHEN"0110"=>SEGOUT<="1011111";WHEN"0111"=>SEGOUT<="1110000";WHEN"1000"=>SEGOUT<="1111111";WHEN"1001"=>SEGOUT<="1111011";WHEN OTHERS=>SEGOUT<="0000000";END CASE;END PROCESS;END a;去抖电路library ieee;use ieee.std_logic_1164.all;entity qudou isport(cp: in std_logic;key: in std_logic;cpo: out std_logic);end;architecture a of qudou issignal temp1,temp2: std_logic;beginprocess(cp)beginif(cp'event and cp='0') thentemp1<=temp2;temp2<=key;end if;end process;cpo<=cp and temp2 and (not temp1);end a;电路图如下。

1、秒计时器（second1）Library ieee;Use ieee.std_logic_1164.all;Use ieee.std_logic_arith.all;Use ieee.std_logic_unsigned.all;Entity second1 isPort(clk,set,reset:in std_logic;S1:in std_logic_vector(7 downto 0); ――置数端（秒）Sec:buffer std_logic_vector(7 downto 0); ――秒输出端Ensec:out std_logic); ――秒计时器的进位，用来驱动分计时器End;Architecture a of second1 isBeginProcess(clk,reset,set,s1)BeginIf reset='0' then sec<="00000000"; ――对秒计时器清0Elsif set='0' then sec<=s1; ――对秒计时器置s1的数Elsif clk'event and clk='1' thenif sec=59 then sec<="00000000";ensec<='1'; ――重复计数并产生进位else sec<=sec+1;ensec<='0'; 以驱动下一级end if;end if;End process;End;2、分计时器（minute1）Library ieee;Use ieee.std_logic_1164.all;Use ieee.std_logic_arith.all;Use ieee.std_logic_unsigned.all;Entity second1 isPort(clk,set,reset:in std_logic;S1:in std_logic_vector(7 downto 0); ――置数端（分）Sec:buffer std_logic_vector(7 downto 0); ――分输出端Ensec:out std_logic); ――分计时器的进位，用来驱动分计时器End;Architecture a of second1 isBeginProcess(clk,reset,set,s1)BeginIf reset='0' then sec<="00000000"; ――对分计时器清0Elsif set='0' then sec<=s1; ――对分计器置s1的数Elsif clk'event and clk='1' thenif sec=59 then sec<="00000000";ensec<='1'; ――重复计数并产生进位else sec<=sec+1;ensec<='0'; 以驱动下一级end if;end if;End process;End;3、时计时器（hour1）Library ieee;Use ieee.std_logic_1164.all;Use ieee.std_logic_arith.all;Use ieee.std_logic_unsigned.all;Entity hour1 isPort(clkh,set,reset:in std_logic;h1:in std_logic_vector(7 downto 0); ――置数端（时）hour:buffer std_logic_vector(7 downto 0); ――时输出端Enhour:out std_logic); ――时计时器的进位，用来驱动星期计时器End;Architecture a of hour1 isBeginProcess(clkh,reset,set,h1)BeginIf reset='0' then hour<="00000000"; ――对时计时器清0 Elsif set='0' then hour<=h1; ――对时计时器置h1的数Elsif clkh'event and clkh='1' thenif hour=23 then hour<="00000000";enhour<='1'; ――重复计数else hour<=hour+1;enhour<='0'; 并产生进位以驱动下一级end if;end if;End process;End;。