SOLDER JOINT RELIABILITY OF SN-AG-CU BGA COMPONENTS ATTACHED WITH EUTECTIC PB-SN SOLDER PASTEFay Hua1, Raiyo Aspandiar4, Tim Rothman2,Cameron Anderson3, Greg Clemons3, Mimi Klier21Intel, Materials Technology OperationSanta Clara, CA2Package Technology DevelopmentFolsom, CA3Intel, Assembly Technology DivisionChandler, AZ4Intel, System Manufacturing Technology DivisionHillsboro, ORABSTRACTIn transition to Pb-free electronics, component suppliers may need to carry dual- line production of Pb-free and Pb-containing components. This could cause extensive logistic problems in manufacturing. A total conversion to Pb-free components could be a solution for this problem. Therefore, solder joint reliability of Sn-Ag-Cu BGA components attached with eutectic Pb-Sn solder paste needs to be addressed.This paper presents the results of solder joint reliability evalu-ation of VFBGA (very fine pitch ball grid array) and SCSP (stacked chip scale package) Pb-free packages attached to printed circuit boards (PCBs) with eutectic Pb-Sn pastes. The packages were assembled under various reflow profiles using standard Pb-Sn assembly conditions. Peak reflow temperatures of 208°C and 222°C with a soak profile or a direct ramp up profile was used. The assemblies were subjected then to board level temperature cycling (-40°C to 125°C, 30 minutes per cycle) and drop testing. Detailed failure analysis is also presented.Key words: solder joints, reliability, BGAs, Pb-free, Pb-Sn and Sn-Ag-Cu solder compatibility.INTRODUCTIONAs the industry converts from lead to lead-free, there is expected to be a period where lead and lead-free materials will be used within the same factory, and maybe even to the same customer. In order to limit the line item explosion that could take place, as well as the potential for excursions within a factory environment (due to the use of Pb and Pb-free solder spheres on the same assembly line), an effort is being made by Intel to evaluate the technical feasibility of Sn-Ag-Cu BGAs attached with eutectic Pb-Sn solder paste to printed circuit boards, and the impacts of that material combination to solder joint reliability.Ideally, it would be beneficial for both the chip package manufac-turers and OEMs to only have one solder sphere material per line item. If the process and solder joints of Sn-Ag-Cu BGAs attached with eutectic Pb-Sn solder paste is technically feasible, it would allow an OEM customer to accept Pb-free BGA solder sphere packages, regardless of what attachment process and material are used by the OEM customer without concerns on solder joint reliability. While the electronic industry is very anxious to know if Sn-Ag-Cu BGA packages are compatible with eutectic PbSn solders paste attachment, there is only limited data available and the data is somewhat contradictory.Geoff Swan from Motorola [1] and Jasbir Bath from Solectron [2,3] evaluated backward compatibility as part of National Electronics Manufacturing Initiative (NEMI) Pb-free task force. BGA solder metallurgy was Sn-Ag-Cu and eutectic Sn-Ag for Motorola and Solectron, respectively. Composition of Sn-Ag-Cu solder BGA ball was Sn with 3.8 wt.% Ag and 0.7wt.% Cu. PBGA package solder ball pitch size was 1.27mm. The Sn-Ag solder sphere was reflowed at a peak temperature of 210°C, in which case BGA solder did not melt completely during reflow. The Sn-Ag-Cu BGA was reflowed under 220°C. While different plastic packages were evaluated and different test methods were adopted, the results suggested the solder joints made by Sn-Ag-Cu BGA balls or eutectic Sn-Ag balls and Pb-Sn pastes performed equivalently with classic Pb-Sn joints.Most recently, chip scale package (CSP) backward compatibility was evaluated as part of Japan's JEITA program [4]. Two compositions of Sn-Ag-Cu BGA balls were investigated, Sn-3.0wt.%, 0.5wt.% Cu and Sn -1.0w.% Ag, 0.5wt.% Cu. The packages were attached at 234°C peak temperature with relative long time above 183°C. Temperature cycle (-40°C to 125°C, 60 min. per cycle) test results showed that joints made by both kinds of Sn-Ag-Cu BGA ball with eutectic Pb-Sn attachment performed better than eutectic PbSn joints as soldering on OSP. But the Sn-Ag-Cu BGAs attached with Sn-37Pb solder joints on electro-less Ni and immersion Au surface finish, performed slightly worse than Pb-Sn solder joints, and similar to total Sn-Ag-Cu joints. Texas Instruments also evaluated Pb-free BGA joints backward compatibility internally [5] on Tape BGA packages. 235°C peak reflow profile was used for attaching Sn-Ag-Cu BGA balls to PCBs with eutectic Pb-Sn solder paste. Overall, in the case of 0.8mm pitch package, the reliability of solder joints on bare Cu with Sn-Ag-Cu BGA ball and Pb-Sn paste was slightly worse than Pb-Sn solder joints, while that of solders on electro-less Ni/Au was slightly better than Pb-Sn solder joints. However, in the case of 0.5mm pitch package, if BGA ball metallurgy is Sn-2.5Ag-1.0Bi-0.5Cu, the reliability of solder joints attached with Pb-Sn solder paste was much worse than Sn-37Pb BGA control solder joints.This study was done to assess the reliability of solder joints formed with Sn-Ag-Cu BGA ball terminals using the eutectic SnPb paste, under Intel recommended reflow conditions and comparing that with eutectic Pb-Sn solder joints. Both reflow profiles with peak temperature higher than 220°C (above BGA ball melting temperature) and below 220°C (below BGA ball melting tempera-ture) are evaluated. Detailed failure analysis and microstructure characterization is also stated.EXPERIMENTTest Vehicle DescriptionTwo high-density testing vehicles were used in the experiment,VFBGA and SCSP packages.The VFBGA package is comprised of a very thin core substrate,which is wire-bonded to the silicon die (see Figure 1). The VFBGA package used has a 1.0mm total package height and uses a 0.5mm pitch with 0.30mm diameter solder spheres measured before ball attach.The SCSP is a molded BGA package capable of accommodating two or more die. The scalability of the stacked package is limited only by die combinations and maximum height, (see Figure 2).The SCSP package has a 1.4mm total package height and uses a 0.8mm pitch with 0.40mm diameter solder spheres measured before ball attach.The PCB used for this evaluation is a 6 layer (1+4+1) FR4material, build up using µvias on resin-coated copper. This PCB is intended to emulate a PCB that would be used in a mobile communication device with total thickness of 0.8 to 1.0mm. Two surface finishes, electro-less Ni-Immersion Au and Entek Plus OSP, are used in this investigation. Each board has 10 component units. Units 1-5 have 100% via in pad (VIP) surface mount pads, and units 6-10 have non-VIP surface mount pads. The board size and component place-ments are shown in Figure 3.The package side pad metallization is electrolytic Ni and immersion Au. The package pad is solder mask defined.Figure 1: 0.5mm pitch VFBGA package description (a)schematic picture of package side view (b) die andpackage size in mm.Figure 2: 0.8mm pitch SCSP package description (a) schematic picture of package side view (b) die and package size in mm.Figure 3: Test PCB size in mm and component locations.Test MethodologyBoard Level Temperature CyclingTemperature cycling testing is performed to emulate thermal mechanical stresses imposed on the package and interconnects during usage. Tem-perature cycling test is performed using a -40°C to 125°C, 30 minute cycle period in an elevator-style, 2-chamber oven with less than 2 minutes transition between hot and cold zones. Discrete room temperature and cold readouts are performed every 250 cycles. Failure data and Weibull plots are generated. Test duration typically 1500-2000 cycles. The test goal is less than <5% failure at 800 cycles from Weibull plot at 95% confidence.Drop TestBoard level, not system level, drop test is performed to emulate stresses imposed on the package and interconnects during the dropping of a mobile communications device. The test is performed on a 0.43Kg metal sled onto hard rubber platform. The PCB is mounted with only corner support screws. Drops are performed with the units facing down, which is worst case from a height of 1.5m. The PCBs are dropped up to 50 times, and drops to failure arecharted. The drop test setup is shown in Figure 4. Statistical analysis was done to get mean time to failure for each process conditions.Figure 4: Drop test fixture.Assembly Process & Design of Experiment (DOE)The packages were surface mounted at a board subcontractor.All the assembled boards were inspected under X-ray for opens and shorts. Electrical continuity tests were performed on each component and the failing components were marked before the boards were shipped to Intel.Table 1 is the board assembly board build DOE matrix for the VFBGA and the SCSP components. The reasoning behind the choice of levels for each variable in the DOE matrix is given below.Board Surface Finish: Two surface finishes were investigated,Electro-less nickel-immersion gold (NiAu) and the Entek® Plus Organic Solderability Protectant (OSP). NiAu is the most common surface finish for mobile wireless today, and OSP is the most common surface finish for other mobile electronic products.Exp Legs Package / board finish ProfilePeak Temp.TAL (S)BWC 10.5vfBGA/NiAu Standard Ramp 222+/-490-120BWC 20.5vfBGA/NiAu Standard Ramp 208+/-460-90BWC 30.5vfBGA/NiAu Standard Soak 222+/-490-120BWC 40.5vfBGA/NiAu Standard Soak 208+/-460-90BWC 50.5vfBGA/OSP Standard Soak 222+/-490-120BWC 60.5vfBGA/OSP Standard Ramp 208+/-460-90BWC 70.5vfBGA/OSP Standard Soak 208+/-460-90BWC 80.8SCSP/NiAu Standard Ramp 222+/-490-120BWC 90.8SCSP/NiAu Standard Ramp 208+/-460-90BWC 100.8SCSP/NiAu Standard Soak 222+/-490-120BWC 110.8SCSP/NiAu Standard Soak 208+/-460-90BWC 120.8SCSP/OSP Standard Soak 222 +/-490-120BWC 130.8SCSP/OSP Standard Soak 208+/-460-90BWC 140.8SCSP/OSP Standard Ramp 208+/-460-90Pb Control 0.5vfBGA/NiAu Standard Ramp 208+/-460-90Pb Control0.8SCSP/NiAuStandard Ramp208+/-460-90Table 1: Experiment DOE.Solder Joint Metallurgy: BGA balls are Sn-4.0Ag-0.5Cu Pb-free solders. The solder paste used for assembly is eutectic Pb-Sn solders. Assemblies with eutectic Pb-Sn BGA ball attached with eutectic Pb-Sn solder paste on OSP, and electro-less nickel and immersion gold boards were used as control. The package side pad metallization is electrolytic plated Ni and flash Au.Reflow Profile: Two types of reflow profiles were investigated. One was the soak profile, which is typically used for Sn-Pb board assembly today. The temperature ramps up initial until it reaches a predeter-mined temperature and then soaks at this temperature for a while to burn off the paste volatile ingredients, and also to equilibrate the temperature across the board. Subsequent to this soak zone, the temperature then ramps up to the molten range for the solder. The other profile is a ramp profile, which is devoid of the soak zone described above. Ramp profiles are adopted when higher board throughputs are required through the reflow soldering oven.Peak Reflow Temperature: Two different peak reflow tempera-tures were investigated. The lower one, 208°C, was picked so the SnAgCu balls of the components would not completely melt or collapse. The SnAgCu balls have a melting point of ~217°C. The other peak reflow temperature, 222°C, was picked such that the SnAgCu balls would melt or collapse during the reflow soldering process. A tolerance of +/-4°C was set for the peak reflow temperature.Time Above Liquidus (TAL): Two different TAL (above 183°C)ranges were investigated. The shorter range was 60-90 seconds, and the longer range was 90-120 seconds. One of these two ranges is typically used in most board assembly processes today. The shorter range is beneficial for board throughput through the reflow oven,but may preclude complete homogenization of the solder ball composition after the solder paste has melted. The longer range will allow ample time for the solder composition throughout the ball to homogenize and avoid any elemental segregation.BWC are the packages with Sn-Ag-Cu BGA balls attached with Pb-Sn solder paste. FWC are the packages with Pb-Sn BGA balls attached with Sn-Ag-Cu solder paste. Pb-control is Pb-Sn BGA balls attached with Pb-Sn solder paste.Initial build suggested that the ramp profile with the lower peak reflow temperature (208°C) and the shorter time above liquidus (30-60 sec) did not result in acceptable solder joints for both the packages under evaluation. Hence, these two legs were dropped from theDOE matrix. Figure 5 depicts a cross-section of a defective solder joint. The solder paste deposit has reflowed but has not coalesced to form one contiguous solder ball joint.Figure 5: Solder joints made by 208°C peak/60-90TAL ramp profile.For each leg, 2 board panels were assembled. Each panel had 6boards, and each board has 10 component assembled on it.Therefore, the total number of packages assembled per leg was 120. The panel size was 8 inches by 10 inches, and its thickness was 0.9mm (0.035 inches). Round stencil apertures were used to match the geometry of the component lands. The stencils'openings were tapered for to promote uniform release of the solder paste during stencil snap-off. The stencil thickness is 5 mil for the 0.8mm pitchSCSP assemblies, and 4 mil for the 0.5mm pitch VFBGA assemblies, to avoid solder pulling away from the PCB during paste printing.RESULTSAssembly Paste Printing VolumeFigure 7 shows the results of solder paste printing for both package assemblies. Overall printing volume is quite consistent for each package type. The VFBGA package has significantly lower paste volume than SCSP, as indicated in the plots as a result of thin stencil and small opening.Assembly YieldThere were 14 defects for the VFBGA boards for a total package yield of 99.2%, and 99.9% for SCSP package assemblies over both surface finishes, Ni/Au and OSP. 2 shorts were confirmed onVFBGA packages by X-ray inspection. All other VFBGA opens were determined not to be related to surface mount process.There was a single open detected on SCSP assemblies. The openFigure 6: X-ray image of surface mount defect of SCSP solder joints. The arrow points out the excess solder ball caused by depletion of solder from an adjacent ball.Temperature CyclingFigure 8 shows the plotted total failure rate from weibull plot (95% confidence) at 800 cycles. The controls for both SCSP and VFBGA packages show failure rates not meeting the goal of < 5%at 800 cycles. While the solder joints (Sn-Ag-Cu ball with Pb-Sn attachment of SCSP packages on OPS boards) are meeting the goal at all the process conditions in the DOE, one leg in VFBGA assembly slightly missed the goal, that joint was assembled at 208°C, at 60 to 90 second TAL with ramp profile. The solder joints on electro-less Ni/immersion Au surface finished boards do not show a clear trend with various process conditions. Over all VFBGA packages shows higher failure rate compared to SCSP,especially the package processed at 208°C, 60 to 90 second TAL ramp profile.Drop TestingFigures 9 and 10 show the statistical analysis of drops to failure for SCSP and VFBGA packages. The mean drops to failure of all the legs are compared to the control condition (Pb-Sn BGAs attached with Pb-Sn solder paste on OSP boards).In the case of SCSP packages, all the assemblies on OSP boards have higher mean drops to failure than the control, while all the solder joints (Sn-Ag-Cu ball with Pb-Sn attachment joint electro-less Ni and immersion Au surface finish) are significantly worse than the control.In the case of VFBGA packages, while all the solder joints (Sn-Ag-Cu ball with Pb-Sn attachment) on electro-less Ni/ immersion Au perform slightly worse than control leg, only one leg in VFBGA assembly slightly missed the goal. That joint was assembled at 208°C,at 60 to 90 second TAL with ramp profile. All other VFBGA packages on OSP performed better than control units.solder joint caused by solder depleting from a solder ball and transferring to an adjacent ball, which increased in diameter. This defect was detected by X-ray and is shown in Figure 6.Figure 7: Solder printing volume results for VFBGA (top) and for SCSP (bottom).Failure AnalysisDetailed failure analysis has been done on pre-750 temperature cycles failures. There are three major failure modes:1.Clean interfacial separation at solder to board is shown in Figure 11. The failure is believed to be at interface of Ni-Sn intermetallics and Ni (P) layer.2.Via cracks were also found in early failed units. The via-cracking found in the early failures are due to non-uniform plating. The crack initiates at the bottom of the via where the plating is thin. Figure 13 shows an example of via cracking. This defect has since been corrected by the board manufacture.3.Failures also occurred at the solder joint to package side. The crack started at solder and propagated into intermetallics, or it remains within the solder but close to package intermetallics interface, as shown in Figure 12.Figure 8: SCSP and VFBGA package failure rates (% cumulative failures) of various process conditions at 800 temperature cycles (-40°C - 125°C, 30 min. per cycles).Figure 9: SCSP package number of drops to processed at various conditions.Figure 10: VFBGA package number of drops to failure processed at various conditions.DISCUSSIONThe trend for drop test early failures indicates that they are either due to via cracking or clean interfacial separation at solder to PCB. Detailed investigation has been done for clean interfacial separation of solder to PCB. It has been noticed that all the units with the same failure mode are on electroless Ni and immersion Au board surface. As expected, the failure was more profound in drop testing than temperature cycling test. The failure signature was confirmed to be "black pad" defect related. High phosphorus level at interface and "mud cracks" are detected at cracking interface (see Figure 14). The detailed failures and researches have been well documented by investigators [6-9].Figure 8 shows that most of the high early temperature cycle failure rates occurred when the packages were assembled to the board with 208°C, 60s to 90s above 183°C, ramp profile (no pre-soaking). The failure was more profound when it was on electro-less Ni and immersion Au surface boards. Cross section analysis shows that the joints are not completely mixed between Pb-free BGA ball (Sn-4.0Ag-0.5Cu) and attachment solders (Sn-37Pb) (see figure 15). Pb-phase from attachment Sn-37Pb solder is diffused through grain boundaries. In the case of OSP surface finishes, the Pb segregation does not seem responsible for the early failures observed in temperature cycle and drop testing. Figure 16 shows a cross section of a failed 0.5mm pitch VFBGA package with Sn-Ag-Cu BGA ball assembled with Sn-37Pb paste reflowed at 208°C, 60s to 90s above 183°C, ramp profile (no pre-soaking) on OSP board (after 8 drops). The failure is on PCB board side at the Cu-Sn intermetallics.Cu6Sn5was detected at both pad and solder side. In temperature cycling the early failure happened at package side, as shown in Figure 12. Most likely the failure is solder mask registration and bump skew related. The failure rate in the 0.5mm pitch VFBGA package assem-blies is higher than that in 0.8mm SCSP package assemblies. Likely causes for the failure were the small printed solder volume (4mil thick stencil) and rapid, low temperature reflow profile that leads limited time and force for bump self alignment.In the case of failed electro-less Ni and immersion Au surface finish, the failure is clean separation between the solder joint to board interface. However, the assemblies with total Pb-free joints, and joints with Sn-37Pb BGA ball attached with Sn-Ag-Cu solder paste on electro-less Ni and immersion Au surface processed at 250°C, show very low early failure rate. The temperature profile dependent failurerate was not reported elsewhere in the literature. Further investigation could help the electronic industry to better understand the "black pad" related electro-less Ni and immersions Au interfacial failures.Figure 11: Clean separation at board on a 0.8mm SCSP package (Pb-free BGA ball attached with Sn-37Pb solder paste) on electro-less Ni and immersion Au surface pro-cessed with 222°C and 90 to 120s above liquidus. This failure mode is inconsistent with typical temperature cycle failures, the failure was detected at 250 cycles readout.Figure 12: Solder crack at package interface of the 0.5mm VFBGA (Pb-free BGA ball attached with Sn-37Pb solder paste) on OSP board processed with 208°C and 60s to 90s above liquidus. The failure is located at package side solder joint close to the intermetallics. It was detected at500 cycles read out.Figure 13: Board via defect on 0.8mm SCSP package (Sn-37Pb control) on electro-less Ni and immersion Au surface processed with 208°C peak and 60 to 90s above liquidus. The failure was detected at 500 cycles read-out.Figure 14: Black pad cross section of solder joint failure at electro-less and immersion Au surface. The failure happens at Ni-Sn intermetallics and Ni(P) interface.Figure 15: Incomplete mixing seen on at 208°C, 60s to 90s above 183°C, ramp profile (no pre-soaking).Figure 16: Solder mask mis-registration seen on 0.5mm pitch VFBGA package with Sn-Ag-Cu BGA ball assembled with Sn-37Pb paste reflowed at 208°C, 60s to 90s above 183°C, ramp profile (no pre-soaking) on OSP board (after 8 drops).CONCLUSIONSNormal SMT assembly yields were observed. 0.5mm pitch VFBGA and 0.8mm pitch SCSP BGA Pb-free packages were assembled with eutectic Pb-Sn paste under Intel recommended reflow profiles. Yields were above 99.2% yield on both OSP and electro-less Ni and immersion Au PCB surfaces. This data suggests that board level reliability goals are met for Pb-free balls using Sn-37Pb paste on OSP board surface finish under certain process conditions. These conditions are when the Sn-Ag-Cu BGA ball completely melts and mixes with Sn-37Pb paste. The goals are defined as statically less than 5% failure at 800 temperature cycles, and mean drops to failure is equal or better than control Sn-37Pb solder joints. "Black pad" on electro-less Ni-Au and other board defects affected the data in this experiment. The Sn-Ag-Cu BGA balls and Pb-Sn solder paste assemblies are high risk (worse than Sn-Pb joints) under mechani-cal shock load when board defects are present.ACKNOWLEDGEMENTThe authors would like to thank Intel management's support,especially to Mike Garner, Vivek Bissessur, and Vivek Gupta. The authors also like to thank Chee-key Chung for his assistance.REFERENCES1.Geoff S., TS Chong, Linda Matsushita, Alan Woosley, Kennon Simmons, and Thomas Koschmieder, Motorola report - Development of Lead- and Halogen-free Peripheral Leaded and PBGA Components To Meet MSL3 at 260° Peak Reflow Profile .2.Jasbir Bath, Solectron/NEMI report, NEMI Lead-free and Tin -lead Solder Paste Evaluation .3.Jasbir Bath and Emmanuelle Crombez, Surface Mount Assem-bly Evaluations with Lead-Free Solder Paste , NEPCON East 2000.4.Japan JEITA Lead-free Project Report - Lead-free CSP Backward Comptibility , 2001, August.5.Texas Instrument company internal report.6.Mei, Z., Callery, P ., Fisher, D., Hua, F., and Glazer, J., Interfacial fracture mechanism of BGA packages on Electro-less Ni/Au ; Advances in Electronic Packaging 1997, Proc InterPack '97, Vol. 2, pp. 1543-1550.7.Mei, Z., Kaufmann, M., Eslambolchi, A., Johnson, P ., Brittle Interfacial Fracture of PBGA Packages Soldered on Electro-less Nickel / Immersion Gold ; Proceedings 48th Electronic Components & Tech-nology Conference , 1998, pp. 952-61.8.Mei, Z., Johnson, P ., Kaufmann, K., and Eslambolchi, A., Effect of Electro-less Ni/Immersion Au Plating Parameters on PBGA Solder Joint Attachment Reliability ; Proceedings of the 49th Electronic Compo-nents & Technology Conference , June 1999, San Diego, CA.9.Houghton, B. "ITRI Project on Electroless Nickel / Immersion Gold Joint Cracking", Proceedings IPC Printed Circuits Expo 99, March 16-19, Long Beach, CA, S18-4.First published in the pro ceedings o f the 2002 SMTA International Conference (September 22-26, Rosemont, IL).BIOGRAPHYIn 2000, Fay Hua joined Intel Corporation as a company metal-lurgy technologist. She is focusing on Pb-free flip chip pathfinding and other solder metallurgy related areas, such as Pb-free BGA conversion. She has authored and co-authored over 40 publications on Pb-free solders and received 2 US patents.Raiyo Aspandiar has been with Intel Corporation at the Boards and System Assembly facility since 1983. He was part of the team that introduced SMT to Intel and is currently part of the Lead- and Halogen-free Initiative within Intel. Raiyo has published more than 15 technical papers and holds five patents in the electronics packaging and manufacturing field.Cameron Anderson joined Intel Corporation in 1997 and is currently in the Wireless Communications & Computing Group /Assembly Technology Development (WCCG/ATD) Q&R Group.Timothy Rothman joined Intel Corporation in 1995 and is currently the package characterization manager for Flash Products Group. Mr.Rothman has published over 10 papers in conferences and journals on solder joint reliability and electronics packaging technology.Miriam Klier has been with Intel Corporation since 1995. She is currently working in the Flash Package Development Group. Her most recent job assignment was the lead-free program manager responsible for managing all of the lead-free program activities for the division.。
