BS62LV256SC-70中文资料

2M X 8 Bit / 1M X 16 Bit CMOS 3.3 Volt-only,Boot Sector Flash MemoryDocument Title2M X 8 Bit / 1M X 16 Bit CMOS 3.3 Volt-only, Boot Sector Flash MemoryRevision HistoryDate Remark Rev. No. History Issue0.0 Initial issue April 1, 2005 Preliminary0.1 Change Vcc_min from 2.7V to 3.0V May 12, 20052M X 8 Bit / 1M X 16 Bit CMOS 3.3 Volt-only,Boot Sector Flash Memory FeaturesSingle power supply operation- Regulated voltage range: 3.0 to 3.6 volt read and write operations for compatibility with high performance 3.3 volt microprocessorsAccess times:- 70/90 (max.)Current:- 9 mA typical active read current- 20 mA typical program/erase current- 200 nA typical CMOS standby- 200 nA Automatic Sleep Mode currentFlexible sector architecture- 16 Kbyte/ 8 KbyteX2/ 32 Kbyte/ 64 KbyteX31 sectors- 8 Kword/ 4 KwordX2/ 16 Kword/ 32 KwordX31 sectors- Any combination of sectors can be erased- Supports full chip erase- Sector protection:A hardware method of protecting sectors to prevent anyinadvertent program or erase operations within that sector. Temporary Sector Unprotect feature allows code changes in previously locked sectorsUnlock Bypass Program Command- Reduces overall programming time when issuingmultiple program command sequenceTop or bottom boot block configurations availableEmbedded Algorithms- Embedded Erase algorithm will automatically erase the entire chip or any combination of designated sectors and verify the erased sectors - Embedded Program algorithm automatically writes and verifies data at specified addressesTypical 100,000 program/erase cycles per sector20-year data retention at 125°C- Reliable operation for the life of the systemCFI (Common Flash Interface) compliant- Provides device-specific information to the system, allowing host software to easily reconfigure for different Flash devicesCompatible with JEDEC-standards- Pinout and software compatible with single-power-supply Flash memory standard- Superior inadvertent write protectionData Polling and toggle bits- Provides a software method of detecting completion of program or erase operationsReady / BUSY pin (RY / BY)- Provides a hardware method of detecting completion of program or erase operations (not available on 44-pin SOP)Erase Suspend/Erase Resume- Suspends a sector erase operation to read data from, or program data to, a non-erasing sector, then resumes the erase operationHardware reset pin (RESET)- Hardware method to reset the device to reading array dataPackage options- 44-pin SOP or 48-pin TSOP (I) or 48-ball TFBGAGeneral DescriptionThe A29L160A is a 16Mbit, 3.3 volt-only Flash memory organized as 2,097,152 bytes of 8 bits or 1,048,576 words of 16 bits each. The 8 bits of data appear on I/O0 - I/O7; the 16 bits of data appear on I/O0~I/O15. The A29L160A is offered in 48-ball FBGA,44-pin SOP and 48-Pin TSOP packages. This device is designed to be programmed in-system with the standard system 3.3 volt VCC supply. Additional 12.0 volt VPP is not required for in-system write or erase operations. However, the A29L160A can also be programmed in standard EPROM programmers.The A29L160A has the first toggle bit, I/O6, which indicates whether an Embedded Program or Erase is in progress, or it is in the Erase Suspend. Besides the I/O6 toggle bit, the A29L160A has a second toggle bit, I/O2, to indicate whether the addressed sector is being selected for erase. The A29L160A also offers the ability to program in the Erase Suspend mode. The standard A29L160A offers access times of 70 and 90ns, allowing high-speed microprocessors to operate without wait states. To eliminate bus contention the device has separate chip enable (CE), write enable (WE) and output enable (OE) controls.The device requires only a single 3.3 volt power supply for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations.The A29L160A is entirely software command set compatible with the JEDEC single-power-supply Flash standard. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices.Device programming occurs by writing the proper program command sequence. This initiates the Embedded Program algorithm - an internal algorithm that automatically times the program pulse widths and verifies proper program margin.A29L160A SeriesDevice erasure occurs by executing the proper erase command sequence. This initiates the Embedded Erase algorithm - an internal algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper erase margin. The Unlock Bypass mode facilitates faster programming times by requiring only two write cycles to program data instead of four.The host system can detect whether a program or erase operation is complete by observing the RY / BY pin, or by reading the I/O 7 (Data Polling) and I/O 6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or accept another command.The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The A29L160A is fully erased when shipped from the factory.The hardware sector protection feature disables operations for both program and erase in any combination of the sectors of memory. This can be achieved via programming equipment.The Erase Suspend/Erase Resume feature enables the user to put erase on hold for any period of time to read data from, or program data to, any other sector that is not selected for erasure. True background erase can thus be achieved. The hardware RESET pin terminates any operation in progress and resets the internal state machine to reading array data. The RESET pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the system microprocessor to read the boot-up firmware from the Flash memory.The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters the automatic sleep mode. The system can also place the device into the standby mode. Power consumption is greatly reduced in both these modes.Pin ConfigurationsSOPTSOP (I)A18A17A7A6A5A4A3A2A1A0CE VSS OE I/O 0I/O 14I/O 8I/O 7I/O 15(A-1)VSS BYTE A16A15A14A12A11A10A19A8A9A13A 29L 160A M1234567891011121314151629303132333435363738394041424344RESET WE 171819202122282726252423I/O 1I/O 9I/O 2I/O 10I/O 3I/O 11I/O 6I/O 13I/O 5I/O 12I/O 4VCCPin Configurations (continued)TFBGABlock DiagramPin DescriptionsAbsolute Maximum Ratings*Storage Temperature Plastic Packages. . . -65°C to + 150°C Ambient Temperature with Power Applied. -55°C to + 125°C Voltage with Respect to GroundVCC (Note 1) . . . . . . . . . . . . . . . . . . . . ……. . -0.5V to +4.0V A9, OE & (Note 2) . . . . . . . . . . . …. -0.5 to +12.5V All other pins (Note 1) . . . . . . . . . . …. . -0.5V to VCC + 0.5V Output Short Circuit Current (Note 3) . . . . . . . …. . 200mANotes:1. Minimum DC voltage on input or I/O pins is -0.5V. Duringvoltage transitions, input or I/O pins may undershoot VSS to -2.0V for periods of up to 20ns. Maximum DC voltage on input and I/O pins is VCC +0.5V. During voltage transitions, input or I/O pins may overshoot to VCC +2.0V for periods up to 20ns.2. Minimum DC input voltage on A9,OE and RESET is -0.5V. During voltage transitions, A9,OE and RESET may overshoot VSS to -2.0V for periods of up to 20ns.Maximum DC input voltage on A9 is +12.5V which may overshoot to 14.0V for periods up to 20ns.3. No more than one output is shorted at a time. Duration ofthe short circuit should not be greater than one second.*CommentsStresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of these specification is not implied or intended. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability.Operating RangesCommercial (C) DevicesAmbient Temperature (T A ) . . . . . . . . . . . ….. . . 0°C to +70°CExtended Range DevicesAmbient Temperature (T A )For –I series. . . . . . . . . . . . . . . . . . . . . . . . . . -25°C to +85°C For –U series . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°CVCC Supply VoltagesVCC for all devices . . . . . . . . . . . . . . . . . …...+3.0V to +3.6V Operating ranges define those limits between which the functionally of the device is guaranteed.Device Bus OperationsThis section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory location. The register is composed of latches that store the commands, along with the address and data information needed toexecute the command. The contents of the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. The appropriate device bus operations table lists the inputs and control levels required, and the resulting output. The following subsections describe each of these operations in further detail.Table 1. A29L160A Device Bus OperationsL = Logic Low = V IL , H = Logic High = V IH , V ID = 12.0 ± 0.5V, X = Don't Care, D IN = Data In, D OUT = Data Out, A IN = Address In Notes:1. Addresses are A19:A0 in word mode (BYTE =V IH ), A19: A -1 in byte mode (BYTE =V IL ).2. See the “Sector Protection/Unprotection” section and Temporary Sector Unprotect for more information.Word/Byte ConfigurationThe BYTE pin determines whether the I/O pins I/O15-I/O0 operate in the byte or word configuration. If the BYTE pin is set at logic ”1”, the device is in word configuration, I/O15-I/O0 are active and controlled by CE and OE.If the BYTE pin is set at logic “0”, the device is in byte configuration, and only I/O0-I/O7 are active and controlled by CE and OE. I/O8-I/O14 are tri-stated, and I/O15 pin is used as an input for the LSB(A-1) address function. Requirements for Reading Array DataTo read array data from the outputs, the system must drive the CE and OE pins to V IL. CE is the power control and selects the device. OE is the output control and gates array data to the output pins. WE should remain at V IH all the time during read operation. The BYTE pin determines whether the device outputs array data in words and bytes. The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory content occurs during the power transition. No command is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. The device remains enabled for read access until the command register contents are altered.See "Reading Array Data" for more information. Refer to the AC Read Operations table for timing specifications and to the Read Operations Timings diagram for the timing waveforms, l CC1 in the DC Characteristics table represents the active current specification for reading array data.Writing Commands/Command SequencesTo write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive WE and CE to V IL, and OE to V IH. For program operations, the BYTE pin determines whether the device accepts program data in bytes or words, Refer to “Word/Byte Configuration” for more information. The device features an Unlock Bypass mode to facilitate faster programming. Once the device enters the Unlock Bypass mode, only two write cycles are required to program a word or byte, instead of four. The “Word / Byte Program Command Sequence” section has details on programming data to the device using both standard and Unlock Bypass command sequence. An erase operation can erase one sector, multiple sectors, or the entire device. The Sector Address Tables indicate the address range that each sector occupies. A "sector address" consists of the address inputs required to uniquely select a sector. See the "Command Definitions" section for details on erasing a sector or the entire chip, or suspending/resuming the erase operation.After the system writes the autoselect command sequence, the device enters the autoselect mode. The system can then read autoselect codes from the internal register (which is separate from the memory array) on I/O7 - I/O0. Standard read cycle timings apply in this mode. Refer to the "Autoselect Mode" and "Autoselect Command Sequence" sections for more information.I CC2 in the DC Characteristics table represents the active current specification for the write mode. The "AC Characteristics" section contains timing specification tables and timing diagrams for write operations.Program and Erase Operation StatusDuring an erase or program operation, the system may check the status of the operation by reading the status bits on I/O7 - I/O0. Standard read cycle timings and I CC read specifications apply. Refer to "Write Operation Status" for more information, and to each AC Characteristics section for timing diagrams.Standby ModeWhen the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE input.The device enters the CMOS standby mode when the CE & RESET pins are both held at VCC ± 0.3V. (Note that this is a more restricted voltage range than V IH.) If CE and RESET are held at V IH, but not within VCC ± 0.3V, the device will be in the standby mode, but the standby current will be greater. The device requires the standard access time (t CE) before it is ready to read data.If the device is deselected during erasure or programming, the device draws active current until the operation is completed.I CC3 and I CC4 in the DC Characteristics tables represent the standby current specification.Automatic Sleep ModeThe automatic sleep mode minimizes Flash device energy consumption. The device automatically enables this mode when addresses remain stable for t ACC +30ns. The automatic sleep mode is independent of the CE,WE and OE control signals. Standard address access timings provide new data when addresses are changed. While in sleep mode, output data is latched and always available to the system. I CC4 in the DC Characteristics table represents the automatic sleep mode current specification.Output Disable ModeWhen the OE input is at V IH, output from the device is disabled. The output pins are placed in the high impedance state.RESET: Hardware Reset PinThe RESET pin provides a hardware method of resetting the device to reading array data. When the system drives the RESET pin low for at least a period of t RP, the device immediately terminates any operation in progress, tristates all data output pins, and ignores all read/write attempts for the duration of the RESET pulse. The device also resets the internal state machine to reading array data. The operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity.Current is reduced for the duration of the RESET pulse. When RESET is held at VSS ± 0.3V, the device draws CMOS standby current (I CC4 ). If RESET is held at V IL but not within VSS ± 0.3V, the standby current will be greater.The RESET pin may be tied to the system reset circuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firmware from the Flash memory.If RESET is asserted during a program or erase operation, the RY/BY pin remains a “0” (busy) until the internal reset operation is complete, which requires a time t READY (during Embedded Algorithms). The system can thus monitor RY/BYto determine whether the reset operation is RESET is asserted when a program or eraseoperation is not executing (RY/BYpin is “1”), the reset operation is completed within a time of t READY (not during Embedded Algorithms). The system can read data t RH after the RESET pin return to V IH .Refer to the AC Characteristics tables for RESET parameters and diagram.Table 2. A29L160A Top Boot Block Sector Address TableAddress Range (in hexadecimal) Sector A19 A18 A17 A16 A15 A14A13A12Sector Size (Kbytes/ Kwords) Byte Mode (x8)Word Mode (x16)SA0 0 0 0 0 0 X X X 64/32 000000 - 00FFFF 00000 - 07FFF SA1 0 0 0 0 1 X X X 64/32 010000 - 01FFFF 08000 - 0FFFF SA2 0 0 0 1 0 X X X 64/32 020000 - 02FFFF 10000 - 17FFF SA3 0 0 0 1 1 X X X 64/32 030000 - 03FFFF 18000 - 1FFFF SA4 0 0 1 0 0 X X X 64/32 040000 - 04FFFF 20000 - 27FFF SA5 0 0 1 0 1 X X X 64/32 050000 - 05FFFF 28000 - 2FFFF SA6 0 0 1 1 0 X X X 64/32 060000 - 06FFFF 30000 - 37FFF SA7 0 0 1 1 1 X X X 64/32 070000 - 07FFFF 38000 - 3FFFF SA8 0 1 0 0 0 X X X 64/32 080000 - 08FFFF 40000 - 47FFF SA9 0 1 0 0 1 X X X 64/32 090000 - 09FFFF 48000 - 4FFFF SA10 0 1 0 1 0 X X X 64/32 0A0000 - 0AFFFF 50000 - 57FFF SA11 0 1 0 1 1 X X X 64/32 0B0000 - 0BFFFF 58000 - 5FFFF SA12 0 1 1 0 0 X X X 64/32 0C0000 - 0CFFFF 60000 - 67FFF SA13 0 1 1 0 1 X X X 64/32 0D0000 - 0DFFFF 68000 - 6FFFF SA14 0 1 1 1 0 X X X 64/32 0E0000 - 0EFFFF 70000 - 77FFF SA15 0 1 1 1 1 X X X 64/32 0F0000 - 0FFFFF 78000 - 7FFFF SA16 1 0 0 0 0 X X X 64/32 100000 - 10FFFF 80000 - 87FFF SA17 1 0 0 0 1 X X X 64/32 110000 - 11FFFF 88000 - 8FFFF SA18 1 0 0 1 0 X X X 64/32 120000 - 12FFFF 90000 - 97FFF SA19 1 0 0 1 1 X X X 64/32 130000 - 13FFFF 98000 - 9FFFF SA20 1 0 1 0 0 X X X 64/32 140000 - 14FFFF A0000 - A7FFF SA21 1 0 1 0 1 X X X 64/32 150000 - 15FFFF A8000 - AFFFF SA22 1 0 1 1 0 X X X 64/32 160000 - 16FFFF B0000 - B7FFF SA23 1 0 1 1 1 X X X 64/32 170000 - 17FFFF B8000 - BFFFF SA24 1 1 0 0 0 X X X 64/32 180000 - 18FFFF C0000 - C7FFF SA25 1 1 0 0 1 X X X 64/32 190000 - 19FFFF C8000 - CFFFF SA26 1 1 0 1 0 X X X 64/32 1A0000 - 1AFFFF D0000 - D7FFF SA27 1 1 0 1 1 X X X 64/32 1B0000 - 1BFFFF D8000 - DFFFF SA28 1 1 1 0 0 X X X 64/32 1C0000 - 1CFFFF E0000 - E7FFF SA29 1 1 1 0 1 X X X 64/32 1D0000 - 1DFFFF E8000 - EFFFF SA30 1 1 1 1 0 X X X 64/32 1E0000 - 1EFFFF F0000 - F7FFF SA31 1 1 1 1 1 0 X X 32/16 1F0000 - 1F7FFF F8000 - FBFFF SA32 1 1 1 1 1 1 0 0 8/4 1F8000 - 1F9FFF FC000 - FCFFF SA3311111118/41FA000 - 1FBFFFFD000 - FDFFF SA34 1 1 1 1 1 1 1 X 16/8 1FC000 - 1FFFFF FE000 - FFFFFNote:Address range is A19 : A -1 in byte mode and A19 : A0 in word mode. See “Word/Byte Configuration” section.Table 3. A29L160A Bottom Boot Block Sector Address TableSector A19 A18 A17 A16 A15 A14A13A12Sector SizeAddress Range (in hexadecimal)(Kbytes/Kwords) Byte Mode (x8) Word Mode (x16) SA0 0 0 0 0 0 0 0 X 16/8 000000 - 003FFF 00000 - 01FFF SA1 0 0 0 0 0 0 1 0 8/4 004000 - 005FFF 02000 - 02FFF SA2 0 0 0 0 0 0 1 1 8/4 006000 - 007FFF 03000 - 03FFF SA3 0 0 0 0 0 1 X X 32/16 008000 - 00FFFF 04000 - 07FFF SA4 0 0 0 0 1 X X X 64/32 010000 - 01FFFF 08000 - 0FFFF SA5 0 0 0 1 0 X X X 64/32 020000 - 02FFFF 10000 - 17FFF SA6 0 0 0 1 1 X X X 64/32 030000 - 03FFFF 18000 - 1FFFF SA7 0 0 1 0 0 X X X 64/32 040000 - 04FFFF 20000 - 27FFF SA8 0 0 1 0 1 X X X 64/32 050000 - 05FFFF 28000 - 2FFFF SA9 0 0 1 1 0 X X X 64/32 060000 - 06FFFF 30000 - 37FFF SA10 0 0 1 1 1 X X X 64/32 070000 - 07FFFF 38000 - 3FFFF SA11 0 1 0 0 0 X X X 64/32 080000 - 08FFFF 40000 - 47FFF SA12 0 1 0 0 1 X X X 64/32 090000 - 09FFFF 48000 - 4FFFF SA13 0 1 0 1 0 X X X 64/32 0A0000 - 0AFFFF 50000 - 57FFF SA14 0 1 0 1 1 X X X 64/32 0B0000 - 0BFFFF 58000 - 5FFFF SA15 0 1 1 0 0 X X X 64/32 0C0000 - 0CFFFF 60000 - 67FFF SA16 0 1 1 0 1 X X X 64/32 0D0000 - 0DFFFF 68000 - 6FFFF SA17 0 1 1 1 0 X X X 64/32 0E0000 - 0EFFFF 70000 - 77FFF SA18 0 1 1 1 1 X X X 64/32 0F0000 - 0FFFFF 78000 - 7FFFF SA19 1 0 0 0 0 X X X 64/32 100000 - 10FFFF 80000 - 87FFF SA20 1 0 0 0 1 X X X 64/32 110000 - 11FFFF 88000 - 8FFFF SA21 1 0 0 1 0 X X X 64/32 120000 - 12FFFF 90000 - 97FFF SA22 1 0 0 1 1 X X X 64/32 130000 - 13FFFF 98000 - 9FFFF SA23 1 0 1 0 0 X X X 64/32 140000 - 14FFFF A0000 - A7FFF SA24 1 0 1 0 1 X X X 64/32 150000 - 15FFFF A8000 - AFFFF SA25 1 0 1 1 0 X X X 64/32 160000 - 16FFFF B0000 – B7FFF SA26 1 0 1 1 1 X X X 64/32 170000 - 17FFFF B8000 - BFFFF SA27 1 1 0 0 0 X X X 64/32 180000 - 18FFFF C0000 - C7FFF SA28 1 1 0 0 1 X X X 64/32 190000 - 19FFFF C8000 - CFFFF SA29 1 1 0 1 0 X X X 64/32 1A0000 - 1AFFFF D0000 - D7FFF SA30 1 1 0 1 1 X X X 64/32 1B0000 - 1BFFFF D8000 - DFFFF SA31 1 1 1 0 0 X X X 64/32 1C0000 - 1CFFFF E0000 - E7FFF SA32 1 1 1 0 1 X X X 64/32 1D0000 - 1DFFFF E8000 - EFFFF SA33 1 1 1 1 0 X X X 64/32 1E0000 - 1EFFFF F0000 - F7FFF SA34 1 1 1 1 1 X X X 64/32 1F0000 - 1FFFFF F8000 - FFFFF Note:Address range is A19 : A-1 in byte mode and A19 : A0 in word mode. See “Word/Byte Configuration” section.Autoselect ModeThe autoselect mode provides manufacturer and device identification, and sector protection verification, through identifier codes output on I/O7 - I/O0. This mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. However, the autoselect codes can also be accessed in-system through the command register. When using programming equipment, the autoselect mode requires V ID (11.5V to 12.5 V) on address pin A9. Address pins A6, A1, and A0 must be as shown in Autoselect Codes (High Voltage Method) table. In addition, when verifying sector protection, the sector address must appear on the appropriate highest order address bits. Refer to the corresponding Sector Address Tables. The Command Definitions table shows the remaining address bits that are don't care. When all necessary bits have been set as required, the programming equipment may then read the corresponding identifier code on I/O7 - I/O0.To access the autoselect codes in-system, the host system can issue the autoselect command via the command register, as shown in the Command Definitions table. This method does not require V ID. See "Command Definitions" for details on using the autoselect mode.Table 4. A29L160A Autoselect Codes (High Voltage Method)L=Logic Low= V IL, H=Logic High=V IH, SA=Sector Address, X=Don’t Care.Note: The autoselect codes may also be accessed in-system via command sequences.Sector Protection/UnprotectionThe hardware sector protection feature disables both program and erase operations in any sector. The hardware sector unprotection feature re-enables both program and erase operations in previously protected sectors.It is possible to determine whether a sector is protected or unprotected. See “Autoselect Mode” for details.Sector protection / unprotection can be implemented via two methods. The primary method requires VID on the RESET pin only, and can be implemented either in-system or via programming equipment. Figure 2 shows the algorithm and the Sector Protect / Unprotect Timing Diagram illustrates the timing waveforms for this feature. This method uses standard microprocessor bus cycle timing. For sector unprotect, all unprotected sectors must first be protected prior to the first sector unprotect write cycle. The alternate method must be implemented using programming equipment. The procedure requires a high voltage (V ID) on address pin A9 and the control pins.The device is shipped with all sectors unprotected.It is possible to determine whether a sector is protected or unprotected. See "Autoselect Mode" for details.Hardware Data ProtectionThe requirement of command unlocking sequence for programming or erasing provides data protection against inadvertent writes (refer to the Command Definitions table). In addition, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during V CC power-up transitions, or from system noise. The device is powered up to read array data to avoid accidentally writing data to the array.Write Pulse "Glitch" ProtectionNoise pulses of less than 5ns (typical) on OE, CE or WEdo not initiate a write cycle.Logical InhibitWrite cycles are inhibited by holding any one of OE=V IL, CE = V IH or WE = V IH. To initiate a write cycle, CE and WE must be a logical zero while OE is a logical one.Power-Up Write InhibitIf WE = CE = V IL and OE = V IH during power up, the device does not accept commands on the rising edge of WE. The internal state machine is automatically reset to reading array data on the initial power-up. Temporary Sector UnprotectThis feature allows temporary unprotection of previous protected sectors to change data in-system. The Sector Unprotect mode is activated by setting the RESET pin to V ID. During this mode, formerly protected sectors can be programmed or erased by selecting the sector addresses. Once V ID is removed from the RESET pin, all the previously protected sectors are protected again. Figure 1 shows the algorithm, and the Temporary Sector Unprotect diagram shows the timing waveforms, for this feature.Notes:1. All protected sectors unprotected.2. All previously protected sectors are protected once again.Figure 1. Temporary Sector Unprotect OperationFigure 2. In-System Sector Protect/Unprotect AlgorithmsCommon Flash Memory Interface (CFI)The Common Flash Interface (CFI) specification outlines device and host system software interrogation handshake, which allows specific vendor-specified software algorithms to be used for entire families of devices. Software support can then be device-independent, JEDEC ID-independent, and forward- and backward-compatible for the specified flash device families. Flash vendors can standardize their existing interface for long-term compatibility.This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to address 55h in word mode (or address AAh in byte mode), any time the device is ready to read array data. The system can read CFI information at the addresses given in Table 5-8. In word mode, the upper address bits (A7-MSB) must be all zeros. To terminate reading CFI data, the system must write the reset command.The system can also write the CFI query command when the device is in the autoselect mode. The device enters the CFI query mode, and the system can read CFI data at the addresses given in Table 5-8. The system must write the reset command to return the device to the autoselect mode.Table 5. CFI Query Identification StringAddresses (Word Mode)Addresses(Byte Mode)Data Description10h 11h 12h 20h22h24h0051h0052h0059hQuery Unique ASCII string “QRY”13h 14h 26h28h0002h0000hPrimary OEM Command Set15h 16h 2Ah2Ch0040h0000hAddress for Primary Extended Table17h 18h 2Eh30h0000h0000hAlternate OEM Command Set (00h = none exists)19h 1Ah 32h34h0000h0000hAddress for Alternate OEM Extended Table (00h = none exists) Table 6 System Interface StringAddresses (Word Mode)Addresses(Byte Mode)Data Description1Bh 36h 0027h VCC Min. (write/erase)I/O7- I/O4 : volt, I/O3- I/O0: 100 millivolt1Ch 38h 0036h VCC Max. (write/erase)I/O7- I/O4: volt, I/O3- I/O0: 100 millivolt1Dh 3Ah 0000h Vpp Min. voltage (00h = no Vpp pin present)1Eh 3Ch 0000h Vpp Max. voltage (00h = no Vpp pin present)1Fh 3Eh0004hTypical timeout per single byte/word write 2Nµs20h 40h0000hTypical timeout for Min. size buffer write 2Nµs (00h = not supported) 21h 42h 000Ah Typical timeout per individual block erase 2N ms22h 44h 0000h Typical timeout for full chip erase 2N ms (00h = not supported)23h 46h 0005h Max. timeout for byte/word write 2N times typical24h 48h 0000h Max. timeout for buffer write 2N times typical25h 4Ah 0004h Max. timeout per individual block erase 2N times typical26h 4Ch 0000h Max. timeout for full chip erase 2N times typical (00h = not supported)。

ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.DESCRIPTIONThe 1+51 IS62LV2568L and IS62LV2568LL are low powerand low V CC , 262,144-bit words by 8 bits CMOS static RAMs.They are fabricated using 1+51's high-performance CMOS technology. This highly reliable process coupled with innova-tive circuit design techniques, yields higher performance and low power consumption devices.When CE1 is HIGH or CE2 is LOW (deselected), the device assumes a standby mode at which the power dissipation can be reduced by using CMOS input levels.Easy memory expansion is provided by using two Chip Enable inputs, CE1 and CE2. The active LOW Write Enable (WE )controls both writing and reading of the memory.The IS62LV2568L and IS62LV2568LL are available in 32-pin 8*20mm TSOP-1, 8*13.4mm TSOP-1 and 48-pin 6*8mm TF-BGA.FEATURESAccess times of 55, 70, 100 nsLow active power: 126 mW (max, L, LL)Low standby power: 36 µW (max, L) and 7.2µW (max, LL) CMOS standbyLow data retention voltage: 1.5V (min.) Available in Low Power (-L) and Ultra-Low Power (-LL)Output Enable (OE ) and two Chip Enable TTL compatible inputs and outputs Single 2.7V-3.6V power supplyAvailable in the 32-pin 8x20mm TSOP-1, 32-pin 8x13.4mm TSOP-1 and 48-pin 6*8mm TF-BGA2Integrated Circuit Solution Inc.IS62LV2568L IS62LV2568LLPIN CONFIGURATIONS32-Pin 8*20mm TSOP-1, 8*13.4mm STSOP-1PIN DESCRIPTIONSA0-A17Address Inputs CE1Chip Enable 1 Input CE2Chip Enable 2 Input OE Output Enable Input WE Write Enable Input I/O0-I/O7Data Input/Output NC No Connection Vcc Power GNDGround48-Pin 6*8mm TF-BGAOPERATING RANGERangeAmbient TemperatureV CCCommercial 0°C to +70°C 2.7V - 3.6V Industrial40°C to +85°C2.7V -3.6VIS62LV2568L IS62LV2568LLABSOLUTE MAXIMUM RATINGS (1)Symbol ParameterValueUnit V TERM Terminal Voltage with Respect to GND 0.5 to Vcc + 0.5V V CC Vcc related to GND0.3 to +4.0V T BIAS Temperature Under Bias 40 to +85°C T STG Storage Temperature 65 to +150°C P TPower Dissipation0.7WNotes:1.Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.CAPACITANCE (1)Symbol Parameter Conditions Max.Unit C IN Input Capacitance V IN = 0V 6pF C OUTOutput CapacitanceV OUT = 0V8pFNotes:1.Tested initially and after any design or process changes that may affect these parameters.DC ELECTRICAL CHARACTERISTICS (Over Operating Range)Symbol ParameterTest ConditionsMin.Max.Unit V OH Output HIGH Voltage V CC = Min., I OH = 1.0 mA 2.2 V V OL Output LOW Voltage V CC = Min., I OL = 2.1 mA0.4V V IH Input HIGH Voltage 2.2V CC + 0.3V V IL (1)Input LOW Voltage (1) 0.30.4V I LI Input Leakage GND ≤ V IN ≤ V CC 11µA I LOOutput LeakageGND ≤ V OUT ≤ V CC11µANotes:1.V IL =2.0V for pulse width less than 10 ns.TRUTH TABLEModeWE CE1CE2OE I/O OperationVcc Current Not Selected X H X X High-Z I SB , I SB (Power-down)X X L X High-Z I SB , I SBOutput Disabled H L H H High-Z I CC Read H L H L D OUT I CC WriteLLHXD INI CCIS62LV2568LIS62LV2568LLIS62LV2568L POWER SUPPLY CHARACTERISTICS(1)(Over Operating Range)-55-70-100Symbol Parameter Test Conditions Min.Max.Min.Max.Min.Max.UnitI CC Vcc Dynamic Operating V CC = Max.,Com. 40 30 20mASupply Current I OUT = 0 mA, f = f MAX Ind. 45 35 25I SB TTL Standby Current V CC = Max.,Com. 0.4 0.4 0.4mA(TTL Inputs)V IN = V IH or V IL,Ind. 1.0 1.0 1.0CE1≥ V IH or CE2 ≤ V IL, f = 0I SB CMOS Standby V CC = Max., f = 0Com. 35 35 35µACurrent (CMOS Inputs)CE1≥ V CC 0.2V,Ind. 50 50 50CE2 ≤ 0.2V,or V IN≥ V CC 0.2V, V IN≤ 0.2VNote:1.At f = f MAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.IS62LV2568LL POWER SUPPLY CHARACTERISTICS(1)(Over Operating Range)-55-70-100Symbol Parameter Test Conditions Min.Max.Min.Max.Min.Max.UnitI CC Vcc Dynamic Operating V CC = Max.,Com. 40 30 20mASupply Current I OUT = 0 mA, f = f MAX Ind. 45 35 25I SB TTL Standby Current V CC = Max.,Com. 0.4 0.4 0.4mA(TTL Inputs)V IN = V IH or V IL,Ind. 1.0 1.0 1.0CE1≥ V IH or CE2 ≤ V IL, f = 0I SB CMOS Standby V CC = Max., f = 0Com. 10 10 10µACurrent (CMOS Inputs)CE≥ V CC 0.2V,Ind. 15 15 15CE2 ≤ 0.2V,or V IN≥ V CC 0.2V, V IN≤ 0.2VNote:1.At f = f MAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.4Integrated Circuit Solution Inc.IS62LV2568LIS62LV2568LLREAD CYCLE SWITCHING CHARACTERISTICS(1)(Over Operating Range)-55-70-100Symbol Parameter Min.Max.Min.Max.Min.Max.Unit t RC Read Cycle Time55 70 100 nst AA Address Access Time 55 70 100nst OHA Output Hold Time10 10 15 nst ACE1CE1 Access Time 55 70 100nst ACE2CE2 Access Time 55 70 100nst DOE OE Access Time 30 35 50nst LZOE(2)OE to Low-Z Output5 5 5 nst HZOE(2)OE to High-Z Output 20025030nst LZCE1(2)CE1 to Low-Z Output10 10 10 nst LZCE2(2)CE2 to Low-Z Output10 10 10 nst HZCE(2)CE1 or CE2 to Low-Z Output020025030nsNotes:1.Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levelsof 0.4V to 2.2V and output loading specified in Figure 1.2.Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.AC TEST CONDITIONSParameter UnitInput Pulse Level0.4V to 2.2VInput Rise and Fall Times 5 nsInput and Output Timing 1.5Vand Reference LevelOutput Load See Figures 1 and 2AC TEST LOADSFigure 1Figure 26Integrated Circuit Solution Inc.IS62LV2568L IS62LV2568LLNotes:1.WE is HIGH for a Read Cycle.2.The device is continuously selected. OE , CE1 = VIL , CE2 = V IL .3.Address is valid prior to or coincident with CE1 LOW and CE2 HIGH transitions.AC WAVEFORMS(1,3)AC TEST LOADSREAD CYCLE NO.1(1,2)IS62LV2568L IS62LV2568LL-55-70-100SymbolParameter Min.Max.Min.Max.Min.Max Unit t WC Write Cycle Time 55 70 100 ns t SCE 1CE1 to Write End 45 65 80 ns t SCE 2CE2 to Write End45 65 80 ns t AW Address Setup Time to Write End 45 65 80 ns t HA Address Hold from Write End 0 0 0 ns t SA Address Setup Time 0 0 0 ns t PWE (4)WE Pulse Width 50 55 70 ns t SD Data Setup to Write End 25 30 40 ns t HDData Hold from Write End0 0 0 ns t HZWE (3)WE LOW to High-Z Output 25 25 30ns t LZWE (3)WE HIGH to Low-Z Output555nsNotes:1.Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0.4V to2.2V and output loading specified in Figure 1.2.Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.3.The internal write time is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the Write.4.Tested with OE HIGH.WRITE CYCLE SWITCHING CHARACTERISTICS (1,2) (Over Operating Range, Standard and Low Power)AC WAVEFORMSWRITE CYCLE NO. 1 (WE Controlled )(1,2)IS62LV2568LIS62LV2568LLWRITE CYCLE NO. 2 (CE1, CE2 Controlled)(1,2)Notes:1.The internal write time is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW. All signals must be in valid statesto initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the Write.2.I/O will assume the HIGH-z state if OE =V IH.8Integrated Circuit Solution Inc.IS62LV2568L IS62LV2568LLDATA RETENTION SWITCHING CHARACTERISTICSSymbolParameterTest ConditionMin.Max.Unit V DRVcc for Data Retention See Data Retention Waveform 1.5 3.6V I DRData Retention CurrentVcc = 2.0V, CE1 ≥ Vcc 0.2VCom. (-L) 20µA Com. (-LL) 5µA Ind. (-L) 25µA Ind. (-LL)7µA t SDR Data Retention Setup Time See Data Retention Waveform 0ns t RDRRecovery TimeSee Data Retention Waveformt RCnsDATA RETENTION WAVEFORM (CE2 Controlled)DATA RETENTION WAVEFORM (CE1Controlled)IS62LV2568L IS62LV2568LLORDERING INFORMATION Commercial Range: 0°C to +70°C Speed (ns)Order Part No.Package55IS62LV2568L-55T8*20mm TSOP-1IS62LV2568L-55H8*13.4mm TSOP-1IS62LV2568L-55B6*8mm TF-BGA 70IS62LV2568L-70T8*20mm TSOP-1IS62LV2568L-70H8*13.4mm TSOP-1IS62LV2568L-70B6*8mm TF-BGA 100IS62LV2568L-100T8*20mm TSOP-1IS62LV2568L-100H8*13.4mm TSOP-1IS62LV2568L-100B6*8mm TF-BGA Industrial Range: -40°C to +85°CSpeed (ns)Order Part No.Package55IS62LV2568L-55TI8*20mm TSOP-1IS62LV2568L-55HI8*13.4mm TSOP-1IS62LV2568L-55BI6*8mm TF-BGA70IS62LV2568L-70TI8*20mm TSOP-1IS62LV2568L-70HI8*13.4mm TSOP-1IS62LV2568L-70BI6*8mm TF-BGA100IS62LV2568L-100TI8*20mm TSOP-1IS62LV2568L-100HI8*13.4mm TSOP-1IS62LV2568L-100BI6*8mm TF-BGAIntegrated Circuit Solution Inc.HEADQUARTER:NO.2, TECHNOLOGY RD. V, SCIENCE-BASED INDUSTRIAL PARK,HSIN-CHU, TAIWAN, R.O.C.TEL: 886-3-5780333Fax: 886-3-5783000BRANCH OFFICE:7F, NO. 106, SEC. 1, HSIN-TAI 5TH ROAD,HSICHIH TAIPEI COUNTY, TAIWAN, R.O.C.TEL: 886-2-26962140FAX: 886-2-2696225210Integrated Circuit Solution Inc.。

行号物料代码物料名称单位数量1CL.01.09.0045二极管（IN5819/1A/40V/0.4间距）个172 2CL.01.09.0046发光二极管（0603-绿灯）PLC个3,530 3CL.01.09.0048二极管（SMD BZT52-C11）PLC个2,306 4CL.01.09.0052二极管（MBR1535CT）个315CL.01.10.0043桥（DF06M/1A/600V(DB107/1A/700V)）个2,261 6CL.01.12.0005MOS管（SMD IRFR9024N）PLC个2,000 7CL.01.12.0006MOS管（SMD ST3407）PLC个448CL.01.13.0019三极管（SMD CAT810LTBI）PLC个2,881 9CL.01.13.0020三极管（SMD MMBT6427LT1/0.5A/40V）PLC个3,174 10CL.01.13.0022三极管（2SC2383）PLC个732 11CL.01.13.0025三极管（SMD MJD112 TO252）PLC用个1,964 12CL.01.14.0019稳压块（SMD LM2575S-5V）个4513CL.01.15.0019稳压管（SMD REF3020AIDBZ）PLC个3,164 14CL.01.15.0020稳压管（LM385BLP-1.2）个1,128 15CL.01.15.0026稳压管（SMD REF3040AIDBZ）个3416CL.01.15.0027稳压管（LM385BLP-2.5）个989 17CL.01.15.0028稳压管（P6KE170A）个9018CL.01.15.0029稳压管（P6KE200A）个800 19CL.01.16.0082集成电路（SMD SN74AHC32DR）PLC个2,050 20CL.01.16.0083集成电路（SMD SN74AHC14DR）PLC个4,628 21CL.01.16.0084集成电路（SMD DAC7612UB）PLC个214 22CL.01.16.0085集成电路（SMD SN74AHCIG14DBV）PLC个2823CL.01.16.0086集成电路（SMD ADS1110A0IDBVT）PLC个3,084 24CL.01.16.0087集成电路（SMD PCA82C250T）PLC个3,869 25CL.01.16.0088集成电路（SMD BS62LV256SC-70）PLC个2,54226CL.01.16.0089集成电路（SMD FM3164-S）PLC个2627CL.01.16.0090集成电路（SMD LM2675M-5.0）PLC个182 28CL.01.16.0091集成电路（SMD AT93C46-10SI-2.7）PLC个3,009 29CL.01.16.0092集成电路（SMD MCP2515-I/ST）PLC个2,297 30CL.01.16.0093集成电路（SMD SN74HC244DW）PLC个1,180 31CL.01.16.0094集成电路（SMD DG409DY）PLC个2,568 32CL.01.16.0095集成电路（TNY268P）个2,267 33CL.01.16.0096集成电路（ICL7662CPA）个420 34CL.01.16.0099集成电路（SMD ZT232LEEN）PLC个497 35CL.01.16.0101集成电路（无铅 SMD INA143UA）PLC个2,441 36CL.01.16.0105集成电路（无铅 SMD M29F102BB70K1）个7637CL.01.16.0111集成电路（SMD TL16C550DIPT）PLC个1,950 38CL.01.16.0112集成电路（SMD SN74AHC1G00DBV）PLC个2,500 39CL.01.16.0113集成电路（SMD SN74AHC1G08DBV）PLC个2,492 40CL.01.16.0114集成电路（SMD SN74HC273PW）PLC个1,500 41CL.01.16.0116集成电路（TNY264PN）个266 42CL.01.16.0117集成电路（TNY266PN）个270 43CL.01.16.0119集成电路（SMD FM24C256-S）PLC个1,185 44CL.01.16.0120集成电路（SMD ISL1208IB8）PLC个1,612 45CL.01.16.0121集成电路（SMD AM29F200BB-70EI）PLC个2,512 46CL.01.16.0122集成电路（SMD BS616LV1010EI-70）PLC个1,033 47CL.01.16.0123集成电路（SMD SN74AC573PW 窄体）PLC个5,000 48CL.01.16.0125集成电路（SMD INA126UA）个2,429 49CL.01.16.0126集成电路（SMD ADS1112IDGST）PLC个550CL.01.16.0127集成电路（SMD 74HC00）个4651CL.01.16.0128集成电路（SMD 74HCT245）个4552CL.01.16.0129集成电路（SMD CAT24WC64J）个853CL.01.16.0130集成电路（SMD SPC3）个4654CL.01.16.0131集成电路（SMD GAL16V8D）PLC个414 55CL.01.16.0135集成电路（SMD LM71CIMF）个6356CL.01.16.0136集成电路（SMD AM29F040B-70JC）个2457CL.01.16.0138集成电路（散新：SMD HY6264ALJ-10HY6264ALJ个4558CL.01.16.0159集成电路（SMD SN74HC273DW）PLC个150 59CL.01.16.0165集成电路（SMD AM29F040B-70JF）个750 60CL.01.16.0168集成电路（SMD LTC2627IDE-1#PBF）PLC个791CL.01.01.0012自恢复保险（RF30-135B/1.35A/30V）个325 2CL.01.01.0013自恢复保险（RF30-090B(0.9A/30V/RUE090)）个488 3CL.01.01.0014自恢复保险（RF30-300B 3A/30V）个334CL.01.01.0015保险慢融（CIS T2A/250V 5*20）个361 5CL.01.03.0002磁珠（SMD CBW453215U121B）个1,781 6CL.01.06.0011晶振（SMD 25.000MHZ/5V-50ppm）个553 7CL.01.06.0012晶振 KDS（32.768KHz/12.5pF/5ppm）个828CL.01.06.0013晶振（AT-38/25.000MHZ/30PF-30PPM）个109 9CL.01.06.0024晶振（25.000M 5V 4PIN）个165 10CL.01.24.0022共模电感（3.3UH/0.6A）个478 11CL.01.24.0023工字型电感（47UH/1.5A）个393 12CL.01.24.0033电感（10UH/3A）个2113CL.01.25.0007编码开关（R7H3-10RB-V-B）个3214CL.03.02.0159变压器（ELEE19-1）个295 15CL.03.02.0161变压器（EPEI22-2）个24016CL.03.02.0193变压器（EPEI22-1S）个274 17CL.03.02.0220变压器（EPEI22-3）个1018CL.03.02.0221变压器（EPEI22-4）个219CL.03.02.0230变压器（EPEI22-1T）个520CL.03.11.0038摇柄开关（UT-4-T2CK-2-H）个320 21CL.04.02.0068简牛插座（配菏泽线用）2*8个482 22CL.04.02.0077插座排母（F/H 2.0 2*18 SMT H=4.3 PA6T）个136 23CL.04.02.0078插座排母（F/H 2.0 2*10 SMT H=4.3 PA6T）个222 24CL.04.02.0079插座排母（F/H 2.54 1*17 H=5.0 PA6T）蜈蚣个562 25CL.04.02.0080插座排母（SMD F/H2.54 2*14 H=5.0SMT）个3626CL.04.02.0081插座排母（SMD F/H2.54 1*14H=5.0蜈蚣脚=5.0个415 27CL.04.03.0023短路针排针（P/H 2.0 2*10*2 L=17.5 PA6T）只354 28CL.04.03.0024短路针排针（P/H 2.0 2*18*2 L=17.5 PA6T）只256 29CL.04.03.0025短路针排针（P/H 2.54 1*17*2 L=30.0 PA6T）只566 30CL.04.03.0026短路针排针（P/H2.54 2*14*2 L=14.0）只4631CL.04.03.0027短路针排针（P/H 2.54 1*14*2 180D L=30.0 P只388 32CL.04.05.0059插接件（DR9 孔）个151CL.01.01.0004保险管（3A）个198 2CL.01.01.0018保险夹（5*20）个724CL.04.05.0050插接件（DP9 PIN-F 母头 PLC用）个301CL.01.17.0014CPU（SMD SAK-164CI-LM CA+）PLC个12CL.01.17.0015CPU（SMD AT89S51-24AI）PLC个252 3CL.01.17.0016CPU（SMD AT89S52-24AI）PLC个1,5464CL.01.17.0017电源芯片（SMD LM317MKTPR）PLC个3,002 5CL.01.17.0018CPU（SMD SAK-XE164FM-72F80L AA）PLC个36CL.01.17.0019CPU（SMD SAF-C164CI-LM CA+）PLC个128 7CL.01.17.0020电源芯片（TNY279P）个418CL.01.17.0021电源芯片（TNY278P）个329CL.01.17.0022电源芯片（B0505S-1W）个2910CL.01.17.0023CPU （SMD STC12C5A32S2）PLC个4311CL.01.17.0029CPU（SMD AT89S51-24AU）个1,600 12CL.01.17.0032CPU（SMD LM317DCYR）个2,463 13CL.01.18.0025光耦（SMD HCPL-0600-500E）个1,500 14CL.02.02.0075电容（334K/275V(0.33uF/275V)）个546 15CL.02.02.0076电容（3.3nF/250V）个709 16CL.02.02.0077电解电容（47uF/400V/20% D16*L20）个326 17CL.02.02.0078电解电容（33uF/400V/20% D16*L20）个284 18CL.02.02.0079电容（22nF/500V(630V)/20%/0.4）个246 19CL.02.03.0047法拉电容（0.33F/5.5V）个419 20CL.02.04.0064磁介电容（0805-15P/50V）PLC个2,611 21CL.02.07.0161电阻（RC-ML08W122JT/风华）（排阻）PLC个5022CL.02.07.0163电阻（YC164-JR-071K5L）网络电阻（阻排）PL个5,000 23CL.02.08.0056电阻（MF-25-680KΩ 1/4W）个348 24CL.02.08.0057电阻（MF-25-2MΩ 1/4W）个34925CL.02.08.0058电阻（RN-60-50KΩ 1/4W 0.1%）个433 26CL.02.08.0059电阻（RN-60-10KΩ 1/4W 0.1%）个443 27CL.02.08.0060电阻（RN-60-2KΩ 1/4W 0.1%）个324 28CL.02.08.0061电阻（RN-60-1KΩ 1/4W 0.1%）个307 29CL.02.08.0062电阻（RN-60-100Ω 1/4W 0.1%）个255 30CL.02.08.0063电阻（RN-60-250Ω 1/4W 0.1%）个454 31CL.02.08.0092精密直插电阻（500Ω 1/4W0.1%）个190 32CL.02.08.0097电阻（无铅 1/2W 200K）PLC个112 33CL.02.08.0098电阻（无铅 1/2W 30R）PLC个123 34CL.02.08.0112电阻（无铅1/4W 300Ω）个908 35CL.02.08.0113电阻（无铅1/2W 120Ω）个517 36CL.02.12.0004压敏电阻（FNR-07K390/39V/0.2）个980 37CL.02.12.0005压敏电阻（10D471K/470V）个607 38CL.02.13.0020水泥电阻（无铅RX27-3-7W-120ΩJ）个605 39CL.04.04.0157端子（DG129-5.08-03 绿）位8,130 40CL.04.04.0174端子（DG129-5.08-02P-13-07A(H)黑）位2,438 41CL.04.04.0175端子（DG129-5.08-03P-13-07A(H)黑）位4,630 42CL.04.04.0220端子（DG129-5.08-13P-13-60AH）条943CL.04.04.0221端子（DG129-5.08-08P-13-60AH）条944CL.04.04.0222端子（DG129-5.08-19P-13-60AH）条9调出仓库调入仓库调入仓位订单单号呆滞材料库材料库A呆滞材料库材料库A呆滞材料库材料库A呆滞材料库材料库A呆滞材料库材料库A呆滞材料库材料库A呆滞材料库材料库A呆滞材料库材料库A呆滞材料库材料库A呆滞材料库材料库A呆滞材料库材料库A呆滞材料库材料库A呆滞材料库材料库A呆滞材料库材料库A呆滞材料库材料库A呆滞材料库材料库A呆滞材料库材料库A呆滞材料库材料库A呆滞材料库材料库A呆滞材料库材料库A呆滞材料库材料库A呆滞材料库材料库A呆滞材料库材料库A呆滞材料库材料库A呆滞材料库材料库A呆滞材料库材料库A 呆滞材料库材料库A 呆滞材料库材料库A 呆滞材料库材料库A 呆滞材料库材料库A 呆滞材料库材料库A 呆滞材料库材料库A 呆滞材料库材料库A 呆滞材料库材料库A 呆滞材料库材料库A 呆滞材料库材料库A 呆滞材料库材料库A 呆滞材料库材料库A 呆滞材料库材料库A 呆滞材料库材料库A 呆滞材料库材料库A 呆滞材料库材料库A 呆滞材料库材料库A 呆滞材料库材料库A 呆滞材料库材料库A 呆滞材料库材料库A 呆滞材料库材料库A 呆滞材料库材料库A 呆滞材料库材料库A 呆滞材料库材料库A 呆滞材料库材料库A呆滞材料库材料库A 呆滞材料库材料库A 呆滞材料库材料库A 呆滞材料库材料库A 呆滞材料库材料库A 呆滞材料库材料库A 呆滞材料库材料库A 呆滞材料库材料库A 呆滞材料库材料库A 呆滞材料库材料库A 呆滞材料库材料库A 呆滞材料库材料库A 呆滞材料库材料库A 呆滞材料库材料库A 呆滞材料库材料库A 呆滞材料库材料库A 呆滞材料库材料库A 呆滞材料库材料库A 呆滞材料库材料库A 呆滞材料库材料库A 呆滞材料库材料库A 呆滞材料库材料库A 呆滞材料库材料库A 呆滞材料库材料库A呆滞材料库材料库A 呆滞材料库材料库A 呆滞材料库材料库A 呆滞材料库材料库A 呆滞材料库材料库A 呆滞材料库材料库A 呆滞材料库材料库A 呆滞材料库材料库A 呆滞材料库材料库A 呆滞材料库材料库A 呆滞材料库材料库A 呆滞材料库材料库A 呆滞材料库材料库A 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CSRV065V0PRoHs DeviceFeaturesESD Protect for 4 high-speed I/O channels. IEC61000-4-2 (ESD)±14kV(Contact),±18kV(Air). IEC61000-4-4 (FET)20A for I/O,80A for Power. Working voltage: 5VLow capacitance:1.3pF(Typ.). High component density.Mechanical dataCase: SC70-6L(SOT-363) standard package, molded plastic.Terminals: Solder plated, solderable per MIL-STD-750,method 2026. Mounting position: Any Weight: 0.0091 gram(approx.).Pin ConfigurationCircuit DiagramkV kV V A 1866.5ESD V DC I PP ESD _VDD °C °C 260 ( 10 sec)-55 to +125-55 to +85T SOL T j Lead soldering temperature Operating temperature ESD per IEC 61000-4-2(Air)Operating supply voltage Peak pulse current ( tp = 8/20 us)ParameterSymbolValueUnitMaximum Rating (at T A =25°C unless otherwise noted)ESD per IEC 61000-4-2(Contact)ESD per IEC 61000-4-2(Air)(VDD-GND)ESD per IEC 61000-4-2(Contact)(VDD-GND)Storage temperature DC voltage at any I/O pinT STG V IO(GND -0.5) to (VDD +0.5)3014°C VV5V RWM Reverse leakage current Reverse stand-Off voltage ParameterConditionsSymbol Min Typ Max UnitV RWM = 5 V, Pin 5 to Pin 2Pin 5 to Pin 2Electrical Characteristics (at T A =25°C unless otherwise noted)V PIN 5 = 5 V, V PIN 2 =0V ,V IO = 0~5V I RDiode breakdown voltage I R = 1 mA, Pin 5 to Pin 2uAV BD Forward voltageI F = 15 mA, Pin 2 to Pin 5V FV 1Clamping voltageI PP = 5 A, tp=8/20us,Any Channel Pin to GroundV CVIEC 61000-4-2 +6kV,Contact mode Any Channel Pin to Ground IEC 61000-4-2 +6kV,Contact moed VDD Pin to Ground9912.58.10.86Junction capacitanceV pin5 = 5V,V pin2= 0V, V IO =2.5V,f = 1MHz,Any Channel Pin to GroundC j 1.3pF1.6V pin5 = 5V,V pin2= 0V, V IO =2.5V f = 1MHz,Between Channel Pins 0.120.14V pin5 = 5V,V pin2= 0V, V IN =2.5Vf = 1MHz,Channel_x pin to ground - channel_y pin to ground0.050.07591VRATING AND CHARACTERISTIC CURVES (CSRV065V0P)% o f R a t e d p o w e r o r I P PAmbient temperature (°C)Fig. 1 - Power derating curveC l a m p i n g v o l t a g e ( V )Peak pulse current (A)0 4.5Fig. 2 - Clamping voltage vs. Peak pulse currentF o r w a r d v o l t a g e (V )Peak pulse current(A)Fig.3 - Forward voltage v.s. forward currentInput voltage (V)I n p u t c a p a c i t a n c e (p F )Fig.4 - Typical variation of C IN v.s. VIN01005025125751501020304050607080901001105.05.56.06.57.07.511112109876543204.55.05.56.06.57.07.54.03.53.02.52.01.51.00.50543210.00.20.40.60.81.01.21.41.61.82.0I n p u t c a p a c i t a n c e (p F )20Temperature (°C)Fig. 5 - Typical variation of C IN v.s. temperatureFig. 6 - Transmission line pulsing (TLP) measurement1.008040100601201.051.101.151.201.251.301.351.401.451.50T r a n s m i s s i o n l i n e p u l s i n g (T L P )c u r r e n t (A )Transmission line pulsing(TLP)voltage(V)01356247818141210864216T r a n s m i s s i o n l i n e p u l s i n g (T L P )c u r r e n t (A )Transmission line pulsing(TLP)voltage(V)Fig.7 -Transmission line pulsing (TLP) measurement001356910181412108642162478End W 1Reel Taping SpecificationSC70-6L (SOT-363)SC70-6L (SOT-363)BCdDD 2D 1SYMBOLA(mm)(inch)1.969 MIN.2.20 ± 0.102.40 ± 0.104.00 ± 0.101.55 ± 0.103.50 ± 0.051.75 ± 0.1050.0 MIN.13.0 ± 0.201.35 ± 0.104.00 ± 0.102.00 ± 0.058.00 ± 0.3014.4 MAX.178 ± 10.094 ± 0.0040.087 ± 0.0040.053 ± 0.0040.061 ± 0.0047.008 ± 0.0400.512 ± 0.008SYMBOL(mm)(inch)0.315 0.012±0.138 ± 0.0020.069 ± 0.0040.157 ± 0.0040.157 ± 0.0040.079 ± 0.0020.567 MAXEFPP 0P 1WW 1C05 = Device code X = Date Code Y = Control CodeSuggested PAD LayoutSIZE(inch)0.031(mm)0.800.351.300.0140.051SC70-6L(SOT-363)1.940.076E2.740.108B C D AMarking CodePart Number CSRV065V0PMarking CodeC05XYC05XY.123654Standard PackageCase Type Qty per Reel(Pcs)3000SC70-6L(SOT-363)Reel Size (inch)7。